CN105182377A - Receiver board card and receiver - Google Patents
Receiver board card and receiver Download PDFInfo
- Publication number
- CN105182377A CN105182377A CN201510520389.7A CN201510520389A CN105182377A CN 105182377 A CN105182377 A CN 105182377A CN 201510520389 A CN201510520389 A CN 201510520389A CN 105182377 A CN105182377 A CN 105182377A
- Authority
- CN
- China
- Prior art keywords
- data
- storage area
- write
- dual port
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/33—Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS
Abstract
The embodiment of the invention discloses a receiver board card and a receiver. According to the embodiment of the invention, a baseband processing module is used for obtaining first data according to a satellite digital intermediate frequency signal, enables the first data to be written into N double-ports RAMs, and transmits a first instruction to a positioning resolving module. The baseband processing module is also used for reading second data from the N double-ports RAMs when receiving a second instruction, wherein N is an integer greater than one. The positioning resolving module is used for reading the first data from the N double-ports RAMs through an EMIF bus when receiving the first instruction. According to the first and second data, the second data is written into the N double-ports RAMs through the EMIF bus, and the second instruction is transmitted to the baseband processing module. According to the embodiment of the invention, the capability of data interaction between the baseband processing module and the positioning resolving module is effectively improved through the EMIF bus and the N double-ports RAMs.
Description
Technical field
The present invention relates to technical field of satellite navigation, particularly relate to a kind of receiver board and receiver.
Background technology
In current global navigation satellite receiving system, mainly include and mainly include Chinese BDS (BeiDouNavigationSatelliteSystem, Beidou satellite navigation system), GPS of America (GlobalNavigationSatelliteSystem, GPS), Russia's GLONASS (GLONASS) and European galileo (Galileo), each satellite system has again multiple frequency signal, has been added together tens frequencies.For design can hold the multimode multi-frequency receiver of more multifrequency point, the Satellite Tracking passage in base band may reach hundreds of, and baseband processing module and positioning calculation module data interaction amount each time can reach about 10K.Satellite navigation receiver baseband processing module and positioning calculation module communication method mainly contain two kinds of modes: first kind of way: the CPU (CentralProcessingUnit, processor) in positioning calculation module is by the register in bus access baseband processing module; CPU in second way positioning calculation module is by the data of the single RAM (RandomAccessMemory, random access memory) in bus mode access baseband processing module.
Above-mentioned first kind of way, satellite data is latched in Parasites Fauna by baseband processing module at regular intervals, then the CPU in positioning calculation module is by the data in bus read-write register, therefore, bus data renewal rate in this mode is by the clock control of baseband processing module, communication efficiency is very low, generally maximum also can only reach tens traffic rate; In addition, all satellite channel registers are connected with address logic by a data selector, affect the success ratio of baseband processing module FPGA comprehensive wiring.
The above-mentioned second way, uses single RAM as the data buffering between bus and base band, and the fan-in of RAM during baseband processing module internal wiring can be caused on the one hand too large, on the other hand, tradition single port RAM only has a data address port, and read-write can not be carried out simultaneously, and communication efficiency is lower.In addition, the data of all satellite channels are all written in a RAM by baseband processing module needs the long period, bus utilization ratio when reducing communication, and when passage is abundant, likely can not meet the real-time processing time needed for Satellite Tracking.
To sum up, a kind of reliable and stable method is needed at present badly for realizing the data interaction between baseband processing module and positioning calculation module.
Summary of the invention
The embodiment of the present invention provides a kind of receiver board, in order to improve the data exchange capability between baseband processing module and positioning calculation module.
A kind of receiver board that the embodiment of the present invention provides, comprise radio-frequency module, baseband processing module and positioning calculation module, described radio-frequency module is connected with described baseband processing module, and described baseband processing module is connected by external memory interface EMIF bus with described positioning calculation module; Described baseband processing module comprises N number of dual port RAM; Described radio-frequency module is used for obtaining satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and described satellite digital intermediate-freuqncy signal is sent to described baseband processing module;
The described satellite digital intermediate-freuqncy signal that described baseband processing module is used for according to receiving obtains the first data, described first data is write in N number of dual port RAM, and sends the first instruction to described positioning calculation module; And when receiving the second instruction, from described N number of dual port RAM, read the second data; N be greater than 1 integer;
Described positioning calculation module is used for when receiving described first instruction, reads described first data by described EMIF bus from described N number of dual port RAM; According to described first data, obtain described second data, and by described EMIF bus by the described N number of dual port RAM of described second data write, and send the second instruction to described baseband processing module.
Preferably, described dual port RAM comprises the first reading-writing port and the second reading-writing port;
Described baseband processing module is used for by described first data by the described N number of dual port RAM of described first reading-writing port write, and from described N number of RAM, reads described second data by described first reading-writing port;
Described positioning calculation module is used for by described second data by the described N number of dual port RAM of described second reading-writing port write, and from described N number of dual port RAM, reads described first data by described second reading-writing port.
Preferably, the speed that described baseband processing module is read and write data by described first reading-writing port is controlled by the first clock signal;
The speed that described positioning calculation module is read and write data by described second reading-writing port is controlled by second clock signal.
Preferably, described dual port RAM comprises the first storage area and the second storage area;
Described baseband processing module also comprises the first read-write selection unit; Described first read-write selection unit is used for described first data selection ground N number of described first storage area of write or N number of described second storage area, and optionally reads described second data from N number of described first storage area or N number of described second storage area;
Described positioning calculation module also comprises the second read-write selection unit; Described second read-write selection unit is used for described second data selection ground N number of described first storage area of write or N number of described second storage area, and optionally reads described first data from N number of described first storage area or N number of described second storage area;
The storage area and described second that described first read-write selection unit writes the first data reads and writes selection unit, and to write the storage area of described second data different.
Preferably, described first read-write selection unit comprise with described N number of RAM one to one N number of internal logic control;
Described first read-write selection unit is used for described first data selection ground N number of described first storage area of write or N number of described second storage area, and optionally read described second data from N number of described first storage area or N number of described second storage area, comprising:
Described N number of internal logic controls, by writing logic, described first data selection is write N number of described first storage area or N number of described second storage area, and optionally reads described second data from N number of described first storage area or N number of described second storage area by reading logic.
Preferably, described second read-write selection unit comprises EMIF bus controller; Described baseband processing module also comprises RAM and selects logic;
Described second read-write selection unit is used for described second data selection ground N number of described first storage area of write or N number of described second storage area, and optionally read described first data from N number of described first storage area or N number of described second storage area, comprising:
Described EMIF bus controller selects logic by described second data selection ground N number of described first storage area of write or N number of described second storage area by described RAM, and optionally reads described first data from N number of described first storage area or N number of described second storage area.
Preferably, described first data comprise each satellite IQ passage accumulation amount, chip count value, code all count value, carrier cycle count value; Described second data comprise shift register taps word, shift register initial status word, shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.
Preferably, described baseband processing module is field programmable gate array module FPGA; Described positioning calculation module is digital signal processor DSP.
Preferably, described positioning calculation module comprises enhancement mode direct memory access EDMA controller;
Described EDMA controller reads described first data for controlling described EMIF bus from described N number of dual port RAM, and controls described EMIF bus by the described N number of dual port RAM of described second data write.
A kind of receiver that the embodiment of the present invention provides, comprises the receiver board described in antenna and above-described embodiment;
Described antenna, for receiving satellite navigation signals, and sends to described receiver board by described satellite navigation signals.
Receiver board in the embodiment of the present invention comprises radio-frequency module, baseband processing module and positioning calculation module, and radio-frequency module is connected with baseband processing module, and baseband processing module is connected by EMIF bus with positioning calculation module; Baseband processing module comprises N number of dual port RAM; Radio-frequency module is used for obtaining satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and described satellite digital intermediate-freuqncy signal is sent to baseband processing module; Baseband processing module is used for obtaining the first data according to satellite digital intermediate-freuqncy signal, the first data is write in N number of dual port RAM, and sends the first instruction to positioning calculation module; And when receiving the second instruction, from N number of dual port RAM, read the second data; N be greater than 1 integer; Positioning calculation module receives and is used for when receiving the first instruction, reads the first data by EMIF bus from N number of dual port RAM; According to the first data, obtain the second data, by EMIF bus, the second data are written in N number of dual port RAM, and send the second instruction to baseband processing module.In the embodiment of the present invention, baseband processing module and positioning calculation module adopt the data communication mode based on EMIF bus and N number of dual port RAM, baseband processing module can be read and write N number of dual port RAM in a parallel fashion simultaneously, effectively shorten the time of baseband processing module read-write RAM, improve the success ratio of baseband processing module FPFA comprehensive wiring; And, the ability of the data interaction between baseband processing module and positioning calculation module is effectively improve by EMIF bus and N number of dual port RAM.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of receiver board that Fig. 1 provides for the embodiment of the present invention;
The concrete structure schematic diagram of a kind of receiver board that Fig. 2 provides for the embodiment of the present invention;
A kind of data interaction schematic diagram that Fig. 3 provides for the embodiment of the present invention;
The connected mode schematic diagram of the dual port RAM in the EMIF bus that Fig. 4 provides for the embodiment of the present invention and FPGA;
The structural representation of a kind of receiver that Fig. 5 provides for the embodiment of the present invention.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
The structural representation of a kind of receiver board that Fig. 1 provides for the embodiment of the present invention, be applicable to navigation neceiver, this receiver board comprises the radio-frequency module 102, baseband processing module 103 and the positioning calculation module 104 that are connected with antenna 101, described radio-frequency module 102 is connected with described baseband processing module 103, described baseband processing module 103 is connected by EMIF (ExternalMemoryInterface, external memory interface) bus with described positioning calculation module 104; Described baseband processing module 103 comprises N number of dual port RAM;
Described satellite digital intermediate-freuqncy signal for obtaining satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and is sent to described baseband processing module 103 by described radio-frequency module 102;
Described first data, for obtaining the first data according to the described satellite digital intermediate-freuqncy signal received, write in N number of dual port RAM, and send the first instruction to described positioning calculation module 104 by described baseband processing module 103; When receiving the second instruction, from described N number of dual port RAM, read the second data; N be greater than 1 integer;
Described positioning calculation module 104, for when receiving described first instruction, reads described first data by described EMIF bus from described N number of dual port RAM; According to described first data, obtain described second data, by described EMIF bus, described second data are written in described N number of dual port RAM, and send the second instruction to described baseband processing module 103.
In the embodiment of the present invention, baseband processing module and positioning calculation module adopt the data communication mode based on EMIF bus and N number of dual port RAM, baseband processing module can be read and write N number of dual port RAM in a parallel fashion simultaneously, effectively shorten the time of baseband processing module read-write RAM, improve the success ratio of baseband processing module FPGA comprehensive wiring; And, the ability of the data interaction between baseband processing module and positioning calculation module is effectively improve by EMIF bus and N number of dual port RAM.
The satellite navigation signals that in the embodiment of the present invention, antenna receives can be the signal of multiple satellite navigation system, preferably, satellite navigation signals is one or several in following content: GPS (GlobalPositioningSystem, GPS), Beidou satellite navigation system (BeiDouNavigationSatelliteSystem, BDS), GPS (Global Position System) (GLONASS), Galileo satellite navigation (GALILEO).
In the embodiment of the present invention, after antenna receives satellite navigation signals, send it to the radio-frequency module in receiver board, radio-frequency module obtains satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and described satellite digital intermediate-freuqncy signal is sent to described baseband processing module, described baseband processing module obtains the first data according to the described satellite digital intermediate-freuqncy signal received.
In the embodiment of the present invention, described first data comprise each satellite IQ passage accumulation amount, chip count value, code all count value, carrier cycle count value; Described second data comprise shift register taps word, shift register initial status word, shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.
In the embodiment of the present invention, dual port RAM comprises the first reading-writing port and the second reading-writing port, thus make baseband processing module and positioning calculation module can be accessed N number of dual port RAM by different reading-writing port, particularly, described first data are write in described N number of dual port RAM by described first reading-writing port by baseband processing module, and from described N number of RAM, read described second data by described first reading-writing port; Positioning calculation module is used for by described second data by the described N number of dual port RAM of described second port write, and from described N number of dual port RAM, reads described first data by described second port.
Because baseband processing module and positioning calculation module can access N number of dual port RAM by different reading-writing port, therefore, the speed that baseband processing module and positioning calculation module read and write data also controls by different clock signals.
Particularly, the speed that baseband processing module is read and write data by described first reading-writing port is controlled by the first clock signal, the speed that positioning calculation module is read and write data by described second reading-writing port is controlled by second clock signal, thus achieving baseband processing module and the operating clock of positioning calculation module to dual port RAM is separate, read-write does not interfere with each other.Such as, data parallel writes in dual port RAM with the clock of 50M by baseband processing module, write rear positioning calculation module and can read data with the clock of 200M from dual port RAM, the two is without the need to keeping synchronous, thus make positioning calculation module can access dual port RAM at faster speed, effectively improve the efficiency of the access dual port RAM of positioning calculation module.
In the embodiment of the present invention, the first instruction can be the handshake that baseband processing module sends to positioning calculation module, and the second instruction can be the handshake that positioning calculation module sends to baseband processing module.
In the embodiment of the present invention, baseband signal processing module is can FPGA (FieldProgrammableGateArray, field programmable gate array module); Positioning calculation module can be DSP (DigitalSignalProcessors, digital signal processor).Receiver board based on DSP and FPGA has given full play to the data-handling capacity that Base-Band Processing process in FPGA is able to programme and DSP is powerful.
FPGA with DSP is connected by EMIF bus, realizes two-way communication.Particularly, after satellite data (the first data) after catching is written to N number of dual port RAM by FPGA, send a handshake to DSP, after DSP receives handshake, from N number of dual port RAM, read satellite data by EMIF bus, and obtain loop parameter value (the second data) according to satellite data.Second data are written in N number of dual port RAM by EMIF bus by DSP, and send a handshake to FPGA.After FPGA receives handshake, from N number of dual port RAM, take out the second data, with the parameter value according to each satellite channel of the second data point reuse, ensure the tight tracking to satellite-signal.
In the embodiment of the present invention, the data volume that the large I of N once upgrades according to base band satellite channel is arranged, and also should consider the fan-in fan-out size that FPGA connects up simultaneously.Such as, base band Satellite Tracking port number is M, and the total amount of data that every subchannel upgrades is Q, and each adjustment channel parameters data volume is S, data volume in so each RAM can design according to (Q+S)/N, and N, Q and S determine bit wide and the degree of depth of RAM.In the embodiment of the present invention, when N is 1, in FPGA, the fan-in of the wiring of RAM is maximum, is unfavorable for temporal constraint, therefore, preferably, N be greater than 1 integer.
Because Q data are written to after in dual port RAM by FPGA once, just send handshake to DSP, therefore, the value of port number M is larger, and the value of data total amount Q is just higher, and the time of FPGA write needed for data is longer, is difficult to satisfy the demands.For improving the data transmission efficiency between FPGA and DSP further, the storage area of each dual port RAM in FPGA is preferably divided into two parts by the embodiment of the present invention, i.e. the first storage area and the second storage area.Baseband processing module also comprises the first read-write selection unit, for described first data selection is write N number of described first storage area or N number of described second storage area, and optionally read described second data from N number of described first storage area or N number of described second storage area; Positioning calculation module also comprises the second read-write selection unit, for described second data selection is write N number of described first storage area or N number of described second storage area, and optionally read described first data from N number of described first storage area or N number of described second storage area.
In the embodiment of the present invention, the storage area and second that the first read-write selection unit writes the first data reads and writes selection unit, and to write the storage area of described second data different.If the first read-write selection unit is by N number of first storage area of described first data write, then correspondingly, the second read-write selection unit is by N number of second storage area of the second data write; If the first read-write selection unit is by N number of second storage area of described first data write, then correspondingly, the second read-write selection unit is by N number of first storage area of the second data write.
The concrete structure schematic diagram of a kind of receiver board that Fig. 2 provides for the embodiment of the present invention.As described above, the value of the N in the embodiment of the present invention can be arranged.Herein for convenience of the concrete structure of the receiver board explained in the embodiment of the present invention, two dual port RAMs in FPGA are only shown, i.e. dual port RAM 1 and dual port RAM 2.Wherein, dual port RAM 1 comprises storage area 1a and storage area 1b, and dual port RAM 2 comprises storage area 2a and storage area 2b.The similar of the structure of N number of dual port RAM and two dual port RAMs, can refer to the structure of two dual port RAMs, repeats no more herein.
Particularly, in the embodiment of the present invention, first read-write selection unit can comprise with N number of dual port RAM one to one N number of internal logic control, each internal logic control to comprise one read logic and one write logic, wherein, reading logic for reading data in a storage area of dual port RAM, writing logic for data being write in another storage area of dual port RAM.Described N number of internal logic controls, by writing logic, described first data selection is write N number of described first storage area or N number of described second storage area, and optionally reads described second data from N number of described first storage area or N number of described second storage area by reading logic.
Second read-write selection unit can be EMIF bus controller, wherein, a part of address wire in EMIF bus is connected with the address wire in dual port RAM, another part and the RAM in FPGA select logic to be connected, this part address wire can select all dual port RAMs by the mode of combinational logic successively sheet, thus realize selecting logic that described second data selection is write N number of described first storage area or N number of described second storage area by described RAM, and optionally read described first data from N number of described first storage area or N number of described second storage area.
DSP in the embodiment of the present invention comprises processor, can be carried out reading and the write of data by processor control EMIF bus.Preferably, EDMA (EnhancedDirectMemoryAccess can also be comprised in the embodiment of the present invention, enhancement mode direct memory access) controller, because EDMA controller has the ability of the backstage bulk data transfer independent of processor, therefore, reading and the write of data is carried out by EDMA controller control EMIF bus, effectively can reduce the utilization rate of the processor in DSP, give full play to the high speed performance of DSP, make processor that more resource can be had to have gone more multichannel satnav to resolve, reduce the cost of DSP type selecting.
A kind of data interaction schematic diagram that Fig. 3 provides for the embodiment of the present invention.Similarly, for convenience of the data exchange process explained in the embodiment of the present invention, two dual port RAMs in FPGA are only shown.The data exchange process of the data exchange process of N number of dual port RAM and two dual port RAMs is similar, can refer to two dual port RAMs and obtains, repeat no more herein.
As shown in Figure 3, FPGA comprises dual port RAM 1 and reading and the write of the control of dual port RAM 2, first internal logic for controlling data in dual port RAM 1, and the second internal logic controls reading and write for controlling data in dual port RAM 2; Wherein, first internal logic controls to write in storage area 1b by data by writing logic, from storage area 1a, read data by reading logic, the second internal logic controls to write in storage area 2b by data by writing logic, reads data by reading logic from storage area 2a; Or, first internal logic controls also to write in storage area 1a by data by writing logic, from storage area 1b, data are read by reading logic, second internal logic controls also to write in storage area 2a by data by writing logic, reads data by reading logic from storage area 2b.A kind of situation wherein is only shown in Fig. 3, and the embodiment of the present invention is not specifically limited this.The first signal processing unit can also be comprised, for receiving the handshake of DSP transmission and sending handshake to DSP in FPGA.
DSP comprises processor, EDMA controller, EMIF bus controller, can also comprise secondary signal processing unit, for receiving the handshake of FPGA transmission and sending handshake to FPGA.On the one hand, processor is used for, after secondary signal processing unit receives the handshake of FPGA transmission, starting EDMA controller, reading data by EMIF bus controller control EMIF bus from the dual port RAM of FPGA; On the other hand, processor is used for being write data into after in the dual port RAM of FPGA by EDMA controller, EMIF bus controller and EMIF bus, and instruction secondary signal processing unit sends handshake to FPGA, to notify that FPGA gets out data.
Below in conjunction with Fig. 3, the data interaction flow process between FPGA and DSP is described further.
FPGA by the catching of satellite, follow the tracks of, calculate and comprise each path in-phase branch road, quadrature branch coherent integration value and the code week satellite data such as counting, to be controlled by the first internal logic and satellite data is written to storage area 1b in two dual port RAMs and storage area 2b by logic of writing in the control of the second internal logic; After data write, FPGA sends a handshake by the first signal processing unit to DSP, is used for notifying that DSP reads data from the storage area 1b two dual port RAMs and storage area 2b.Processor in DSP is after determining that secondary signal processing unit receives the handshake of the first signal processing unit transmission in FPGA, start EDMA controller, by EMIF bus controller control EMIF bus, the mode of combinational logic is adopted to read data from the storage area 1b and storage area 2b of FPGA.Processor in DSP processes the data read, and the data such as carrier shift amount and chip offset that will generate, EMIF bus is sent to by EDMA controller, EMIF bus controller, and then by EMIF bus, adopt the mode of combinational logic to be written to storage area 1a and the storage area 2a of two dual port RAMs; After data write, the secondary signal processing unit in DSP sends a handshake to the first signal processing unit in FPGA, is used for notifying that FPGA has completed the write of data.After the first signal processing unit in FPGA receives handshake, from the storage area 1a and storage area 2a of two dual port RAMs, read data by the logic of reading in the first internal logic control and the second internal logic control.FPGA uses carrier frequency control word and the code frequency control word of Data Update M satellite channel in the storage area 1a and storage area 2a read, better to catch or tracking satellite signal.
Below the connected mode of the dual port RAM in EMIF bus in the embodiment of the present invention and FPGA is specifically introduced.
That select in the embodiment of the present invention is the FPGA of Xilinx, FPGA inner integrated block storage resource can be configured to N number of dual port RAM, access speed can reach hundreds of million.The dual port RAM of FPGA inside has two completely independently reading-writing port, the first reading-writing port and the second reading-writing port respectively, two reading-writing port share the storage space of a RAM, and there are independently address wire, data line, read-write control line, therefore, for any one RAM, both can be read and write data by the first reading-writing port, also can be read and write data by the second reading-writing port.In the embodiment of the present invention, DSP can pass through EMIF bus, and from the first reading-writing port access dual port RAM, FPGA by the second reading-writing port access dual port RAM, can achieve the storage space that DSP and FPGA shares dual port RAM.
The connected mode schematic diagram of the dual port RAM in the EMIF bus that Fig. 4 provides for the embodiment of the present invention and FPGA.Similarly, the EMIF bus for convenience in the explanation embodiment of the present invention and the connected mode of dual port RAM, only illustrate two dual port RAMs, i.e. RAM1 and RAM2 in FPGA.The connected mode of EMIF bus and N number of dual port RAM, can refer to EMIF bus and two dual port RAMs obtain, and repeats no more herein.
In the embodiment of the present invention, the bit wide of EMIF data bus E_DATA can be configured according to actual conditions, such as, can be configured to 8,16,32,64.Dual port RAM in the embodiment of the present invention includes the first reading-writing port and the second reading-writing port, pin corresponding to the first reading-writing port comprises data-in port DIA, data-out port DOA, address wire ADRRA, read/write select signal WEA, enable signal ENA, clock signal clk A, and pin corresponding to the second reading-writing port comprises data-in port DIB, data-out port DOB, address wire ADRRB, read/write select signal WEB, enable signal ENB, clock signal clk B.
The annexation of each pin in EMIF bus controller and dual port RAM is specifically introduced below in conjunction with Fig. 4.In the embodiment of the present invention, the pin of EMIF bus controller comprises EMIF data bus E_DATA, SOE signal, EMIF address bus E_ADDR, clock output signal E_CLKOUT1, address strobe control signal ADS, read-write control signal WE, chip selection signal CE, byte control BE.
As shown in Figure 4, EMIF data bus E_DATA is connected with the data-in port DIA of two dual port RAMs and data-out port DOA respectively by data selector, and is controlled to be read data from dual port RAM or data write dual port RAM by SOE signal.EMIF address bus E_ADDR is divided into a high position [22:13] address wire and low level [12:0] address wire two parts, wherein, high-order [22:13] address wire selects combinational logic to be connected with the sheet of dual port RAM, sheet selects combinational logic to be connected with the ENA of two dual port RAMs respectively, carries out data interaction by the way selection EMIF bus of combinational logic and which dual port RAM; Low level [12:0] address wire is connected with the address wire ADRRA of the first reading-writing port of dual port RAM, for accessing the whole storage spaces in RAM.Clock output signal E_CLKOUT1 in EMIF bus controller is connected with the clock signal clk A of the first reading-writing port of two dual port RAMs respectively, reads and writes the speed of dual port RAM for control DSP.ADS, WE, CE, BE signal is through the combinational logic circuit of FPGA inside, and whether on the one hand, select logic effective for control RAM, on the other hand, for being connected with the WEA of two dual port RAMs, control DSP is to the read-write capability of FPGA internal dual port RAM.
The internal logic specifically introduced in FPGA below in conjunction with Fig. 4 controls the annexation with dual port RAM.
In the embodiment of the present invention, FPGA comprises corresponding with dual port RAM 1 first and innerly read and write logic and logic is read and write in second inside corresponding with dual port RAM 2.First inner read-write logic and the second inner read-write logic are connected, for accessing the whole storage spaces in RAM with the address wire ADRRB of the second reading-writing port of dual port RAM 1 and dual port RAM 2 respectively.First inner read-write logic is connected with data-out port DOB with the data-in port DIB in dual port RAM 1 by first selector, second inner read-write logic is connected with data-out port DOB with the data-in port DIB in dual port RAM 2 by second selector, thus can realize by first selector and second selector control FPGA being read data from dual port RAM or data write dual port RAM.First inner read-write logic is connected with WEB, ENB in dual port RAM 1 respectively, and the second inner read-write logic is connected with WEB, ENB in dual port RAM 2 respectively.First inner read-write logic is also connected with the Clock Signal pin CLKB of dual port RAM 1 and dual port RAM 2 respectively with the second inner read-write logic, reads and writes the speed of dual port RAM for control FPGA.
In the embodiment of the present invention, the speed of accessing two dual port RAMs due to DSP is controlled by the clock output signal in EMIF bus controller, and FPGA accesses, and the speed of two dual port RAMs controls by the clock signal of its inside, therefore the operating clock of DSP and FPGA to dual port RAM is separate, and read-write does not interfere with each other.Such as, data parallel writes in dual port RAM with 50M clock by FPGA, and write rear DSP and can read data with the clock of 200M from dual port RAM, the two is without the need to keeping synchronous, thus make DSP can access dual port RAM at faster speed, effectively improve the efficiency of the access dual port RAM of DSP.
Receiver board in the embodiment of the present invention comprises radio-frequency module, baseband processing module and positioning calculation module, and radio-frequency module is connected with baseband processing module, and baseband processing module is connected by EMIF bus with positioning calculation module; Baseband processing module comprises N number of dual port RAM; Radio-frequency module is used for obtaining satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and described satellite digital intermediate-freuqncy signal is sent to baseband processing module; Baseband processing module is used for obtaining the first data according to satellite digital intermediate-freuqncy signal, the first data is write in N number of dual port RAM, and sends the first instruction to positioning calculation module; And when receiving the second instruction, from N number of dual port RAM, read the second data; N be greater than 1 integer; Positioning calculation module receives and is used for when receiving the first instruction, reads the first data by EMIF bus from N number of dual port RAM; According to the first data, obtain the second data, by EMIF bus, the second data are written in N number of dual port RAM, and send the second instruction to baseband processing module.In the embodiment of the present invention, baseband processing module and positioning calculation module adopt the data communication mode based on EMIF bus and N number of dual port RAM, baseband processing module can be read and write N number of dual port RAM in a parallel fashion simultaneously, effectively shorten the time of baseband processing module read-write RAM, improve the success ratio of baseband processing module FPGA comprehensive wiring; And, the ability of the data interaction between baseband processing module and positioning calculation module is effectively improve by EMIF bus and N number of dual port RAM.
The structural representation of a kind of receiver that Fig. 5 provides for the embodiment of the present invention, this receiver comprises antenna 501 and the receiver board 502 as described in above-described embodiment;
Described satellite navigation signals for receiving satellite navigation signals, and is sent to described receiver board 502 by described antenna 501.
It can be seen from the above: the receiver board in the embodiment of the present invention comprises radio-frequency module, baseband processing module and positioning calculation module, and radio-frequency module is connected with baseband processing module, and baseband processing module is connected by EMIF bus with positioning calculation module; Baseband processing module comprises N number of dual port RAM; Radio-frequency module is used for obtaining satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and described satellite digital intermediate-freuqncy signal is sent to baseband processing module; Baseband processing module is used for obtaining the first data according to satellite digital intermediate-freuqncy signal, the first data is write in N number of dual port RAM, and sends the first instruction to positioning calculation module; And when receiving the second instruction, from N number of dual port RAM, read the second data; N be greater than 1 integer; Positioning calculation module receives and is used for when receiving the first instruction, reads the first data by EMIF bus from N number of dual port RAM; According to the first data, obtain the second data, by EMIF bus, the second data are written in N number of dual port RAM, and send the second instruction to baseband processing module.In the embodiment of the present invention, baseband processing module and positioning calculation module adopt the data communication mode based on EMIF bus and N number of dual port RAM, baseband processing module can be read and write N number of dual port RAM in a parallel fashion simultaneously, effectively shorten the time of baseband processing module read-write RAM, improve the success ratio of baseband processing module FPGA comprehensive wiring; And, the ability of the data interaction between baseband processing module and positioning calculation module is effectively improve by EMIF bus and N number of dual port RAM.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a receiver board, it is characterized in that, comprise radio-frequency module, baseband processing module and positioning calculation module, described radio-frequency module is connected with described baseband processing module, and described baseband processing module is connected by external memory interface EMIF bus with described positioning calculation module; Described baseband processing module comprises N number of dual port RAM; Described radio-frequency module is used for obtaining satellite digital intermediate-freuqncy signal by carrying out process to the satellite navigation signals received, and described satellite digital intermediate-freuqncy signal is sent to described baseband processing module;
The described satellite digital intermediate-freuqncy signal that described baseband processing module is used for according to receiving obtains the first data, described first data is write in N number of dual port RAM, and sends the first instruction to described positioning calculation module; And when receiving the second instruction, from described N number of dual port RAM, read the second data; N be greater than 1 integer;
Described positioning calculation module is used for when receiving described first instruction, reads described first data by described EMIF bus from described N number of dual port RAM; According to described first data, obtain described second data, and by described EMIF bus by the described N number of dual port RAM of described second data write, and send the second instruction to described baseband processing module.
2. receiver board as claimed in claim 1, it is characterized in that, described dual port RAM comprises the first reading-writing port and the second reading-writing port;
Described baseband processing module is used for by described first data by the described N number of dual port RAM of described first reading-writing port write, and from described N number of RAM, reads described second data by described first reading-writing port;
Described positioning calculation module is used for by described second data by the described N number of dual port RAM of described second reading-writing port write, and from described N number of dual port RAM, reads described first data by described second reading-writing port.
3. receiver board as claimed in claim 2, it is characterized in that, the speed that described baseband processing module is read and write data by described first reading-writing port is controlled by the first clock signal;
The speed that described positioning calculation module is read and write data by described second reading-writing port is controlled by second clock signal.
4. receiver board as claimed in claim 1, it is characterized in that, described dual port RAM comprises the first storage area and the second storage area;
Described baseband processing module also comprises the first read-write selection unit; Described first read-write selection unit is used for described first data selection ground N number of described first storage area of write or N number of described second storage area, and optionally reads described second data from N number of described first storage area or N number of described second storage area;
Described positioning calculation module also comprises the second read-write selection unit; Described second read-write selection unit is used for described second data selection ground N number of described first storage area of write or N number of described second storage area, and optionally reads described first data from N number of described first storage area or N number of described second storage area;
The storage area and described second that described first read-write selection unit writes the first data reads and writes selection unit, and to write the storage area of described second data different.
5. receiver board as claimed in claim 4, is characterized in that, described first read-write selection unit comprise with described N number of RAM one to one N number of internal logic control;
Described first read-write selection unit is used for described first data selection ground N number of described first storage area of write or N number of described second storage area, and optionally read described second data from N number of described first storage area or N number of described second storage area, comprising:
Described N number of internal logic controls, by writing logic, described first data selection is write N number of described first storage area or N number of described second storage area, and optionally reads described second data from N number of described first storage area or N number of described second storage area by reading logic.
6. receiver board as claimed in claim 4, is characterized in that, described second read-write selection unit comprises EMIF bus controller; Described baseband processing module also comprises RAM and selects logic;
Described second read-write selection unit is used for described second data selection ground N number of described first storage area of write or N number of described second storage area, and optionally read described first data from N number of described first storage area or N number of described second storage area, comprising:
Described EMIF bus controller selects logic by described second data selection ground N number of described first storage area of write or N number of described second storage area by described RAM, and optionally reads described first data from N number of described first storage area or N number of described second storage area.
7. receiver board as claimed in claim 1, it is characterized in that, described first data comprise each satellite IQ passage accumulation amount, chip count value, code all count value, carrier cycle count value; Described second data comprise shift register taps word, shift register initial status word, shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.
8. receiver board as claimed in claim 1, it is characterized in that, described baseband processing module is field programmable gate array module FPGA; Described positioning calculation module is digital signal processor DSP.
9. receiver board as claimed in claim 1, it is characterized in that, described positioning calculation module comprises enhancement mode direct memory access EDMA controller;
Described EDMA controller reads described first data for controlling described EMIF bus from described N number of dual port RAM, and controls described EMIF bus by the described N number of dual port RAM of described second data write.
10. a receiver, is characterized in that, comprises antenna and as the receiver board as described in arbitrary in claim 1 to 9;
Described antenna, for receiving satellite navigation signals, and sends to described receiver board by described satellite navigation signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510520389.7A CN105182377B (en) | 2015-08-21 | 2015-08-21 | A kind of receiver board and receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510520389.7A CN105182377B (en) | 2015-08-21 | 2015-08-21 | A kind of receiver board and receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105182377A true CN105182377A (en) | 2015-12-23 |
| CN105182377B CN105182377B (en) | 2018-06-19 |
Family
ID=54904573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510520389.7A Active CN105182377B (en) | 2015-08-21 | 2015-08-21 | A kind of receiver board and receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105182377B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108226967A (en) * | 2016-12-15 | 2018-06-29 | 展讯通信（上海）有限公司 | GNSS signal tracking and device |
| CN111224877A (en) * | 2019-12-10 | 2020-06-02 | 中国航空工业集团公司西安航空计算技术研究所 | VL query method and device of AFDX switch |
| CN111398996A (en) * | 2020-03-17 | 2020-07-10 | 广州南方卫星导航仪器有限公司 | Surveying and mapping satellite navigation receiver |
| WO2022016946A1 (en) * | 2020-07-20 | 2022-01-27 | 长沙海格北斗信息技术有限公司 | Shared caching method, baseband processing unit, and chip thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| US20100332700A1 (en) * | 2000-02-03 | 2010-12-30 | Realtime Data Llc | Data storewidth accelerator |
| CN102760106A (en) * | 2011-04-28 | 2012-10-31 | 北京京师励耘教育科技有限公司 | PCI (peripheral component interconnect) academic data mining chip and operation method thereof |
| CN102832090A (en) * | 2012-08-29 | 2012-12-19 | 安徽华东光电技术研究所 | Heater assembly for space traveling wave tube and preparation method thereof |
| CN104597458A (en) * | 2015-01-22 | 2015-05-06 | 上海海积信息科技股份有限公司 | Receiver board card and navigation receiver |
-
2015
- 2015-08-21 CN CN201510520389.7A patent/CN105182377B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100332700A1 (en) * | 2000-02-03 | 2010-12-30 | Realtime Data Llc | Data storewidth accelerator |
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| CN102760106A (en) * | 2011-04-28 | 2012-10-31 | 北京京师励耘教育科技有限公司 | PCI (peripheral component interconnect) academic data mining chip and operation method thereof |
| CN102832090A (en) * | 2012-08-29 | 2012-12-19 | 安徽华东光电技术研究所 | Heater assembly for space traveling wave tube and preparation method thereof |
| CN104597458A (en) * | 2015-01-22 | 2015-05-06 | 上海海积信息科技股份有限公司 | Receiver board card and navigation receiver |
Non-Patent Citations (3)
| Title |
|---|
| 于凤芹等: "利用EDMA和DSP/BIOS实现高速数据搬移与处理", 《仪表技术与传感器》 * |
| 关红宾: "双口RAM设计调试", 《科技信息》 * |
| 杨龙等: "DSP EMIF与FPGA双口RAM高速通信实现", 《现代电子技术》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108226967A (en) * | 2016-12-15 | 2018-06-29 | 展讯通信（上海）有限公司 | GNSS signal tracking and device |
| CN108226967B (en) * | 2016-12-15 | 2021-08-20 | 展讯通信（上海）有限公司 | GNSS signal tracking method and device |
| CN111224877A (en) * | 2019-12-10 | 2020-06-02 | 中国航空工业集团公司西安航空计算技术研究所 | VL query method and device of AFDX switch |
| CN111398996A (en) * | 2020-03-17 | 2020-07-10 | 广州南方卫星导航仪器有限公司 | Surveying and mapping satellite navigation receiver |
| WO2022016946A1 (en) * | 2020-07-20 | 2022-01-27 | 长沙海格北斗信息技术有限公司 | Shared caching method, baseband processing unit, and chip thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105182377B (en) | 2018-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105182377A (en) | Receiver board card and receiver | |
| CN103116175B (en) | Embedded type navigation information processor based on DSP (digital signal processor) and FPGA (field programmable gata array) | |
| CN102831090B (en) | Address line for space-borne DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) communication interfaces and optimization method for address line | |
| US8612686B2 (en) | Resource pool managing system and signal processing method | |
| KR910010315A (en) | 2-way data transfer device | |
| CN205229465U (en) | Baseband chip and multimode GNSS receiver of multimode GNSS receiver | |
| CN102760111A (en) | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof | |
| CN103365602A (en) | Semiconductor memory circuit and data processing system using same | |
| CN103279309A (en) | DDR control device and method based on FPGA | |
| CN102567280A (en) | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) | |
| CN112416823A (en) | Sensor data read-write control method, system and chip in burst mode | |
| CN102436840A (en) | Digital radio frequency memory board | |
| CN101661429B (en) | Storage method of statistical information and device thereof | |
| CN101825997A (en) | Asynchronous first-in first-out storage | |
| CN110474727A (en) | Processing method, device, relevant device and storage medium based on uplink signal | |
| CN102654852A (en) | Asynchronous data reading/writing control method, device and system | |
| CN105608028A (en) | EMIF (External Memory Interface) and dual-port RAM (Random Access Memory)-based method for realizing high-speed communication of DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) | |
| CN101566941B (en) | FIFO storage unit based on static random access memory (SRAM) | |
| CN206431615U (en) | A kind of fifo controller of multichannel read-write multicapacity selection | |
| CN104052831A (en) | Data transmission method and device based on queues and communication system | |
| CN109376049B (en) | Performance test method of FPGA embedded block memory | |
| CN103135097B (en) | 16-channel double-mode radar digital down conversion method based on field programmable gate array (FPGA) | |
| CN103516627A (en) | Method and apparatus for transmitting and receiving data packets in multi-chip communication | |
| CN201859658U (en) | Embedded SDRAM (synchronous dynamic random access memory) module | |
| CN102253917B (en) | Serial peripheral interface (SPI) controller and data sending method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A receiver board and receiver Effective date of registration: 20220826 Granted publication date: 20180619 Pledgee: China Merchants Bank Co.,Ltd. Shanghai Branch Pledgor: SHANGHAI HIGH GAIN INFORMATION TECHNOLOGY Co.,Ltd. Registration number: Y2022310000205 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20230818 Granted publication date: 20180619 Pledgee: China Merchants Bank Co.,Ltd. Shanghai Branch Pledgor: SHANGHAI HIGH GAIN INFORMATION TECHNOLOGY Co.,Ltd. Registration number: Y2022310000205 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A receiver board and receiver Effective date of registration: 20230829 Granted publication date: 20180619 Pledgee: China Merchants Bank Co.,Ltd. Shanghai Branch Pledgor: SHANGHAI HIGH GAIN INFORMATION TECHNOLOGY Co.,Ltd. Registration number: Y2023310000499 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |