CN104009942A - Kilomega AFDX switch and switching method thereof - Google Patents
Kilomega AFDX switch and switching method thereof Download PDFInfo
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- CN104009942A CN104009942A CN201410268433.5A CN201410268433A CN104009942A CN 104009942 A CN104009942 A CN 104009942A CN 201410268433 A CN201410268433 A CN 201410268433A CN 104009942 A CN104009942 A CN 104009942A
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Abstract
The invention discloses a kilomega AFDX switch which comprises a switching structure based on a shared memorizer, a switching port, a storage access interface, a switch terminal interface, a global counter and a local counter. The switching structure comprises the shared memorizer which is a dual-port memorizer, and the bit width of a single port is 512 bits. By means of the shared memorizer structure, the data switching of a 24-port kilomega AFDX is achieved, the total transceiving bandwidth can reach 48 G, and the bandwidth demands of the avionics of a next generation can be met.
Description
Technical field
The present invention relates to avionics field, particularly a kind of gigabit AFDX switch and switching method thereof.
Background technology:
According to ARINC664 standard, AFDX switch and commercial Ethernet switch mainly contain that following some is different:
1) support based on virtual link clean culture and the multicast of (Virtual Link is called for short VL);
2) support the flow control strategy based on virtual link;
3) support two kinds of priority settings based on virtual link;
4) support the data buffer size configure based on port;
5) exchange process of switch has definite time of delay estimated;
6) have a terminal interface that meets AFDX standard.
These differences determined the switching fabric of AFDX exchange chip and the switching fabric of commercial exchange chip incomplete same.The routing table of first commercial exchange chip has become fixing virtual link allocation list, and Path selection will be according to the clean culture of virtual link information realization and Multicast function, and the traffic policy that secondly AFDX exchange chip has added based on virtual link is controlled and priority mechanism.The design of AFDX exchange chip switching fabric simultaneously will guarantee that frame has confirmable time delay in transmittance process.
The design of switch exchange chip internal structure can be divided into based on input rank with based on two kinds of structures of output queue (sharing storage).Switch architecture based on input rank is provided with buffering area for each input port.The Frame that input port enters is first cached in input port buffering area, forms communication input rank.The exchange control logic of switch, according to the state of output port, takes out Frame asynchronously from input rank, from the switching entity of switch, forwards output; Switch architecture based on output queue is provided with output buffer for each output port.The Frame that input port enters, directly, by exchange control logic, enters in the output buffer of output port, forms communication output queue.The output port of switch takes out Frame asynchronously from output queue, from communication port, exports, and realizes exchanges data.Output queue switch architecture adopts shared storage mode to realize conventionally.
AFDX switching engine is mainly supported 10M/100M speed at present, and because swap data amount increases, the exchange rate that improves AFDX switching engine becomes even more important, based on this demand, in the urgent need to a kind of gigabit AFDX switch.
Summary of the invention
For the deficiencies in the prior art, goal of the invention of the present invention is to provide a kind of gigabit AFDX switch, supports the AFDX switching engine of 24 mouthfuls of gigabit speed.
Goal of the invention of the present invention is achieved through the following technical solutions:
A kind of gigabit AFDX switch, comprise switching fabric, switching port, memory access interface, exchange termination interface, global counter, local counter based on shared storage, described switching fabric comprises shared storage, described shared storage is dual-ported memory, and the bit wide of single port is 512bits;
Described switching port is input to shared storage for the SGMII Ethernet data of input port is converted to 512bit parallel data; 512bit parallel data in shared storage is converted to the output of SGMII Ethernet data;
Described memory access interface is for the configuration information of reading external memory storage;
Described exchange termination interface for the communicating by letter of processor, complete the information interaction of MIB and processor;
Global counter is used for calculating global clock, completes the calculating of credit;
In the processing time of local counter for calculating individual frames, coordinate overall skill to count the calculating that device completes the information such as credit.
Preferably, described shared storage adopts fpga chip, and by 64 BRAM, being combined into a degree of depth is 2K, the dual-ported memory that bit wide is 1024bits.
According to above-mentioned feature, described switching fabric also comprises clock sharding unit, storage control, idle address pointer alignment, output queue scheduling, multicast counting unit;
Described clock sharding unit is for providing for sharing storage control to N input port and N the timing cycle that output port carries out the access of timeslice poll;
Described storage control for to input the request of sending with time time-card poll mode make arbitration, from the pointer alignment of idle address, take out an address blank, data are write to this address blank shared storage space pointed, and this address blank and other relevant informations are write in the output queue of corresponding output port;
Described shared storage control is used for time-card on time shared storage is carried out to poll access;
Described address blank pointer alignment is for the management of shared storage address blank;
Described output queue scheduler for time time-card poll mode from the output queue of each output port non-NULL, read memory address and other information of the frame being buffered, according to memory address, from shared storage space, read frame data and send to output port;
Counting when described multicast counting unit forwards for multichannel is controlled.
Another object of the present invention is to provide a kind of gigabit AFDX switch switching method, comprise following steps:
A), when input has Frame to arrive, input port is converted to 512bits data format by SGMII data; In switching fabric, according to virtual link BAG pre-configured the virtual link table reading in from memory access interface and Jitter, carry out the filtration statistics that credit filters statistics, carries out erroneous frame according to AFDX data packet format; Then input sends request, storage control with time time-card poll mode make arbitration;
B), the input that obtains control takes out an address blank from null pointer queue, unfiltered correct data frame is write to this address blank shared storage space pointed with 512bits bit wide, and this address blank and other relevant informations are write in the output queue of corresponding output port; Wherein other relevant informations comprise output port, multicast port number information, in the virtual link table information that these information are read in by memory access interface equally, obtain.For guaranteeing the integrality of data, write till the shared storage end time should write completely with single complete data packet.
C), at output, output queue scheduler is read memory address and other information of the frame being buffered from the output queue of each port non-NULL in the mode of clock poll, according to memory address, from shared storage, read frame data, and send to output port;
D), output port is converted to SGMII Ethernet data by 512bits bit wide data and sends out switch.
According to above-mentioned feature, described credit filters statistics and specifically comprises following steps:
E), system is when start, global counter starts counting, the local counter of frame in VL list item is clear 0, AC composes maximum permissible value Acmax=BAG
i+ J
i, switch;
F), when a frame arrives, the local Counter Value that deducts each VL by global counter is added the AC surplus of this VL, obtains the current credit AC of frame
i;
G) if current credit AC
ibe less than the maximum frame length of relevant link
this frame abandons, and all fields of this VL item remain unchanged;
If current credit is greater than
be less than ACmax, forward present frame, the count value that the local Counter Value of this VL of write-back is current global counter, write-back AC surplus is current credit AC
ideduct
If current credit AC
ibe greater than ACmax, composing current credit is Acmax, forwards present frame, the count value that the local Counter Value of this VL of write-back is current global counter, and write-back AC surplus is that current credit deducts
According to above-mentioned feature, the type of error of described erroneous frame comprises that crc error, frame length mistake, byte do not line up mistake, field of constants mistake, virtual link (VL) ID mistake, credit mistake.
Compared with prior art, the present invention can meet following requirement:
A) 24 1000Mbps AFDX switching ports, 100% full line speed;
B) whole switch bandwidth 48Gbps;
C) the total buffer memory 128 of switch;
D) support 2 grades of priority;
E) AFDX switch is at least supported 4096 VL, and the ID of each VL should be in 0～65535 scope;
F) technology time delay is less than 10us;
G) logic working frequency: 20ns.
In the present invention, according to the specificity analysis of AFDX switch and emulation, and consider the restriction of bandwidth, gigabit AFDX agreement switching engine has adopted the structure based on shared drive.The structure of employing based on sharing storage has following advantage:
1) shared memory architecture can guarantee deterministic time delay;
2) shared memory architecture is supported the forwarding of elongated bag;
3) shared memory architecture can can't harm filtration to super band data.
By adopting shared storage organization, realize gigabit AFDX exchanges data.
Accompanying drawing explanation
Fig. 1 is the general switching fabric logic diagram based on shared storage;
Fig. 2 is the structure chart of gigabit AFDX switch of the present invention.
Specific implementation method
For 24 port gigabit AFDX switches, its total transmitting-receiving bandwidth is 24*1G*2=48G.This just requires the memory bandwidth of switch is also 48G, adopts the storage resources of FPGA inside.
In the present invention, use the shared storage of dual-port, for single storage port, only need like this memory bandwidth of 24G, switch internal operating frequencies is the size of 50M and internal storage unit, the bit wide of design memory is 512bits, the memory bandwidth of single port can reach 512*50M=25.6G, the bandwidth of whole dual-ported memory is 51.2G, can meet the transmission bandwidth requirement of switch.
Because the memory block BRAM of FPGA inside is that to take a 36K be unit, the BRAM of a 36K is deformed into 1K*32 and uses, the dual-ported memory that needs 32 BRAM to be combined into a 1K (degree of depth) * 1024 (bit wide) uses.For extended buffer area size, can adopt 64 BRAM to be combined into the dual-ported memory of a 2K (degree of depth) * 1024 (bit wides).128 buffering areas are overall in switch inside, by all of the port, are shared.
Fig. 1 has provided the general switching fabric logic diagram based on shared storage.It is mainly comprised of idle address pointer alignment, storage control, shared storage, output queue and output queue scheduler etc.
Switching fabric working method based on shared storage is as described below.At input, when input has Frame to arrive, input sends request, scheduler with time time-card poll mode make arbitration.The input that obtains control takes out an address blank from null pointer queue, and frame data are write to this address blank shared storage space pointed, and this address blank and other relevant informations are write in the output queue of corresponding output port.At output, scheduler is read memory address and other information of the frame being buffered equally from the output queue of each port non-NULL in the mode of clock poll, read frame data and send to output port according to memory address from shared storage.
According to above discussion, Fig. 2 has provided and has adopted shared storage to realize the block diagram of gigabit AFDX switch.Comprise switching fabric, switching port, memory access interface, exchange termination interface, global counter, local counter based on shared storage, described switching fabric comprises shared storage, described shared storage is dual-ported memory, and the bit wide of single port is 512bits.
Described switching port is input to shared storage for the SGMII Ethernet data of input port is converted to 512bit parallel data; 512bit parallel data in shared storage is converted to the output of SGMII Ethernet data.
Described memory access interface is for the configuration information of reading external memory storage.
Described exchange termination interface for the communicating by letter of processor, complete the information interaction of MIB and processor.
Global counter is used for calculating global clock, completes the calculating of credit.
In the processing time of local counter for calculating individual frames, coordinate overall skill to count the calculating that device completes the information such as credit.
Its switching fabric also comprises clock sharding unit, storage control, idle address pointer alignment, output queue scheduling, multicast counting unit.
Described clock sharding unit is for providing for sharing storage control to N input port and N the timing cycle that output port carries out the access of timeslice poll.
Described storage control for to input the request of sending with time time-card poll mode make arbitration, from the pointer alignment of idle address, take out an address blank, data are write to this address blank shared storage space pointed, and this address blank and other relevant informations are write in the output queue of corresponding output port.
Described shared storage control is used for time-card on time shared storage is carried out to poll access.
Described address blank pointer alignment is for the management of shared storage address blank.
Described output queue scheduler for time time-card poll mode from the output queue of each output port non-NULL, read memory address and other information of the frame being buffered, according to memory address, from shared storage space, read frame data and send to output port.
Counting when described multicast counting unit forwards for multichannel is controlled.
When input has Frame to arrive, input port is converted to 512bits data format by SGMII data; In switching fabric, according to virtual link BAG pre-configured the virtual link table reading in from memory access interface and Jitter, carry out the filtration statistics that credit filters statistics, carries out erroneous frame according to AFDX data packet format; Then input sends request, storage control with time time-card poll mode make arbitration;
B), the input that obtains control takes out an address blank from null pointer queue, unfiltered correct data frame is write to this address blank shared storage space pointed with 512bits bit wide, and this address blank and other relevant informations are write in the output queue of corresponding output port; Wherein other relevant informations comprise output port, multicast port number information, in the virtual link table information that these information are read in by memory access interface equally, obtain.For guaranteeing the integrality of data, write till the shared storage end time should write completely with single complete data packet.
C), at output, output queue scheduler is read memory address and other information of the frame being buffered from the output queue of each port non-NULL in the mode of clock poll, according to memory address, from shared storage, read frame data, and send to output port;
D), output port is converted to SGMII Ethernet data by 512bits bit wide data and sends out switch.
The present invention has realized normal AFDX agreement switching engine: meet ARINC664 agreement and support 24 mouthfuls of gigabit exchanges data, can complete credit filtration, erroneous frame filtration.
Credit Account filters:
One, establishing credit ACcount initialize is:
after the first frame data are received, Account deducts
Two, the value of ACcount is pressed in time
ratio increases, and maximum is no more than
wherein
for the maximum frame length of relevant link, J
i, switchfor relevant link jitter value, BAG
ifor relevant link frame period;
Three,, when each frame arrives switch, adopt two strategies below:
If AC
ibe greater than
frame is allowed through, and the value of ACi cuts
If AC
ibe less than
frame is dropped, AC
ivalue remain unchanged and upgrade MIB entry;
J
i, switchspan from 0 to 10ms, BAG
ifrom 1ms to 128ms;
After abbreviation, ACmax is BAG
i+ J
i, switch, ratio increases in time, deducts at every turn
aCmax is 138ms to the maximum.With 22bit, just can represent (40ns).With 23bit, just can represent (20ns).
The credit account form of employing based on frame, flow control computational process is as follows:
When system starts, global counter starts counting.The local counter of frame in VL list item is clear 0, and AC composes maximum permissible value ACmax.
When a frame arrives, the local Counter Value (64bits) that deducts each VL by global counter (64bits) is added the AC surplus of this VL, has so just obtained the current credit of frame.
If current credit is less than
this frame abandons.All fields of this VL item remain unchanged.
If current credit is greater than
be less than ACmax, frame can forward.The count value that the local Counter Value of this VL of write-back is current global counter.Write-back AC surplus is that current credit deducts
If current credit is greater than ACmax, composing current credit is ACmax.Frame can forward.The count value that the local Counter Value of this VL of write-back is current global counter.Write-back AC surplus is that current credit deducts
Claims (6)
1. a gigabit AFDX switch, comprise switching fabric, switching port, memory access interface, exchange termination interface, global counter, local counter based on shared storage, it is characterized in that described switching fabric comprises shared storage, described shared storage is dual-ported memory, and the bit wide of single port is 512bits;
Described switching port is input to shared storage for the SGMII Ethernet data of input port is converted to 512bit parallel data; 512bit parallel data in shared storage is converted to the output of SGMII Ethernet data;
Described memory access interface is for the configuration information of reading external memory storage;
Described exchange termination interface for the communicating by letter of processor, complete the information interaction of MIB and processor;
Global counter is used for calculating global clock, completes the calculating of credit;
In the processing time of local counter for calculating individual frames, coordinate global counter to complete the calculating of the information such as credit.
2. a kind of gigabit AFDX switch according to claim 1, is characterized in that described shared storage adopts fpga chip, and by 64 BRAM, being combined into a degree of depth is 2K, the dual-ported memory that bit wide is 1024bits.
3. a kind of gigabit AFDX switch according to claim 1, is characterized in that described switching fabric also comprises clock sharding unit, storage control, idle address pointer alignment, output queue scheduling, multicast counting unit;
Described clock sharding unit is for providing for sharing storage control to N input port and N the timing cycle that output port carries out the access of timeslice poll;
Described storage control for to input the request of sending with time time-card poll mode make arbitration, from the pointer alignment of idle address, take out an address blank, data are write to this address blank shared storage space pointed, and this address blank and other relevant informations are write in the output queue of corresponding output port;
Described shared storage control is used for time-card on time shared storage is carried out to poll access;
Described address blank pointer alignment is for the management of shared storage address blank;
Described output queue scheduler for time time-card poll mode from the output queue of each output port non-NULL, read memory address and other information of the frame being buffered, according to memory address, from shared storage space, read frame data and send to output port;
Counting when described multicast counting unit forwards for multichannel is controlled.
4. a kind of gigabit AFDX switch according to claim 1, its switching method comprises following steps:
A), when input has Frame to arrive, input port is converted to 512bits data format by SGMII data; In switching fabric, according to virtual link BAG pre-configured the virtual link table reading in from memory access interface and Jitter, carry out the filtration statistics that credit filters statistics, carries out erroneous frame according to AFDX data packet format; Then input sends request, storage control with time time-card poll mode make arbitration;
B), the input that obtains control takes out an address blank from null pointer queue, unfiltered correct data frame is write to this address blank shared storage space pointed with 512bits bit wide, and this address blank and other relevant informations are write in the output queue of corresponding output port; Wherein other relevant informations comprise output port, multicast port number information, in the virtual link table information that these information are read in by memory access interface equally, obtain;
C), at output, output queue scheduler is read memory address and other information of the frame being buffered from the output queue of each port non-NULL in the mode of clock poll, according to memory address, from shared storage, read frame data, and send to output port;
D), output port is converted to SGMII Ethernet data by 512bits bit wide data and sends out switch.
5. switching method according to claim 4, is characterized in that described credit filters statistics and specifically comprises following steps:
E), system is when start, global counter starts counting, the local counter of frame in virtual link list item is clear 0, AC composes maximum permissible value Acmax=BAG
i+ J
i, switch;
F), when a frame arrives, the local Counter Value that deducts each VL by global counter is added the AC surplus of this VL, obtains the current credit AC of frame
i;
G) if current credit AC
ibe less than the maximum frame length of relevant link
this frame abandons, and all fields of this VL item remain unchanged;
If current credit is greater than
be less than ACmax, forward present frame, the count value that the local Counter Value of this VL of write-back is current global counter, write-back AC surplus is current credit AC
ideduct
If current credit AC
ibe greater than ACmax, composing current credit is Acmax, forwards present frame, the count value that the local Counter Value of this VL of write-back is current global counter, and write-back AC surplus is that current credit deducts
6. switching method according to claim 4, is characterized in that the type of error of described erroneous frame comprises that crc error, frame length mistake, byte do not line up mistake, field of constants mistake, virtual link VL ID mistake, credit mistake.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486112A (en) * | 2014-12-09 | 2015-04-01 | 中国航空工业集团公司第六三一研究所 | Receiving processing method for data frame |
| CN105530157A (en) * | 2015-12-08 | 2016-04-27 | 中国航空工业集团公司西安航空计算技术研究所 | Method for sharing credit by multiple virtual links in AFDX (Avionics Full Duplex Switched Ethernet) network switch |
| CN105897621A (en) * | 2016-07-01 | 2016-08-24 | 中国航空无线电电子研究所 | Gigabit AFDX (Avionics Full Duplex Switched Ethernet) switcher based on CIOQ (Combined Input and Output Queuing) structure and switching method thereof |
| CN108199911A (en) * | 2017-12-07 | 2018-06-22 | 中国航空工业集团公司西安航空计算技术研究所 | AVDX shares the test method of same virtual link credit |
| CN108614667A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frames power on automatic loaded circuit and method |
| CN111585918A (en) * | 2020-05-09 | 2020-08-25 | 中国航空无线电电子研究所 | Store-and-forward device and method applied to store-and-forward mechanism switch |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098216A (en) * | 2010-12-21 | 2011-06-15 | 中国航空无线电电子研究所 | Avionics full duplex switched Ethernet (AFDX) protocol switching engine based on shared storage |
| CN103634238A (en) * | 2013-12-03 | 2014-03-12 | 中国航空无线电电子研究所 | Interchanger and interchanging method for supporting data monitoring of AFDX (avionics full duplex-switched Ethernet) protocol interchanging engine |
-
2014
- 2014-06-17 CN CN201410268433.5A patent/CN104009942A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098216A (en) * | 2010-12-21 | 2011-06-15 | 中国航空无线电电子研究所 | Avionics full duplex switched Ethernet (AFDX) protocol switching engine based on shared storage |
| CN103634238A (en) * | 2013-12-03 | 2014-03-12 | 中国航空无线电电子研究所 | Interchanger and interchanging method for supporting data monitoring of AFDX (avionics full duplex-switched Ethernet) protocol interchanging engine |
Non-Patent Citations (1)
| Title |
|---|
| 沈磊 等: "AFDX 交换机的ASIC 设计和实现", 《航空电子技术》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486112A (en) * | 2014-12-09 | 2015-04-01 | 中国航空工业集团公司第六三一研究所 | Receiving processing method for data frame |
| CN105530157A (en) * | 2015-12-08 | 2016-04-27 | 中国航空工业集团公司西安航空计算技术研究所 | Method for sharing credit by multiple virtual links in AFDX (Avionics Full Duplex Switched Ethernet) network switch |
| CN105530157B (en) * | 2015-12-08 | 2018-12-25 | 中国航空工业集团公司西安航空计算技术研究所 | The multiple virtual links of the AFDX network switch share the framework and method of credit |
| CN105897621A (en) * | 2016-07-01 | 2016-08-24 | 中国航空无线电电子研究所 | Gigabit AFDX (Avionics Full Duplex Switched Ethernet) switcher based on CIOQ (Combined Input and Output Queuing) structure and switching method thereof |
| CN105897621B (en) * | 2016-07-01 | 2019-01-15 | 中国航空无线电电子研究所 | Gigabit AFDX interchanger and its exchange method based on CIOQ structure |
| CN108614667A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frames power on automatic loaded circuit and method |
| CN108614667B (en) * | 2016-12-12 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frame power-on automatic loading circuit and method |
| CN108199911A (en) * | 2017-12-07 | 2018-06-22 | 中国航空工业集团公司西安航空计算技术研究所 | AVDX shares the test method of same virtual link credit |
| CN111585918A (en) * | 2020-05-09 | 2020-08-25 | 中国航空无线电电子研究所 | Store-and-forward device and method applied to store-and-forward mechanism switch |
| CN111585918B (en) * | 2020-05-09 | 2022-05-06 | 中国航空无线电电子研究所 | Store-and-forward device and method applied to store-and-forward mechanism switch |
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