CN109446132A - A kind of interface bus device and data communication protocol - Google Patents

Abstract

The present disclosure discloses a kind of interface bus device and data communication protocols, devise a kind of interface bus device, data fifo buffer is separately configured for data and order transmission channel, and it is provided with the control of corresponding access and status signal data line, realize the separated transmission of data and order, improve the communication efficiency of bus, proposing the Data Transport Protocol of the interface bus device based on the disclosure simultaneously includes synchronous transfer, asynchronous transmission and parallel transmission, interface signal is concise, it is realized by FIFO transmission mechanism, signal of communication line number amount can be effectively reduced, and flow control can be supported to transmit, solves the problems, such as short packet transmission, realize the scalability and compatibility of high-speed data and command communication between ASIC/SoC and FPGA.

Description

A kind of interface bus device and data communication protocol

Technical field

This disclosure relates to correlative technology field be communicated, in particular to a kind of interface bus device and data communication Agreement.

Background technique

Only there is provided background technical informations relevant to the disclosure for the statement of this part, it is not necessary to so constitute first skill Art.

ASIC is the english abbreviation of Application Specific Integrated Circuit, and SoC is System The abbreviation of on Chip, ASIC and SoC are address of the integrated circuit fields to different application type chip.ASIC is generally referred to specially With chip, SoC refers generally to System on Chip/SoC.FPGA (Field-Programmable Gate Array), i.e. field-programmable gate array Column, it is the product of programming device development.It is as one of the field specific integrated circuit (ASIC) semi-custom circuit And occur, not only solved the deficiency of custom circuit, but also overcome the limited disadvantage of original programming device gate circuit number.

In actual circuit application, the electrical combination mode of ASIC/SoC+FPGA is used, often to extend ASIC/SoC The function of chip.However the communication bus between ASIC/SoC and the FPGA in the industry cycle not agreement of standard, typically basis Depending on the interface that ASIC/SoC is extended out, SRAM interface, SDIO interface, fifo interface, high-speed differential interface etc., interface are generally comprised Many kinds of and performance is inconsistent.Wherein fifo interface is more common, and application block diagram is as shown in Figure 1, interface sequence figure such as Fig. 2 It is shown, when FULL is non-full, can be write data into SoC by PUSH and DQ (data)；When EMPTY signal non-empty, lead to POP is crossed to read data DQ (data) from SoC.

Traditional fifo interface is very simple, it can be achieved that property is strong, but there are problems in actual application:

1. it is generally divided into order, data and state phase in application protocol, if using traditional fifo interface, by There was only one group in physical interface and be limited, then can only be realized by serial process, be illustrated in figure 3 traditional fifo interface number According to the flow chart of transmission.

2. utility command, data length are limited, if needing the end SoC and the end FPGA, in advance using traditional fifo interface Artificially defined good command format or data length are unable to satisfy the transmission application of the similar short packet of usb protocol.Short packet transmission is opposite The data length of concept, current transmission is all short packet less than agreement conveying length.For example the data packet that both sides arrange to transmit is The multiple of 512 bytes or 512 bytes, then the transmission of inadequate 512 byte is exactly short packet.

Summary of the invention

The disclosure to solve the above-mentioned problems, proposes a kind of interface bus device and data communication protocol, devises one Kind interface bus device is separately configured data fifo buffer for data and order transmission channel, and is provided with corresponding access Control and status signal data line, realize the separated transmission of data and order, improve the communication efficiency of bus, simultaneously The Data Transport Protocol of the interface bus device based on the disclosure, including synchronous transfer, asynchronous transmission and parallel transmission are proposed, Interface signal is concise, is realized by FIFO transmission mechanism, can effectively reduce signal of communication line number amount, and can support flow control Transmission solves the problems, such as short packet transmission, realizes the scalability of high-speed data and command communication between ASIC/SoC and FPGA And compatibility.

To achieve the goals above, the disclosure adopts the following technical scheme that

A kind of or multiple embodiments provide a kind of interface bus device, for realizing the number between FPGA and integrated chip According to transmission, integrated chip is connected to by configuring bus, including configuration register, interface logic biock, is separately positioned on data With the FIFO buffer and data signal transmission wire in order transmission channel；The data signal line is used for transmission order, data And state；The configuration file that the configuration register is used to store and execute host computer transmission realizes configuration and the shape of data transmission The inquiry of state；The connecting interface that the interface logic biock is transmitted as data, data signal transmission wire pass through interface logic mould Block is separately connected configuration register and FIFO buffer.

Further, the data signal transmission wire includes FIFO selection signal line, FIFO full signal line, fifo empty signal Line and data end-of-packet command signal line；It is respectively used to the selected FIFO buffer signal of transmission present data transmission, current The state of FIFO buffer is full or spacing wave and transmission end of data order.

Further, the FIFO buffer in the data and order transmission channel includes write order channel FIFO, writes number According to channel FIFO, read command channel FIFO and read data channel FIFO, be respectively used to caching write order, write data, read command and Read data.

Further, the configuration register includes register and DFF trigger interconnected.

Further, each FIFO buffer includes dual-port SRAM interconnected, read counter, writes counter With cross clock domain synchronous circuit.

Based on a kind of Data synchronization interface agreement of above-mentioned interface arrangement, interface arrangement connects FPGA and integrated chip, Realize that FPGA writes data into integrated chip or reads the data in integrated chip, on the basis of synchronizing clock signals, interface In order, address and data line all with clock along aligning, including following operation:

1) write order operates: when CLK rising edge clock is sampled, working as CS#, WE#, CFIFO_SEL#, CFIFO_ When FULL is low simultaneously, expression current operation is order write operation；

2) read command operates: when CLK rising edge clock is sampled, working as CS#, RE#, CFIFO_SEL#, CFIFO_ When EMPTY is low simultaneously, expression current operation is order read operation；

3) data writing operation: when CLK rising edge clock is sampled, working as CS#, WE# be it is low, CFIFO_SEL# is height, When WFIFO_FULL is low, expression current operation is data write operation；

4) read data manipulation: when CLK rising edge clock is sampled, working as CS#, RE#, CFIFO_EMPTY be it is low, When CFIFO_SEL# is high, expression current operation is data read operation.

It further, further include PKGEND# signal for transmission end of data order, when to have sent data same for data sending terminal When send transmission end of data order, realize the definition of data or order length.

Data asynchronous interface agreement based on a kind of above-mentioned interface arrangement, interface arrangement connect FPGA and integrated chip, Realize that FPGA writes data into integrated chip or reads the data in integrated chip, on the basis of command signal line, in interface Order, address and data line by command signal line edging trigger, including following operation:

1) write order operates: when WE# rising edge is sampled, working as CS#, CFIFO_SEL#, CFIFO_FULL is simultaneously When low, expression current operation is order write operation.

2) read command operates: when RE# rising edge is sampled, working as CS#, CFIFO_SEL#, CFIFO_EMPTY is simultaneously When low, expression current operation is order read operation.

3) data writing operation: when WE# rising edge is sampled, when CS# be it is low, CFIFO_SEL# be height, CFIFO_ When FULL is low, expression current operation is data write operation.

4) read data manipulation: when RE# rising edge is sampled, working as CS#, CFIFO_EMPTY be it is low, CFIFO_SEL# is Gao Shi, expression current operation are data read operation.

It further, further include PKGEND# signal for transmission end of data order, when to have sent data same for data sending terminal When send transmission end of data order, realize the definition of data or order length.

Based on a kind of data concurrency transmission method of above-mentioned interface arrangement, using above-mentioned when data or order are transmitted Sync cap agreement or above-mentioned asynchronous interface agreement, main side send the order of read-write data to from end, include the following steps:

1) hair write order in main side is given from end；

2) read command operation is inserted into main side while writing data；

3) from end while data are write in reception, reading data are begun preparing after receiving read command, data and preparation are write in reception Data Concurrent is read to carry out；

4) the case where after harvesting data from termination, sending back to write state, then preparing data according to read command, which sends, reads data；

5) after main side receives reading data, read states are returned.

Compared with prior art, the disclosure has the beneficial effect that

(1) disclosure devises a kind of interface bus device, and data fifo is separately configured for data and order transmission channel Buffer, and it is provided with the control of corresponding access and status signal data line, the separated transmission of data and order is realized, The communication efficiency of bus is improved,

It (2) include synchronous transfer the present disclosure proposes the Data Transport Protocol of the interface bus device based on the disclosure, different Step transmission and parallel transmission, interface signal is concise, is realized by FIFO transmission mechanism, can effectively reduce signal of communication line number Amount, and flow control can be supported to transmit, it solves the problems, such as short packet transmission, realizes high-speed data and life between ASIC/SoC and FPGA Enable the scalability and compatibility of communication.

Detailed description of the invention

The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows Meaning property embodiment and its explanation do not constitute the restriction to the application for explaining the application.

Fig. 1 is existing fifo interface application block diagram；

Fig. 2 is existing fifo interface timing diagram；

Fig. 3 is existing fifo interface data transmission stream journey figure；

Fig. 4 is the interface arrangement structural schematic diagram of the disclosure；

Fig. 5 is the single fifo logic circuit diagram of the disclosure；

Fig. 6 is disclosure sync cap agreement timing diagram；

Fig. 7 is disclosure asynchronous interface agreement timing diagram；

Fig. 8 is the Data Concurrent transmission flow figure of the interface arrangement based on the disclosure.

Specific embodiment:

The disclosure is described further with embodiment with reference to the accompanying drawing.

It is noted that described further below be all exemplary, it is intended to provide further instruction to the application.Unless another It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field The identical meanings of understanding.

It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.It should be noted that not conflicting In the case where, the features in the embodiments and the embodiments of the present application can be combined with each other.Below in conjunction with attached drawing to embodiment It is described in detail.

In the technical solution disclosed in one or more embodiments, as shown in figure 4, a kind of interface bus device, is used In realizing the data transmission between FPGA and integrated chip, the integrated chip can be special chip or System on Chip/SoC, lead to It crosses configuration bus and is connected to integrated chip, the configuration bus can be ahb bus, APB bus or AXI bus, the disclosure Interface bus device includes configuration register, interface logic biock, the FIFO being separately positioned in data and order transmission channel Buffer and data signal transmission wire；The data signal line is used for transmission order, data and state；The configuration register is used The configuration of data transmission and the inquiry of state are realized in the configuration file for storing and execute host computer transmission；The interface logic mould Connecting interface of the block as data, order and state transfer, data signal transmission wire is separately connected by interface logic biock matches Set register and FIFO buffer.

FIFO buffer in disclosure data and order transmission channel includes write order channel C WFIFO, write data channel WFIFO, read command channel C RFIFO and reading data channel RFIFO are respectively used to caching write order, write data, read command and reading Data.Interface logic biock includes register and the CMOS logic gate circuit connecting with register, cmos logic gate include NOT gate, With door, NAND gate, nor gate or door, XOR gate and biconditional gate etc., interface logic biock is set by conventional circuit structure Set main realization Data Physical layer transmission；Order write operation is realized into CWFIFO by hardware logic, realizes that order is read Operate the read-out command from CRFIFO；Data write operation is realized into WFIFO, realizes that data read operation is read from RFIFO Data out.

As shown in figure 4, being the interface arrangement structural schematic diagram of the disclosure, data signal transmission wire is in addition to including traditional Data signal transmission wire described in fifo interface includes following signal wire:

CFIFO_SEL#:FIFO selection signal line, for selecting the selected FIFO buffer of present data transmission. CFIFO_FULL:FIFO expires signal wire, for judging whether the state of current FIFO buffer is full.CFIFO_EMPTY:FIFO Spacing wave line, for judging whether the state of current FIFO buffer is empty.PKGEND#: data end-of-packet command signal line is used In transmission the data transfer ends order.

The configuration register of the present embodiment includes register and DFF trigger interconnected, and register and DFF are triggered Device connects to form configuration circuit by existing method, and configuration register is connect by configuring bus with host computer, for storing With the configuration file for executing host computer transmission, configuration bus can pass through for ahb bus, APB bus or AXI bus, host computer Configuration register can carry out the configuration and status inquiry of entire interface arrangement；The configuration file is for Data Transport Protocol The file of definition, including synchronous transfer configuration file, asynchronous transmission configuration file and concurrent transmission configuration file.

The present embodiment is provided with transmission/reception FIFO and the transmission/reception of data group that 4 FIFO are respectively order group FIFO, the transmission for carrying out data and order are sent.4 data fifo depth and bit wide can be configured voluntarily, the electricity of 4 FIFO Road figure can be used general fifo logic circuit and realize, as shown in figure 5, FIFO Memory is common dual-port SRAM；Left side FIFO wptr is to write counter logic and export FIFO wfull to expire signal；Right side FIFO rptr is read counter logic and defeated Rempty spacing wave out；Sync_r2w and sync_w2r is the cross clock domain synchronous circuit for writing counter and read counter respectively. Static random access memory (Static Random-Access Memory, SRAM) is one kind of random access memory.

The application method of above-mentioned interface arrangement is to connect FPGA and integrated chip by above-mentioned interface arrangement, counted It is initialized according to connection host computer before transmission, host computer fills the interface bus that corresponding configuration file is transmitted to the disclosure It sets, the transmission of data is carried out according to configuration, the disclosure is respectively provided with FIFO buffer for the channel of data and order, and corresponding Provided with corresponding signal transmssion line, the data in each channel and order transmission will not influence each other, and parallel transmission may be implemented, mention The efficiency of high data transmission.And data end-of-packet command signal line is provided in the device of the disclosure, when transmission end of data A data end-of-packet order is sent, realizes the transmission of short packet data.

Embodiment 2

The present embodiment provides a kind of based on a kind of data synchronous transfer agreement of interface arrangement described in embodiment 1.

Sync cap agreement, which refers to, clock in interface signal, the order, address and data line in interface are all and clock edge It aligns.

Timing diagram is as shown in fig. 6, the signal instruction first in timing diagram is as follows:

CS# is chip selection signal: the integrated chip for selecting to carry out data transmission with FPGA, and FPGA sends order or number According to when, while sending chip selection signal, low level is effective.

WE# is write command signal: being write operation for defining current operation, FPGA sends write order or writes data When, while write command signal is sent, low level is effective.

CFIFO_SEL# is FIFO buffer selection signal: CFIFO_SEL# is high level for selecting in interface arrangement Data FIFO buffers, CFIFO_SEL# are that low level is used to select the order FIFO buffer in interface arrangement, and FPGA is sent Order or when, while sending FIFO buffer selection signal:

CFIFO_FULL is FIFO full signal: the FIFO buffer in elected interface devices is discontented, and CFIFO_FULL is Low level order or data can be written.

RE# is read command signal: it is read operation for defining current operation, when FPGA sends read command or reads data, Read command signal is sent simultaneously, low level is effective.

CFIFO_EMPTY is fifo empty signal: the FIFO buffer in elected interface devices is not empty, CFIFO_EMPTY For low level, order or data can be read.

It is described to connect FPGA and integrated chip for interface arrangement, realize that FPGA writes data into integrated chip or reading Data in integrated chip, including following operation:

1) write order operates: when CLK rising edge clock is sampled, working as CS#, WE#, CFIFO_SEL#, CFIFO_ When FULL is low simultaneously, expression current operation is order write operation；When FPGA send write order, while send chip selection signal, Write command signal, FIFO buffer selection signal, if the write order FIFO buffer of selection is discontented to be written CWFIFO for order； Interface arrangement connection configuration bus transmits commands to integrated chip by configuring bus.This operation FPGA sends FIFO buffer Selection signal CFIFO_SEL# is low level and write command signal WE#, can determine that the FIFO buffer selected is write order FIFO buffer CWFIFO.Other operations are identical to the method for selecting of FIFO buffer.

2) read command operates: when CLK rising edge clock is sampled, working as CS#, RE#, CFIFO_SEL#, CFIFO_ When EMPTY is low simultaneously, expression current operation is order read operation；When FPGA send read command, while send chip selection signal, Read command signal, FIFO buffer selection signal, if selection read command FIFO buffer CRFIFO it is not empty will order from It is read in CRFIFO.

3) data writing operation: when CLK rising edge clock is sampled, working as CS#, WE# be it is low, CFIFO_SEL# is height, When WFIFO_FULL is low, expression current operation is data write operation；When FPGA transmission read command, while sending piece choosing letter Number, write command signal, FIFO buffer selection signal, if selection writes that data FIFO buffers are discontented to be write data into WFIFO；Interface arrangement connection configuration bus will write data by configuring bus and be transmitted to integrated chip.

4) read data manipulation: when CLK rising edge clock is sampled, working as CS#, RE#, CFIFO_EMPTY be it is low, When CFIFO_SEL# is high, expression current operation is data read operation；Data are read when FPGA is sent, while sending piece choosing letter Number, read command signal, FIFO buffer selection signal, if selection reading data FIFO buffers RFIFO it is not empty by data from It is read in RFIFO.

It further include PKGEND# signal to transmit end of data order, when data sending terminal has sent data while sending biography Transmission of data terminates order, realizes the definition of data or order length.

When PKGEND# is that low signal is effective, judge that the current end of transmission is according to current CFIFO_SEL# signal The order end of transmission or the data transfer ends, such both ends SoC and FPGA can freely define the order and data of current transmission Length realizes short packet transmission.

Embodiment 3

The present embodiment provides a kind of based on a kind of data asynchronous interface agreement of interface arrangement described in embodiment 1.This reality The signal definition for applying example is identical as in embodiment 2

Asynchronous interface agreement does not have clock for sync cap in interface signal, address and data in interface Line is all by order wire edging trigger.

A kind of data asynchronous interface agreement of interface arrangement, at this time without clock signal on interface, all signals are by inside Internal clk driving, timing diagram realize that FPGA writes data as shown in fig. 7, interface arrangement connection FPGA and integrated chip Enter integrated chip or reads the data in integrated chip, order, address and data on the basis of command signal line, in interface Line is by command signal line edging trigger, including following operation:

1) write order operates: when WE# rising edge is sampled, working as CS#, CFIFO_SEL#, CFIFO_FULL is simultaneously When low, expression current operation is order write operation.When FPGA send write order, while send chip selection signal, write command signal, FIFO buffer selection signal, if the write order FIFO buffer of selection is discontented to be written CWFIFO for order；Interface arrangement connects It connects configuration bus and transmits commands to integrated chip by configuring bus.

2) read command operates: when RE# rising edge is sampled, working as CS#, CFIFO_SEL#, CFIFO_EMPTY is simultaneously When low, expression current operation is order read operation.When FPGA send read command, while send chip selection signal, read command signal, FIFO buffer selection signal reads order if the read command FIFO buffer of selection is not empty from CRFIFO.

3) data writing operation: when WE# rising edge is sampled, when CS# be it is low, CFIFO_SEL# be height, WFIFO_ When FULL is low, expression current operation is data write operation.When FPGA transmission read command, while sending chip selection signal, writing life Signal, FIFO buffer selection signal are enabled, if selection writes that data FIFO buffers are discontented to write data into WFIFO；Interface Device connection configuration bus will write data by configuring bus and be transmitted to integrated chip.

4) read data manipulation: when RE# rising edge is sampled, working as CS#, CFIFO_EMPTY be it is low, CFIFO_SEL# is Gao Shi, expression current operation are data read operation.When FPGA send read data, while send chip selection signal, read command signal, FIFO buffer selection signal reads data if the reading data FIFO buffers of selection are not empty from RFIFO.

The integrated chip end such as end SoC time sequence parameter:

Twl indicates write signal low level number effective period, acts on to be spliced into the period of WE# signal with Twh, composition is write letter Number period, Twl >=3 can be set.

Twh indicates write signal high level hold period number, can set Twh >=3.

Trl indicates read signal low level number effective period, can set Trl >=3.

Trh indicates write signal high level hold period number, can set Trh >=3.

Data effective time of the data before WE# rising edge is write in Twdsetup expression, can set Twdsetup≤1.

Tend indicates PKGEND# signal low level number effective period, can set Tend >=3.

The end FPGA time sequence parameter:

Trdhold indicates data hold time of the reading data after RE# rising edge, can set Trdhold=0/1, Trdsetup indicates data effective time of the reading data before RE# rising edge, can set Trdsetup≤1

The realization of the short packet transmission of the present embodiment 3 is identical as the method implemented in 2.

Embodiment 4

The present embodiment provides a kind of based on a kind of data concurrency transmission method of interface arrangement described in embodiment 1

Concurrent transmission refers to that data and order between FPGA and integrated chip or internal synchronization and can advance Row transmission.Realization rate is mainly by being separately configured hardware FIFO buffer, hardware FIFO buffer for data and command channel Between data transmission be independent of each other.Can define send read write command end be main side, the other end be from end, can when data are transmitted With using the asynchronous interface agreement of 1 sync cap agreement of embodiment or embodiment 2, main side send the orders of read-write data to from End includes the following steps:

1) hair write order in main side is given from end；

2) read command operation is inserted into main side while writing data；

3) from end while data are write in reception, reading data are begun preparing after receiving read command, data and preparation are write in reception Data Concurrent is read to carry out；

4) the case where after harvesting data from termination, sending back to write state, then preparing data according to read command, which sends, reads data；

5) after main side receives reading data, read states are returned.

It is illustrated by taking the data transmission between the end FPGA and SoC as an example, it is concurrent between FPGA and SoC end shown in Fig. 8 The process of transmission is as follows:

1) hair write order in the end FPGA gives the end SoC.

2) read command operation is inserted at the end FPGA while writing data.

3) end SoC begins preparing reading data after receiving read command, the two concurrently carries out while data are write in reception.

4) after SoC termination harvests data, write state is sent back to, is then sent and is read according to the case where read command preparation data According to.

5) after the end FPGA receives reading data, read states are returned.

The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.

Although above-mentioned be described in conjunction with specific embodiment of the attached drawing to the disclosure, model not is protected to the disclosure The limitation enclosed, those skilled in the art should understand that, on the basis of the technical solution of the disclosure, those skilled in the art are not Need to make the creative labor the various modifications or changes that can be made still within the protection scope of the disclosure.

Claims (10)

1. a kind of interface bus device is connected with the data transmission then realized between FPGA and integrated chip by configuring bus It is connected to integrated chip, it is characterized in that: including configuration register, interface logic biock, being separately positioned on data and order transmission logical FIFO buffer and data signal transmission wire on road；The data signal line is used for transmission order, data and state；It is described to match It sets register and realizes the configuration of data transmission and the inquiry of state for storing and executing the configuration file of host computer transmission；It is described Interface logic biock as connecting interface, data signal transmission wire by interface logic biock be separately connected configuration register and FIFO buffer.

2. a kind of interface bus device as described in claim 1, it is characterized in that: the data signal transmission wire includes FIFO choosing Signal wire, FIFO full signal line, fifo empty signal line and data end-of-packet command signal line are selected, transmission current data is respectively used to Transmit selected FIFO buffer signal, the state of current FIFO buffer is full or spacing wave and transmission end of data Order.

3. a kind of interface bus device as described in claim 1, it is characterized in that: in the data and order transmission channel FIFO buffer includes write order channel FIFO, write data channel FIFO, read command channel FIFO and reads data channel FIFO, point Write order Yong Yu not be cached, data, read command are write and reads data.

4. a kind of interface bus device as described in claim 1, it is characterized in that: the configuration register includes interconnected Register and DFF trigger.

5. a kind of interface bus device as described in claim 1, it is characterized in that: each FIFO buffer includes mutually interconnecting The dual-port SRAM that connects, read counter, counter and cross clock domain synchronous circuit are write.

6. based on a kind of described in any item Data synchronization interface agreements of interface arrangement of claim 1-5, interface arrangement connection FPGA and integrated chip realize that FPGA writes data into integrated chip or reads the data in integrated chip, it is characterized in that: with On the basis of synchronizing clock signals, order, address and data line in interface all align with clock edge, including following operation:

1) write order operates: when CLK rising edge clock is sampled, working as CS#, WE#, CFIFO_SEL#, CFIFO_FULL is same When for it is low when, expressions current operation be order write operation；

2) read command operates: when CLK rising edge clock is sampled, working as CS#, RE#, CFIFO_SEL#, CFIFO_EMPTY is same When for it is low when, expressions current operation be order read operation；

3) data writing operation: when CLK rising edge clock is sampled, working as CS#, WE# be it is low, CFIFO_SEL# is height, When WFIFO_FULL is low, expression current operation is data write operation；

4) it reads data manipulation: when CLK rising edge clock is sampled, working as CS#, RE#, CFIFO_EMPTY are low, CFIFO_ When SEL# is high, expression current operation is data read operation.

7. Data synchronization interface agreement as claimed in claim 6, it is characterized in that: further including PKGEND# signal for transmission data Terminate order, when data sending terminal has sent data while sending transmission end of data order, realization data or order length Definition.

8. based on a kind of described in any item data asynchronous interface agreements of interface arrangement of claim 1-5, interface arrangement connection FPGA and integrated chip realize that FPGA writes data into integrated chip or reads the data in integrated chip, it is characterized in that: with On the basis of command signal line, the order, address and data line in interface are by command signal line edging trigger, including following operation:

1) write order operates: when WE# rising edge is sampled, work as CS#, when CFIFO_SEL#, CFIFO_FULL are low simultaneously, Expression current operation is order write operation.

2) read command operates: when RE# rising edge is sampled, working as CS#, CFIFO_SEL#, CFIFO_EMPTY are simultaneously low When, expression current operation is order read operation.

3) data writing operation: when WE# rising edge is sampled, when CS# be it is low, CFIFO_SEL# is height, and CFIFO_FULL is When low, expression current operation is data write operation.

4) read data manipulation: when RE# rising edge is sampled, working as CS#, CFIFO_EMPTY be it is low, CFIFO_SEL# is height When, expression current operation is data read operation.

9. Data synchronization interface agreement as claimed in claim 8, it is characterized in that: further including PKGEND# signal for transmission data Terminate order, when data sending terminal has sent data while sending transmission end of data order, realization data or order length Definition.

10. based on a kind of described in any item data concurrency transmission methods of interface arrangement of claim 1-5, it is characterized in that: number According to or when order transmission any one of using the described in any item sync cap agreements of claim 6-7 or claim 8-9 The asynchronous interface agreement, the order that main side sends read-write data extremely include the following steps: from end

1) hair write order in main side is given from end；

2) read command operation is inserted into main side while writing data；

3) from end while data are write in reception, reading data are begun preparing after receiving read command, reception writes data and prepares reading According to concurrently carrying out；

4) the case where after harvesting data from termination, sending back to write state, then preparing data according to read command, which sends, reads data；

5) after main side receives reading data, read states are returned.