CN105680871B - For data serial transmission and go here and there, serioparallel exchange device - Google Patents
For data serial transmission and go here and there, serioparallel exchange device Download PDFInfo
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- CN105680871B CN105680871B CN201610210167.XA CN201610210167A CN105680871B CN 105680871 B CN105680871 B CN 105680871B CN 201610210167 A CN201610210167 A CN 201610210167A CN 105680871 B CN105680871 B CN 105680871B
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- H03—ELECTRONIC CIRCUITRY
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Abstract
The invention discloses it is a kind of for data serial transmission and go here and there, serioparallel exchange device, including：It receives parallel data and converts parallel data into the parallel serial conversion unit of serial data output, and receive serial data and convert serial data to the serioparallel exchange unit of parallel data output.The present invention constitutes parallel serial conversion unit by the first holding register, the first shift register, the first push-up storage, to realize that parallel data is converted into serial data；Serioparallel exchange unit is constituted by the second push-up storage, the second shift register, the second holding register, to realize that serial data is converted into parallel data.The device is provided with data buffer area, data conversion control signal can effectively be simplified, and the input clock of the device and output clock may be at different clock-domains, and then can overcome since there are all data conversion mistakes caused by meeting when clock skew in input clock and output clock.
Description
Technical field
The present invention relates to data transformation technology field, more particularly to it is a kind of for data serial transmission and go here and there, go here and there and turn
Changing device.
Background technology
With the development of modern science and technology, data transmission technology has also obtained significant progress, during data transmission,
As clock frequency is higher and higher, when parallel transmission, increasingly severe, parallel transmission mode is interfered with each other between parallel wires
Bottleneck is developed to.And serial transmission uses differential signal (differential signal) transmission technology, effectively overcomes
Crosstalk between the interference formed to signal transmission line by antenna effect and transmission line so that serial transmission can obtain
Very high data transmission rate is obtained, and by extensive use.
Existing field programmable gate array (Field Programmable Gate Array, referred to as " FPGA ") technology
In, in order to realize the serial transmission of data, the parallel data in circuit is first often converted to serial data and is transmitted, then
Serial data is re-converted into parallel data in the end of transmission.Wherein, in order to realize and go here and there, serioparallel exchange, need first will
Data are first put into holding register, are then cached in putting shift register by controlling signal, finally by counting
Device generation carrys out output signal and exports data.
But rely on shift register data cached, it has the following problems：
It is complicated to control signal.In FPGA design, the switching that control signal not only controls clock frequency will also be responsible for data
The displacement of shift register, the buffering of data, output tally control etc., can increase in this way control signal complexity.FPGA
Middle control signal is made of combinational circuit, and signal is controlled in high frequency clock system and will appear burr and maloperation.
Clock adjustability is small.Input clock in existing FPGA design in serioparallel exchange and parallel-serial conversion and output clock
Than being changeless, when encountering data delay, it controls the design meeting more complexity of signal, in input clock and output
There are the mistakes that can all lead to data conversion when clock skew in clock.
Invention content
In order to solve the problems, such as exist in the prior art by shift register is data cached, the embodiment of the present invention provides
It is a kind of for data serial transmission and go here and there, serioparallel exchange device.The technical solution is as follows：
An embodiment of the present invention provides it is a kind of for data serial transmission and go here and there, serioparallel exchange device, including：It receives simultaneously
Row data simultaneously convert parallel data into the parallel serial conversion unit of serial data output, and receive serial data and by serial data
It is converted into the serioparallel exchange unit of parallel data output,
The parallel serial conversion unit includes：
First holding register is used for the parallel data of buffering external circuit transmission；
First shift register, for the parallel data cached in first holding register to be converted into serial number
According to；
First push-up storage, the serial data generated for caching first shift register, and using with
The different reading clock of clock is write to control data cached output；
The serioparallel exchange unit includes：
Second push-up storage is used for the serial data of buffering external circuit transmission, and using different from clock is write
Reading clock control data cached output；
Second shift register, for the serial data cached in second push-up storage to be converted into parallel
Data；
Second holding register, for caching the parallel data generated in second shift register.
In the above-mentioned device of the present invention, in the parallel serial conversion unit, the DataInValid pins of external circuit with
The Valid pins of first holding register are electrically connected, and are protected to control the write-in of the parallel data in external circuit described first
It holds in register；The WCtr pin electricity of the Valid pins of first shift register and first push-up storage
Connection, when first shift register converts parallel data into serial data, Valid pins will produce write-in control
Serial data is written to control first push-up storage in signal；It is written when in first push-up storage
When serial data, REmpty pins and Usageing pins generate not empty signal and Usageing signals respectively, described
Usageing signals indicate that the Bit numbers of storage serial data in first push-up storage, external circuit pass through non-empty
Signal and Usageing signals control the output of the serial data cached in first push-up storage.
In the above-mentioned device of the present invention, first push-up storage uses synchronous mode or asynchronous mode work
Make, the DataInClk for the clock signal that the clk pins of first holding register are connected to parallel data with external circuit draws
Foot is electrically connected, the Wclk pins of the clk pins of first shift register and first push-up storage with outside
In portion's circuit be connected to write clock signal DataWClk pins electrical connection, the Rclk pins of first push-up storage with
The DATARClk pins electrical connection of read clock signal is connected in external circuit.
In the above-mentioned device of the present invention, when first push-up storage uses synchronous mode, external circuit
DataInClk pins connection parallel data clock signal frequency fDataInClk, it is parallel data bit wide N, described first advanced
First go out the write clock signal frequency f that the Wclk pins of memory receiveWclkAnd the Rclk of first push-up storage
The read clock signal frequency f that pin receivesRclkBetween there are following relationships：
The Wfull pins of first push-up storage respectively with the Full pins of first holding register and
The Full pins of first shift register connect, when the Wfull pins of first push-up storage generate full scale
When knowledge, the input of first holding register and first shift register pause serial data can be controlled.
In the above-mentioned device of the present invention, when first push-up storage uses asynchronous mode, external circuit
DataInClk pins connection parallel data clock signal frequency fDataInClk, it is parallel data bit wide N, described first advanced
First go out the write clock signal frequency f that the Wclk pins of memory receiveWclkBetween there are following relationships：
The Wfull pins of first push-up storage respectively with the Full pins of first holding register and
The Full pins of first shift register connect, when the Wfull pins of first push-up storage generate full scale
When knowledge, the input of first holding register and first shift register pause serial data can be controlled, and identifies institute
It states in the first shift register and turns string and mistake occurs.
In the above-mentioned device of the present invention, in the serioparallel exchange unit, the DATAInValid pins of external circuit with
The WCtr pins of second push-up storage are electrically connected, to control the write-in of the serial data in external circuit described second
In push-up storage；The Data of the RData pins of second push-up storage and second shift register
Pin is electrically connected, the RCtr pin electricity of the Ready pins of second shift register and second push-up storage
Connection is written with controlling the serial data in second push-up storage in second shift register；Described
The REmpty pins and Usaging pins of two push-up storages Empty pins with second shift register respectively
It is electrically connected with Use pins, serial data is converted to parallel data to control second shift register；Described second keeps
The Active pins and Ready pins of register respectively with the DataOutActive pins and DataOutReady of external circuit
Pin is electrically connected, and the parallel data cached in second holding register is read for controlling external circuit.
In the above-mentioned device of the present invention, second push-up storage uses synchronous mode or asynchronous mode work
Make, the Wclk pins of second push-up storage are connected to the DATAWClk pin electricity of write clock signal with external circuit
Connection, the Rclk pins of the clk pins of second shift register and second push-up storage are and external electrical
The DataRClk pins electrical connection of read clock signal, the clk pins and external circuit of second holding register are connected in road
The DataOutClk pins electrical connection of the clock signal of middle connection parallel data.
In the above-mentioned device of the present invention, when second push-up storage uses synchronous mode, external circuit
DataOutClk pins connection parallel data clock signal frequency fDataOutClk, parallel data bit wide N, it is described second first
The write clock signal frequency f received into the Wclk pins for first going out memoryWclkAnd second push-up storage
The read clock signal frequency f that Rclk pins receiveRclkBetween there are following relationships：
In the above-mentioned device of the present invention, when second push-up storage uses asynchronous mode, external circuit
DataOutClk pins connection parallel data clock signal frequency fDataOutClk, parallel data bit wide N and described
The read clock signal frequency f that the Rclk pins of two push-up storages receiveWclkBetween there are following relationships：
The advantageous effect that technical solution provided in an embodiment of the present invention is brought is：
Parallel serial conversion unit is constituted by the first holding register, the first shift register, the first push-up storage,
To realize that parallel data is converted into serial data, when the first shift register carries out data conversion, using the first first in first out
Memory constitutes data buffer zone, can effectively simplify the composition of the first shift register control signal, moreover, the first advanced elder generation
Go out memory and the reading clock different from clock is write may be used to control data cached output so that parallel serial conversion unit it is defeated
Enter clock and output clock may be at different clock-domains, and then can overcome due to input clock and in the presence of exporting in clock
It all can caused data conversion mistake when clock deviates；Similarly, pass through the second push-up storage, the second shift register,
Two holding registers constitute serioparallel exchange unit, to realize that serial data is converted into parallel data, the second shift register into
When row data convert, data buffer zone is constituted using the second push-up storage, can effectively simplify the second shift register
The composition of signal is controlled, moreover, the reading clock different from clock is write may be used to control caching in the second push-up storage
The output of data so that the input clock of parallel serial conversion unit and output clock may be at different clock-domains, and then can with gram
Clothes are since there are all data conversion mistakes caused by meeting when clock skew in input clock and output clock.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is provided in an embodiment of the present invention a kind of for data serial transmission and going here and there, the structure of serioparallel exchange device
Schematic diagram；
Fig. 2 is a kind of circuit diagram of parallel serial conversion unit provided in an embodiment of the present invention；
Fig. 3 is a kind of circuit diagram of serioparallel exchange unit provided in an embodiment of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment
An embodiment of the present invention provides it is a kind of for data serial transmission and go here and there, serioparallel exchange device, should referring to Fig. 1
Device includes：
It receives parallel data and converts parallel data into the parallel serial conversion unit 1 of serial data output, and receive serial
Data and the serioparallel exchange unit 2 for converting serial data to parallel data output.
Referring to Fig. 2, which includes：
First holding register 11 is used for the parallel data of buffering external circuit transmission.
First shift register 12, for the parallel data cached in the first holding register 11 to be converted into serial number
According to.
First push-up storage 13, for cache the first shift register 12 generation serial data, and use with
The different reading clock of clock is write to control data cached output.
Referring to Fig. 3, which includes：
Second push-up storage 21 is used for the serial data of buffering external circuit transmission, and uses and write clock not
With reading clock control data cached output.
Second shift register 22, for the serial data cached in the second push-up storage 21 to be converted into parallel
Data.
Second holding register 23, for caching the parallel data generated in the second shift register 22.
In the present embodiment, it is respectively provided with when serial data is converted to parallel data and parallel data is converted into serial data
Data buffer zone (uses the first push-up storage 13 and the second push-up storage 21), this buffering area can be with
Simplify control signal eliminates the delay occurred when data transmission.First push-up storage 13 and the second first in first out storage
21 one side of device can work as data buffer zone, on the other hand, and be controlled using the reading clock different from clock is write
Make data cached output so that should and go here and there, the clock of serioparallel exchange device is adjustable.
In the present embodiment, the data conversion process of above-mentioned apparatus is as follows：
First the parallel data in external circuit is buffered in the first holding register 11；
Then the parallel data cached in the first holding register 11 is converted to serially by the first shift register 12
Data；
Finally the serial data converted is buffered in the first push-up storage 13, and is deposited by the first first in first out
Reservoir 13, which is transmitted in external circuit, to be used for transmission in the circuit of serial data.
Parallel data is converted to after serial data is transmitted by the above process, which can also receive serial data
And the parallel data of script is converted it into, detailed process is as follows：
First the serial data in external circuit is buffered in the second push-up storage 21；
Then serial data is converted to parallel data by the second shift register 22；
Finally the parallel data converted is buffered in the second holding register 23, and is passed by the second holding register 23
It transports in external circuit.
Specifically, referring to Fig. 2, in parallel serial conversion unit 1, the DataInValid pins of external circuit and first are kept
The Valid pins of register 11 are electrically connected, and (its in the first holding register 11 is written to control the parallel data in external circuit
In imply the data line of external circuit and be electrically connected with the data pin Data pins of the first holding register 11)；First
The Valid pins of shift register 12 are electrically connected with the WCtr pins of the first push-up storage 13, when the first shift LD
When device 12 converts parallel data into serial data, Valid pins will produce write control signal, to control the first advanced elder generation
Go out memory 13 serial data be written (wherein to imply the data pin Data pins of the first shift register 12 and first advanced
First go out the WData pins electrical connection of memory 13)；When serial data is written in the first push-up storage 13,
REmpty pins and Usageing pins generate not empty signal and Usageing signals respectively, which indicates first
The Bit numbers of serial data are stored in push-up storage 13, external circuit is controlled by not empty signal and Usageing signals
Make the output of the serial data cached in the first push-up storage 13.
In the present embodiment, external circuit parallel data pin Data [N-1,0] (wherein the width of parallel data be N,
N is the positive integer more than 1) it is electrically connected with the Data pins of the first holding register 11, it is used for transmission parallel data, external circuit
Data In Valid pins be electrically connected with the Valid pins of the first holding register 11, for generating Data In Valid
Signal is cached to control in parallel data the first holding register 11 of write-in.The Valid pins of first shift register 12
It is electrically connected with the WCtr pins of the first push-up storage 13, the Data pins of the first shift register 12 and the first advanced elder generation
Go out the WData pins electrical connection of memory 13, the first shift register 12 is when progress parallel data is converted into serial data, meeting
Write control signal is generated, that is, controls the control signal of the first push-up storage 13 write-in serial data.In practical application
In, it is only necessary to it is write control signal to demarcate parallel data effectively, so that it may to greatly simplify the control of the first shift register 12
Signal.The REmpty pins of first push-up storage 13 are electrically connected with the DATA Out Valid pins of external circuit, the
The Usageing pins of one push-up storage 13 are electrically connected with the DataUsageing pins of external circuit, the first advanced elder generation
The TCtr pins for going out memory 13 are electrically connected with the DATA Out Ready pins of external circuit, in this way, external circuit passes through
The not empty signal and Usageing signals that one push-up storage 13 generates delay to control in the first push-up storage 13
The output for the serial data deposited.In addition, the WRst pins (writing reset pin) of the first push-up storage 13, the first displacement
The Rst pins (i.e. reset pin) of register 12, the Rst pins (i.e. reset pin) of the first holding register 11 are and external electrical
The DataWRst pins on road are electrically connected；The RRst pins (reading reset pin) and external circuit of first push-up storage 13
DataR Rst pins electrical connection.In addition, the depth of the first push-up storage 13 can be set according to actual demand, this
In be not limited.
Further, synchronous mode or asynchronous mode work may be used in the first push-up storage 13, and first protects
Hold register 11 clk pins (i.e. clock pins) be connected to external circuit parallel data clock signal Data In
Clk pins are electrically connected, the clk pins (i.e. clock pins) of the first shift register 12 and the first push-up storage 13
Wclk pins (writing clock pins) are connected to the DataWClk pins of write clock signal with external circuit, and (i.e. data write clock
Pin) electrical connection, when the Rclk pins (reading clock pins) of the first push-up storage 13 are connected to reading with external circuit
The DATARClk pins of clock signal are electrically connected.
In the present embodiment, the write clock signal of the first push-up storage 13 connection is different from read clock signal, when
Exist when first push-up storage 13 is using synchronous mode, between write clock signal and read clock signal and be associated with, when first
When push-up storage 13 is using asynchronous mode, there is no be associated between write clock signal and read clock signal.
Further, when the first push-up storage 13 is using synchronous mode, the DataInClk pins of external circuit
The clock signal frequency f of the parallel data of connectionDataInClk, parallel data bit wide N, the first push-up storage 13 Wclk
The write clock signal frequency f that pin receivesWclkAnd first push-up storage 13 Rclk pins receive reading clock letter
Number frequency fRclkBetween there are following relationships：
The Wfull pins (writing full pin) of first push-up storage 13 respectively with the first holding register 11
Full pins (expiring signal pins) are connected with the Full pins of the first shift register 12, when the first push-up storage 13
Wfull pins generate full scale know when, can control the first holding register 11 and the first shift register 12 pause serial data
Input.
Further, when the first push-up storage 13 is using asynchronous mode, the DataInClk pins of external circuit
The clock signal frequency f of the parallel data of connectionDataInClk, parallel data bit wide N, the first push-up storage 13 Wclk
The write clock signal frequency f that pin receivesWclkBetween there are following relationships：
The Wfull pins of first push-up storage 13 Full pins and first with the first holding register 11 respectively
The Full pins of shift register 12 connect, and when the Wfull pins of the first push-up storage 13, which generate full scale, to be known, can control
The input of the first holding register 11 and the first shift register 12 pause serial data is made, and identifies the first shift register 12
In and turn string occur mistake.
Specifically, referring to Fig. 3, in serioparallel exchange unit 2, DATAInValid pins of external circuit and second advanced
The second push-up storage is written to control the serial data in external circuit in the WCtr pins electrical connection for first going out memory 21
In 21, wherein the DATAIn pins of external circuit are electrically connected with the Wdata pins of the second push-up storage 21, and second first
It is electrically connected into the WFull pins of memory 21 are first gone out with the DATAInReady pins of external circuit, such second first in first out is deposited
Serial data is written to control external circuit by WCtr pins and WFull pins in reservoir 21.Second push-up storage 21
RData pins be electrically connected with the Data pins of the second shift register 22, the Ready pins of the second shift register 22 and
The RCtr pins of two push-up storages 21 are electrically connected, and are written with the serial data controlled in the second push-up storage 21
In second shift register 22.The REmpty pins and Usaging pins of second push-up storage 21 are moved with second respectively
The Empty pins and Use pins of bit register 22 are electrically connected, and are converted simultaneously serial data to controlling the second shift register 22
Row data, wherein what the Uasging signals that Usaging pins generate indicated is significant figure in the second push-up storage 21
According to Bit numbers.The Active pins and Ready pins of second holding register 23 respectively with external circuit
DataOutActive pins and the electrical connection of DataOutReady pins read the second holding register for controlling external circuit
The parallel data cached in 23.In addition, the RRst pins (reading reset pin) of the second push-up storage 21, the second displacement
The Rst pins (i.e. reset pin) of register 22, the Rst pins (i.e. reset pin) of the second holding register 23 are and external electrical
The DataRRst pins on road are electrically connected；The WRst pins (writing reset pin) and external circuit of second push-up storage 21
DataWRst pins electrical connection.
In the present embodiment, the depth of the second push-up storage 21 can be set according to actual demand, not done here
Limitation.
Further, synchronous mode or asynchronous mode work may be used in the second push-up storage 21, and second first
It is electrically connected into the Wclk pins for first going out memory 21 with the DATAWClk pins for being connected to write clock signal in external circuit, second moves
The Rclk pins of the clk pins of bit register 22 and the second push-up storage 21, which are connected to external circuit, reads clock letter
Number the electrical connection of DataRClk pins, the clk pins of the second holding register 23 be connected to external circuit parallel data when
The DataOutClk pins of clock signal are electrically connected.
In the present embodiment, the write clock signal of the second push-up storage 21 connection is different from read clock signal, when
Exist when second push-up storage 21 is using synchronous mode, between write clock signal and read clock signal and be associated with, when second
When push-up storage 21 is using asynchronous mode, there is no be associated between write clock signal and read clock signal.
Further, when the second push-up storage 21 is using synchronous mode, the DataOutClk of external circuit draws
The clock signal frequency f of the parallel data of foot connectionDataOutClk, parallel data bit wide N, second push-up storage 21
The write clock signal frequency f that Wclk pins receiveWclkAnd second push-up storage 21 Rclk pins receive reading when
Clock signal frequency fRclkBetween there are following relationships：
Further, when the second push-up storage 21 is using asynchronous mode, the DataOutClk of external circuit draws
The clock signal frequency f of the parallel data of foot connectionDataOutClk, parallel data bit wide N and the second push-up storage 21
Rclk pins receive read clock signal frequency fRclkBetween there are following relationships：
The embodiment of the present invention is made up of the first holding register, the first shift register, the first push-up storage
Parallel serial conversion unit, when the first shift register carries out data conversion, is used with realizing that parallel data is converted into serial data
First push-up storage constitutes data buffer zone, can effectively simplify the composition of the first shift register control signal, and
And first push-up storage the reading clock different from clock is write may be used to control data cached output so that simultaneously
It goes here and there the input clock of converting unit and output clock may be at different clock-domains, and then can overcome due to input clock and defeated
Go out in clock there are when clock skew all can caused by data conversion mistake；Similarly, pass through the second push-up storage, second
Shift register, the second holding register constitute serioparallel exchange unit, to realize that serial data is converted into parallel data, second
When shift register carries out data conversion, data buffer zone is constituted using the second push-up storage, can effectively simplify the
The composition of two shift register control signals, moreover, when the readings different from clock is write may be used in the second push-up storage
Clock controls data cached output so that the input clock and output clock of parallel serial conversion unit may be at different clocks
Domain, and then can overcome since there are all data conversion mistakes caused by meeting when clock skew in input clock and output clock.
The embodiments of the present invention are for illustration only, can not represent the quality of embodiment.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (8)
1. it is a kind of for data serial transmission and go here and there, serioparallel exchange device, which is characterized in that including：Receive parallel data simultaneously
The parallel serial conversion unit (1) of serial data output is converted parallel data into, and receives serial data and converts serial data
For parallel data output serioparallel exchange unit (2),
The parallel serial conversion unit (1) includes：
First holding register (11) is used for the parallel data of buffering external circuit transmission；
First shift register (12), for the parallel data cached in first holding register (11) to be converted into serially
Data；
First push-up storage (13), the serial data generated for caching first shift register (12), and adopt
Data cached output is controlled with the reading clock different from clock is write；
The serioparallel exchange unit (2) includes：
Second push-up storage (21) is used for the serial data of buffering external circuit transmission, and using different from clock is write
Reading clock control data cached output；
Second shift register (22), for the serial data cached in second push-up storage (21) to be converted into
Parallel data；
Second holding register (23), for caching the parallel data generated in second shift register (22)；
In the parallel serial conversion unit (1), the first pin (DataInValid) and first holding register of external circuit
(11) first holding register is written to control the parallel data in external circuit in the first pin (Valid) electrical connection
(11) in；The first pin (Valid) of first shift register (12) and first push-up storage (13)
First pin (WCtr) is electrically connected, when first shift register (12) converts parallel data into serial data, the
One pin (Valid) will produce write control signal, and serial data is written to control first push-up storage (13)；
When write-in serial data in first push-up storage (13), second pin (REmpty) and third pin
(Usageing) not empty signal and Usageing signals are generated respectively, and the Usageing signals indicate first first in first out
The Bit numbers of storage serial data in memory (13), external circuit are controlled described by not empty signal and Usageing signals
The output of the serial data cached in first push-up storage (13).
2. the apparatus according to claim 1, which is characterized in that first push-up storage (13) is using synchronous mould
Formula or asynchronous mode work, the second pin (clk) of first holding register (11) are connected to parallel with external circuit
The second pin (DataInClk) of the clock signal of data is electrically connected, the second pin of first shift register (12)
(clk) and the 4th pin (Wclk) of first push-up storage (13) with write clock signal is connected in external circuit
Third pin (DataWClk) electrical connection, the 5th pin (Rclk) and external electrical of first push-up storage (13)
Third pin (DATARClk) electrical connection of read clock signal is connected in road.
3. the apparatus of claim 2, which is characterized in that when first push-up storage (13) is using synchronization
When pattern, the clock signal frequency f of the parallel data of second pin (DataInClk) connection of external circuitDataInClk, it is parallel
The write clock signal frequency f of the 4th pin (Wclk) reception of data bit width N, first push-up storage (13)Wclk、
And the read clock signal frequency f that the 5th pin (Rclk) of first push-up storage (13) receivesRclkBetween deposit
In following relationship：
6th pin (Wfull) of first push-up storage (13) respectively with first holding register (11)
The third pin (Full) of third pin (Full) and first shift register (12) connects, when first first in first out
6th pin (Wfull) of memory (13) generates full scale when knowing, and can control first holding register (11) and described the
One shift register (12) suspends the input of serial data.
4. the apparatus of claim 2, which is characterized in that when first push-up storage (13) is using asynchronous
When pattern, the clock signal frequency f of the parallel data of second pin (DataInClk) connection of external circuitDataInClk, it is parallel
The write clock signal frequency f of the 4th pin (Wclk) reception of data bit width N, first push-up storage (13)Wclk
Between there are following relationships：
6th pin (Wfull) of first push-up storage (13) respectively with first holding register (11)
The third pin (Full) of third pin (Full) and first shift register (12) connects, when first first in first out
6th pin (Wfull) of memory (13) generates full scale when knowing, and can control first holding register (11) and described the
One shift register (12) suspends the input of serial data, and identifies in first shift register (12) and turn string and mistake occurs
Accidentally.
5. the apparatus according to claim 1, which is characterized in that in the serioparallel exchange unit (2), the of external circuit
Four pins (DATAInValid) are electrically connected with the first pin (WCtr) of second push-up storage (21), to control
Serial data in external circuit is written in second push-up storage (21)；Second push-up storage
(21) second pin (RData) is electrically connected with the first pin (Data) of second shift register (22), and described second
Third pin (RCtr) electricity of the second pin (Ready) of shift register (22) and second push-up storage (21)
Second shift register (22) is written to control the serial data in second push-up storage (21) in connection
In；The 4th pin (REmpty) and the 5th pin (Usaging) of second push-up storage (21) respectively with it is described
The third pin (Empty) of second shift register (22) and the electrical connection of the 4th pin (Use) are posted with controlling second displacement
Storage (22) converts serial data to parallel data；The first pin (Active) of second holding register (23) and
Two pins (Ready) respectively with the 5th pin (DataOutActive) of external circuit and the 6th pin (DataOutReady)
Electrical connection reads the parallel data cached in second holding register (23) for controlling external circuit.
6. device according to claim 5, which is characterized in that second push-up storage (21) is using synchronous mould
Formula or asynchronous mode work, the 6th pin (Wclk) of second push-up storage (21) are connected to external circuit
7th pin (DATAWClk) of write clock signal is electrically connected, the 5th pin (clk) of second shift register (22) and
7th pin (Rclk) of second push-up storage (21) is connected to the 8th of read clock signal with external circuit
Pin (DataRClk) is electrically connected, and the third pin (clk) of second holding register (23) is connected to simultaneously with external circuit
9th pin (DataOutClk) of the clock signal of row data is electrically connected.
7. device according to claim 6, which is characterized in that when second push-up storage (21) is using synchronization
When pattern, the clock signal frequency f of the parallel data of the 9th pin (DataOutClk) connection of external circuitDataOutClk, simultaneously
The write clock signal frequency of the 6th pin (Wclk) reception of row data bit width N, second push-up storage (21)
fWclkAnd the read clock signal frequency f that the 7th pin (Rclk) of second push-up storage (21) receivesRclkIt
Between there are following relationships：
8. device according to claim 6, which is characterized in that when second push-up storage (21) is using asynchronous
When pattern, the clock signal frequency f of the parallel data of the 9th pin (DataOutClk) connection of external circuitDataOutClk, simultaneously
The read clock signal frequency that 7th pin (Rclk) of row data bit width N and second push-up storage (21) receives
Rate fRclkBetween there are following relationships：
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| CN107222218B (en) * | 2017-05-26 | 2020-11-03 | 四川九洲电器集团有限责任公司 | Parallel data generation circuit and method and electronic equipment |
| CN109947681B (en) * | 2019-03-20 | 2020-12-01 | 天津芯海创科技有限公司 | Serializer/deserializer and high-speed interface protocol exchange chip |
| CN111124997B (en) * | 2019-12-25 | 2021-07-23 | 海光信息技术股份有限公司 | Data sending method, data receiving method, data sending device, data receiving device, processor chip and server |
| CN111600614B (en) * | 2020-06-04 | 2023-09-05 | 北京润科通用技术有限公司 | Coding and decoding method, device and system based on 3/4 code rate of continuous frames |
| CN115189711A (en) * | 2022-07-11 | 2022-10-14 | 天津津航计算技术研究所 | Communication equipment and transmission control method |
| CN117667777A (en) * | 2022-08-30 | 2024-03-08 | 深圳市中兴微电子技术有限公司 | Memory access control circuit and memory access control method |
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