CN205490494U - A and cluster, cluster and conversion equipment for data serial transmission - Google Patents

Abstract

The utility model discloses an and cluster, cluster and conversion equipment for data serial transmission, include: receive parallel data and convert parallel data serial data output's parallel -serial conversion unit into and receive serial data and turn into cluster and the translation unit that parallel data exported with serial data. The utility model discloses a first hold register, a shift register, a first -in first -out memory constitute parallel -serial conversion unit to realize that parallel data turns into serial data, constitute cluster and translation unit through the 2nd first -in first -out memory, the 2nd shift register, second hold register to realize that serial data turns into parallel data. The device is provided with the data buffering district, can effectively simplify data converting control signal to the device's input clock and output clock can be in different clock zones, and then can overcome the data conversion mistake that all can result in when having the clock skew owing to the input clock with in exporting the clock.

Description

For data serial transmission and go here and there, serioparallel exchange device

Technical field

The utility model relates to data transformation technology field, particularly to a kind of for data serial transmission also String, serioparallel exchange device.

Background technology

Along with the development of modern science and technology, data transmission technology have also been obtained significant progress, in data transmission During, along with clock frequency is more and more higher, during parallel transmission, interfering between parallel wires is more come The most serious, parallel transmission mode has developed into bottleneck.And serial transmission uses differential signal (differential signal) Transmission technology, effectively overcomes the interference formed signal transmission line because of antenna effect, and transmission line Crosstalk between road so that serial transmission is obtained in that the highest data transmission rate, and is extensively applied.

Existing field programmable gate array (Field Programmable Gate Array is called for short " FPGA ") In technology, in order to realize the serial transmission of data, the most first the parallel data in circuit is changed into serial Data are transmitted, then when the end of transmission, serial data are re-converted into parallel data.Wherein, in order to Realize and go here and there, serioparallel exchange, need data first first put into holding register, then existed by control signal Put in shift register and cache, produce output signal finally by counter and data are carried out defeated Go out.

But it is data cached to be dependent on shift register, there is problems in that

Control signal is complicated.In FPGA design, control signal not only controls the switching of clock frequency and also wants It is responsible for the displacement of data shift register, the buffering of data, the tally control etc. of output, so can increase control The complexity of signal processed.In FPGA, control signal is to be made up of combinational circuit, controls in high frequency clock system Signal there will be burr and maloperation.

Clock adjustability is little.In existing FPGA design the input clock in serioparallel exchange and parallel-serial conversion and Output clock ratio is changeless, and when running into data delay, the design of its control signal can be more complicated, The mistake that data all can be caused to change when there is clock skew in input clock and output clock.

Utility model content

In order to solve prior art relies on the problem of the data cached existence of shift register, the utility model Embodiment provide a kind of for data serial transmission and go here and there, serioparallel exchange device.Described technical scheme is such as Under:

The utility model embodiment provide a kind of for data serial transmission and go here and there, serioparallel exchange device, Including: receive parallel data and convert parallel data into the parallel serial conversion unit of serial data output, and connecing Receive serial data and serial data be converted into the serioparallel exchange unit of parallel data output,

Described parallel serial conversion unit includes:

First holding register, for the parallel data of buffering external circuit transmission；

First shift register, for by the parallel data conversion bunchiness of caching in described first holding register Row data；

First push-up storage, for caching the serial data that described first shift register generates, and Use the reading clock different from writing clock to control data cached output；

Described serioparallel exchange unit includes:

Second push-up storage, for the serial data of buffering external circuit transmission, and when using and write Clock different read clock control data cached output；

Second shift register, for by the serial data conversion of caching in described second push-up storage Become parallel data；

Second holding register, for caching the parallel data generated in described second shift register.

In the device that the utility model is above-mentioned, in described parallel serial conversion unit, external circuit DataInValid pin electrically connects with the Valid pin of described first holding register, controls in external circuit Parallel data write in described first holding register；The Valid pin of described first shift register and institute State the WCtr pin electrical connection of the first push-up storage, when described first shift register is by parallel data When being converted into serial data, its Valid pin can produce write control signal, advanced first to control described first Go out memory write serial data；When described first push-up storage writes serial data, its REmpty pin and Usageing pin produce not empty signal and Usageing signal, described Usageing respectively Signal represents the Bit number storing serial data in described first push-up storage, and external circuit passes through non-NULL Signal and Usageing signal control in described first push-up storage the defeated of the serial data of caching Go out.

In the device that the utility model is above-mentioned, described first push-up storage use synchronous mode or Asynchronous mode work, the clk pin of described first holding register with external circuit connects parallel data time The DataInClk pin electrical connection of clock signal, the clk pin of described first shift register and described first is first The Wclk pin entering first to go out memory is all electric with the DataWClk pin connecting write clock signal in external circuit Connecting, the Rclk pin of described first push-up storage connects read clock signal with external circuit DATARClk pin electrically connects.

In the device that the utility model is above-mentioned, when described first push-up storage uses synchronous mode, The clock signal frequency f of the parallel data of the DataInClk pin connection of external circuit_DataInClk, parallel data Write clock signal frequency f that bit wide N, the Wclk pin of described first push-up storage receive_Wclk, with And read clock signal frequency f that the Rclk pin of described first push-up storage receives_RclkBetween exist such as Lower relation:

$\frac{f_{DataInClk}}{f_{Wclk}}=\frac{f_{DataInClk}}{f_{Rclk}}=N;$

The Wfull pin of described first push-up storage respectively with the Full of described first holding register The Full pin of pin and described first shift register connects, when described first push-up storage When Wfull pin produces full scale knowledge, described first holding register can be controlled and described first shift register is temporary Stop the input of serial data.

In the device that the utility model is above-mentioned, when described first push-up storage uses asynchronous mode, The clock signal frequency f of the parallel data of the DataInClk pin connection of external circuit_DataInClk, parallel data Write clock signal frequency f that bit wide N, the Wclk pin of described first push-up storage receive_WclkBetween There is following relation:

$\frac{f_{DataInClk}}{f_{Wclk}}=N$

The Wfull pin of described first push-up storage respectively with the Full of described first holding register The Full pin of pin and described first shift register connects, when described first push-up storage When Wfull pin produces full scale knowledge, described first holding register can be controlled and described first shift register is temporary Stop the input of serial data, and identify in described first shift register and turn string and make a mistake.

In the device that the utility model is above-mentioned, in described serioparallel exchange unit, external circuit DATAInValid pin electrically connects with the WCtr pin of described second push-up storage, controls outside Serial data in circuit writes in described second push-up storage；Described second push-up storage RData pin electrically connect with the Data pin of described second shift register, described second shift register Ready pin electrically connect with the RCtr pin of described second push-up storage, to control described second Serial data in push-up storage writes in described second shift register；Described second first in first out The REmpty pin of memory and Usaging pin respectively with the Empty pin of described second shift register Electrically connect with Use pin, serial data is converted into parallel data controlling described second shift register； The Active pin of described second holding register and Ready pin respectively with external circuit DataOutActive pin and the electrical connection of DataOutReady pin, be used for controlling external circuit and read described the The parallel data of caching in two holding registers.

In the device that the utility model is above-mentioned, described second push-up storage use synchronous mode or Asynchronous mode works, and the Wclk pin of described second push-up storage writes clock with connecting in external circuit The DATAWClk pin electrical connection of signal, the clk pin of described second shift register and described second is first The Rclk pin entering first to go out memory is all electrically connected with the DataRClk pin connecting read clock signal in external circuit Connect, the clk pin of described second holding register and the clock signal connecting parallel data in external circuit DataOutClk pin electrically connects.

In the device that the utility model is above-mentioned, when described second push-up storage uses synchronous mode, The clock signal frequency f of the parallel data of the DataOutClk pin connection of external circuit_DataOutClk, and line number Write clock signal frequency f received according to the Wclk pin of bit wide N, described second push-up storage_Wclk、 And read clock signal frequency f that the Rclk pin of described second push-up storage receives_RclkBetween exist Following relation:

$\frac{f_{DataOutClk}}{f_{Wclk}}=\frac{f_{DataOutClk}}{f_{Rclk}}=N.$

In the device that the utility model is above-mentioned, when described second push-up storage uses asynchronous mode, The clock signal frequency f of the parallel data of the DataOutClk pin connection of external circuit_DataOutClk, and line number Read clock signal frequency f received according to the Rclk pin of bit wide N and described second push-up storage_Wclk Between there is following relation:

$\frac{f_{DataOutClk}}{f_{Rclk}}=N.$

The technical scheme that the utility model embodiment provides has the benefit that

Constituted by the first holding register, the first shift register, the first push-up storage and go here and there and turn Change unit, be converted into serial data realizing parallel data, the first shift register carry out data convert time, Use the first push-up storage to constitute data buffer zone, can effectively simplify the first shift register and control The composition of signal, and, the first push-up storage can use the reading clock different from writing clock to control Make data cached output so that when the input clock of parallel serial conversion unit and output clock may be at difference Clock territory, and then the number owing to all can cause when there is clock skew in input clock and output clock can be overcome According to transcription error；In like manner, posted by the second push-up storage, the second shift register, the second holding Storage constitutes serioparallel exchange unit, is converted into parallel data, at the second shift register realizing serial data Carry out data when converting, use the second push-up storage to constitute data buffer zone, can effectively simplify the The composition of two shift register control signals, and, the second push-up storage can use and write clock Different clocks of reading controls data cached output so that when the input clock of parallel serial conversion unit and output Clock may be at different clock-domains, and then can overcome owing to there is clock in input clock and output clock inclined The data transcription error that all can cause during shifting.

Accompanying drawing explanation

In order to be illustrated more clearly that the technical scheme in the utility model embodiment, embodiment will be described below The accompanying drawing used required in is briefly described, it should be apparent that, the accompanying drawing in describing below is only this Some embodiments of utility model, for those of ordinary skill in the art, are not paying creative work On the premise of, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.

Fig. 1 be the utility model embodiment provide a kind of for data serial transmission and go here and there, serioparallel exchange The structural representation of device；

Fig. 2 is the circuit diagram of a kind of parallel serial conversion unit that the utility model embodiment provides；

Fig. 3 is the circuit diagram of a kind of serioparallel exchange unit that the utility model embodiment provides.

Detailed description of the invention

For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing to this Utility model embodiment is described in further detail.

Embodiment

The utility model embodiment provide a kind of for data serial transmission and go here and there, serioparallel exchange device, Seeing Fig. 1, this device includes:

Receive parallel data and convert parallel data into the parallel serial conversion unit 1 of serial data output, and receiving Serial data is also converted into the serioparallel exchange unit 2 that parallel data exports by serial data.

Seeing Fig. 2, this parallel serial conversion unit 1 includes:

First holding register 11, for the parallel data of buffering external circuit transmission.

First shift register 12, for by the parallel data conversion bunchiness of caching in the first holding register 11 Row data.

First push-up storage 13, the serial data generated for caching the first shift register 12, and Use the reading clock different from writing clock to control data cached output.

Seeing Fig. 3, this serioparallel exchange unit 2 includes:

Second push-up storage 21, for the serial data of buffering external circuit transmission, and uses and writes Clock different read clock control data cached output.

Second shift register 22, for by the serial data conversion of caching in the second push-up storage 21 Become parallel data.

Second holding register 23, the parallel data generated in caching the second shift register 22.

In the present embodiment, when serial data changes into parallel data and parallel data is converted into serial data It is respectively provided with data buffer zone and (i.e. have employed the first push-up storage 13 and the second push-up storage 21), this buffering area can simplify control signal, eliminate the time delay occurred when data are transmitted.First is advanced first Go out memory 13 and the second push-up storage 21 1 aspect can work as data buffer zone, On the other hand, use again the reading clock different from writing clock to control data cached output so that should and go here and there, The clock of serioparallel exchange device is adjustable.

In the present embodiment, the data conversion process of said apparatus is as follows:

First the parallel data in external circuit is buffered in the first holding register 11；

Then the parallel data of caching in the first holding register 11 is converted by the first shift register 12 Become serial data；

Finally the serial data converted is buffered in the first push-up storage 13, and advanced by first First go out memory 13 and transmit to external circuit in the circuit of transmitting serial data.

Parallel data being changed into after serial data is transmitted by said process, this device also can receive string Row data also convert it into parallel data originally, and detailed process is as follows:

First the serial data in external circuit is buffered in the second push-up storage 21；

Then serial data is changed into parallel data by the second shift register 22；

Finally the parallel data converted is buffered in the second holding register 23, and is kept depositing by second Device 23 transmits to external circuit.

Specifically, see Fig. 2, in parallel serial conversion unit 1, the DataInValid pin of external circuit with The Valid pin electrical connection of the first holding register 11, controls the parallel data write the in external circuit One holding register 11 (wherein implies data line and first holding register 11 of external circuit Data pin Data pin electrical connection)；The Valid pin of the first shift register 12 and the first advanced person are first Go out the WCtr pin electrical connection of memory 13, when the first shift register 12 converts parallel data into serial During data, its Valid pin can produce write control signal, writes controlling the first push-up storage 13 (the data pin Data pin and the first advanced person that wherein imply the first shift register 12 are first to enter serial data Go out the WData pin electrical connection of memory 13)；When the first push-up storage 13 writes serial data Time, its REmpty pin and Usageing pin produce not empty signal and Usageing signal respectively, are somebody's turn to do Usageing signal represents the Bit number storing serial data in the first push-up storage 13, external circuit The serial data of caching in the first push-up storage 13 is controlled by not empty signal and Usageing signal Output.

In the present embodiment, parallel data pin Data [N-1,0] (the wherein width of parallel data of external circuit Degree is the positive integer more than 1 for N, N) electrically connect with the Data pin of the first holding register 11, it is used for Transmission parallel data, the Data In Valid pin of external circuit and the Valid pin of the first holding register 11 Electrical connection, is used for producing Data In Valid signal and writes in the first holding register 11 to control parallel data Cache.The Valid pin of the first shift register 12 and the WCtr of the first push-up storage 13 Pin electrically connects, the Data pin of the first shift register 12 and the WData of the first push-up storage 13 Pin electrically connects, and the first shift register 12, when carrying out parallel data and being converted into serial data, can produce and write Enter control signal, i.e. control the first push-up storage 13 and write the control signal of serial data.In reality In application, it is only necessary to demarcating parallel data is effectively write control signal, it is possible to be greatly simplified the first displacement The control signal of register 12.The REmpty pin of the first push-up storage 13 and external circuit DATA Out Valid pin electrically connects, the Usageing pin of the first push-up storage 13 and external electrical The DataUsageing pin electrical connection on road, the TCtr pin of the first push-up storage 13 and external electrical The DATA Out Ready pin electrical connection on road, so, external circuit passes through the first push-up storage 13 The not empty signal produced and Usageing signal control the serial number of caching in the first push-up storage 13 According to output.Additionally, the WRst pin of the first push-up storage 13 (i.e. writing reset pin), first The Rst pin (i.e. reset pin) of shift register 12, the first holding register 11 Rst pin (i.e. Reset pin) all electrically connect with the DataWRst pin of external circuit；First push-up storage 13 RRst pin (i.e. reading reset pin) electrically connects with the DataR Rst pin of external circuit.Additionally, first is first The degree of depth entering first to go out memory 13 can set according to the actual requirements, does not limits.

Further, the first push-up storage 13 can use synchronous mode or asynchronous mode work, The clk pin (i.e. clock pins) of the first holding register 11 with external circuit connects parallel data time The Data In Clk pin electrical connection of clock signal, the clk pin (i.e. clock pins) of the first shift register 12 All connect with external circuit with the Wclk pin (i.e. writing clock pins) of the first push-up storage 13 DataWClk pin (i.e. data the write clock pins) electrical connection of write clock signal, the first first in first out storage Rclk pin (i.e. reading clock pins) and the DATARClk connecting read clock signal in external circuit of device 13 Pin electrically connects.

In the present embodiment, the write clock signal of the first push-up storage 13 connection is with read clock signal not With, when the first push-up storage 13 uses synchronous mode, between write clock signal and read clock signal There is association, when the first push-up storage 13 uses asynchronous mode, write clock signal is believed with reading clock Association is there is not between number.

Further, when the first push-up storage 13 uses synchronous mode, external circuit The clock signal frequency f of the parallel data of DataInClk pin connection_DataInClk, parallel data bit wide N, first Write clock signal frequency f that the Wclk pin of push-up storage 13 receives_Wclk, and first advanced first Go out read clock signal frequency f that the Rclk pin of memory 13 receives_RclkBetween there is following relation:

$\frac{f_{DataInClk}}{f_{Wclk}}=\frac{f_{DataInClk}}{f_{Rclk}}=N;$

The Wfull pin (i.e. writing full pin) of the first push-up storage 13 keeps depositing with first respectively The Full pin (i.e. expiring signal pins) of device 11 and the Full pin of the first shift register 12 connect, when When the Wfull pin of the first push-up storage 13 produces full scale knowledge, the first holding register 11 can be controlled With the input that the first shift register 12 suspends serial data.

Further, when the first push-up storage 13 uses asynchronous mode, external circuit The clock signal frequency f of the parallel data of DataInClk pin connection_DataInClk, parallel data bit wide N, first Write clock signal frequency f that the Wclk pin of push-up storage 13 receives_WclkBetween there is following relation:

$\frac{f_{DataInClk}}{f_{Wclk}}=N;$

The Wfull pin of the first push-up storage 13 respectively with the Full pin of the first holding register 11 Connect, when the Wfull of the first push-up storage 13 draws with the Full pin of the first shift register 12 When pin produces full scale knowledge, the first holding register 11 can be controlled and the first shift register 12 suspends serial number According to input, and identify in the first shift register 12 and turn string and make a mistake.

Specifically, see Fig. 3, in serioparallel exchange unit 2, the DATAInValid pin of external circuit with The WCtr pin electrical connection of the second push-up storage 21, the serial data controlled in external circuit is write Enter in the second push-up storage 21, wherein, the DATAIn pin of external circuit and the second first in first out The Wdata pin electrical connection of memory 21, the WFull pin of the second push-up storage 21 is with outside The DATAInReady pin electrical connection of circuit, such second push-up storage 21 is by WCtr pin External circuit write serial data is controlled with WFull pin.The RData of the second push-up storage 21 The Data pin electrical connection of pin and the second shift register 22, the Ready of the second shift register 22 draws The RCtr pin electrical connection of pin and the second push-up storage 21, to control the second push-up storage Serial data in 21 writes in the second shift register 22.The REmpty of the second push-up storage 21 Pin and Usaging pin electrically connect with Empty pin and the Use pin of the second shift register 22 respectively, Serial data being converted into parallel data controlling the second shift register 22, wherein, Usaging pin produces What raw Uasging signal represented is the Bit number of valid data in the second push-up storage 21.Second The Active pin of holding register 23 and Ready pin DataOutActive with external circuit respectively draws Pin and the electrical connection of DataOutReady pin, be used for controlling external circuit and read in the second holding register 23 The parallel data of caching.Additionally, the RRst pin of the second push-up storage 21 (i.e. reading reset pin), The Rst pin (i.e. reset pin) of the second shift register 22, the Rst pin of the second holding register 23 (i.e. reset pin) all electrically connects with the DataRRst pin of external circuit；Second push-up storage 21 WRst pin (i.e. writing reset pin) electrically connect with the DataWRst pin of external circuit.

In the present embodiment, the degree of depth of the second push-up storage 21 can set according to the actual requirements, this In do not limit.

Further, the second push-up storage 21 can use synchronous mode or asynchronous mode work, The Wclk pin of the second push-up storage 21 connects write clock signal with external circuit DATAWClk pin electrically connects, the clk pin of the second shift register 22 and the second push-up storage The Rclk pin of 21 all electrically connects with the DataRClk pin connecting read clock signal in external circuit, and second The clk pin of holding register 23 and the DataOutClk of the clock signal connecting parallel data in external circuit Pin electrically connects.

In the present embodiment, the write clock signal of the second push-up storage 21 connection is with read clock signal not With, when the second push-up storage 21 uses synchronous mode, between write clock signal and read clock signal There is association, when the second push-up storage 21 uses asynchronous mode, write clock signal is believed with reading clock Association is there is not between number.

Further, when the second push-up storage 21 uses synchronous mode, external circuit The clock signal frequency f of the parallel data of DataOutClk pin connection_DataOutClk, parallel data bit wide N, Write clock signal frequency f that the Wclk pin of two push-up storages 21 receives_Wclk, and second advanced First go out read clock signal frequency f that the Rclk pin of memory 21 receives_RclkBetween there is following relation:

$\frac{f_{DataOutClk}}{f_{Wclk}}=\frac{f_{DataOutClk}}{f_{Rclk}}=N.$

Further, when the second push-up storage 21 uses asynchronous mode, external circuit The clock signal frequency f of the parallel data of DataOutClk pin connection_DataOutClk, parallel data bit wide N, with And second push-up storage 21 Rclk pin receive read clock signal frequency f_RclkBetween exist as follows Relation:

$\frac{f_{DataOutClk}}{f_{Rclk}}=N.$

The utility model embodiment passes through the first holding register, the first shift register, the first first in first out Memory constitutes parallel serial conversion unit, is converted into serial data, at the first shift LD realizing parallel data When device carries out data conversion, use the first push-up storage to constitute data buffer zone, can effectively simplify The composition of the first shift register control signal, and, when the first push-up storage can use and write Clock different read clock control data cached output so that the input clock of parallel serial conversion unit and output Clock may be at different clock-domains, and then can overcome owing to there is clock in input clock and output clock The data transcription error that all can cause during skew；In like manner, by the second push-up storage, the second displacement Register, the second holding register constitute serioparallel exchange unit, are converted into parallel data realizing serial data, When the second shift register carries out data conversion, the second push-up storage is used to constitute data buffer zone, Can effectively simplify the composition of the second shift register control signal, and, the second push-up storage can To use different from writing clock reading clock to control data cached output so that parallel serial conversion unit defeated Enter clock and output clock may be at different clock-domains, and then when can overcome due to input clock and output The data transcription error that all can cause when there is clock skew in clock.

Above-mentioned the utility model embodiment sequence number, just to describing, does not represent the quality of embodiment.

The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all Within spirit of the present utility model and principle, any modification, equivalent substitution and improvement etc. made, all should wrap Within being contained in protection domain of the present utility model.

Claims (9)

1. one kind for data serial transmission and go here and there, serioparallel exchange device, it is characterised in that including: connect Receive parallel data and convert parallel data into the parallel serial conversion unit (1) of serial data output, and receiving string Serial data is also converted into the serioparallel exchange unit (2) that parallel data exports by row data,

Described parallel serial conversion unit (1) including:

First holding register (11), for the parallel data of buffering external circuit transmission；

First shift register (12), for by the also line number of caching in described first holding register (11) According to being converted into serial data；

First push-up storage (13), is used for caching the string that described first shift register (12) generates Row data, and use the reading clock different from writing clock to control data cached output；

Described serioparallel exchange unit (2) including:

Second push-up storage (21), for the serial data of buffering external circuit transmission, and use with Write the different reading clock of clock to control data cached output；

Second shift register (22), for by the string of caching in described second push-up storage (21) Row data are converted into parallel data；

Second holding register (23), is used for caching the parallel of the middle generation of described second shift register (22) Data.

Device the most according to claim 1, it is characterised in that in described parallel serial conversion unit (1) In, first pin (DataInValid) of external circuit draws with the first of described first holding register (11) Pin (Valid) electrically connects, and controls the parallel data in external circuit and writes described first holding register (11) In；First pin (Valid) of described first shift register (12) and described first first in first out storage First pin (WCtr) electrical connection of device (13), when described first shift register (12) is by also line number According to when being converted into serial data, its first pin (Valid) can produce write control signal, described to control First push-up storage (13) write serial data；When described first push-up storage (13) During middle write serial data, its second pin (REmpty) and the 3rd pin (Usageing) produce respectively Not empty signal and Usageing signal, described Usageing signal represents described first push-up storage (13) storing the Bit number of serial data in, external circuit is controlled by not empty signal and Usageing signal Make the output of the serial data of caching in described first push-up storage (13).

Device the most according to claim 2, it is characterised in that described first push-up storage (13) Use synchronous mode or asynchronous mode work, second pin (clk) of described first holding register (11) The second pin (DataInClk) electrical connection of the clock signal of parallel data is connected with external circuit, described Second pin (clk) of the first shift register (12) and described first push-up storage (13) 4th pin (Wclk) is all electric with the 3rd pin (DataWClk) connecting write clock signal in external circuit Connect, the 5th pin (Rclk) of described first push-up storage (13) with external circuit connects reading 3rd pin (DATARClk) electrical connection of clock signal.

Device the most according to claim 3, it is characterised in that when described first push-up storage (13) when using synchronous mode, the parallel data that second pin (DataInClk) of external circuit connects Clock signal frequency f_DataInClk, parallel data bit wide N, the of described first push-up storage (13) Write clock signal frequency f that four pins (Wclk) receive_Wclk, and described first push-up storage (13) Read clock signal frequency f that receives of the 5th pin (Rclk)_RclkBetween there is following relation:

$\frac{f_{DataInClk}}{f_{Wclk}}=\frac{f_{DataInClk}}{f_{Rclk}}=N;$

6th pin (Wfull) of described first push-up storage (13) keeps with described first respectively 3rd pin (Full) of register (11) and the 3rd pin (Full) of described first shift register (12) Connect, when the 6th pin (Wfull) of described first push-up storage (13) produces full scale knowledge, Described first holding register (11) can be controlled and described first shift register (12) suspends serial data Input.

Device the most according to claim 3, it is characterised in that when described first push-up storage (13) when using asynchronous mode, the parallel data that second pin (DataInClk) of external circuit connects Clock signal frequency f_DataInClk, parallel data bit wide N, the of described first push-up storage (13) Write clock signal frequency f that four pins (Wclk) receive_WclkBetween there is following relation:

$\frac{f_{DataInClk}}{f_{Wclk}}=N;$

6th pin (Wfull) of described first push-up storage (13) keeps with described first respectively 3rd pin (Full) of register (11) and the 3rd pin (Full) of described first shift register (12) Connect, when the 6th pin (Wfull) of described first push-up storage (13) produces full scale knowledge, Described first holding register (11) can be controlled and described first shift register (12) suspends serial data Input, and identify in described first shift register (12) and turn string and make a mistake.

Device the most according to claim 1, it is characterised in that described serioparallel exchange unit (2) In, the 4th pin (DATAInValid) of external circuit and described second push-up storage (21) First pin (WCtr) electrically connects, and controls the serial data write described second in external circuit advanced first Go out in memory (21)；Second pin (RData) of described second push-up storage (21) and institute State the first pin (Data) electrical connection of the second shift register (22), described second shift register (22) The 3rd pin (RCtr) electricity of the second pin (Ready) and described second push-up storage (21) Connect, to control described second displacement of serial data write in described second push-up storage (21) In register (22)；4th pin (REmpty) of described second push-up storage (21) and Five pins (Usaging) respectively with the 3rd pin (Empty) of described second shift register (22) and 4th pin (Use) electrical connection, is converted into serial data controlling described second shift register (22) Parallel data；First pin (Active) of described second holding register (23) and the second pin (Ready) Electric with the 5th pin (DataOutActive) of external circuit and the 6th pin (DataOutReady) respectively Connect, be used for controlling external circuit and read the parallel data of caching in described second holding register (23).

Device the most according to claim 6, it is characterised in that described second push-up storage (21) Use synchronous mode or asynchronous mode work, the 6th pin of described second push-up storage (21) (Wclk) with the 7th pin (DATAWClk) electrical connection connecting write clock signal in external circuit, institute State the 5th pin (clk) and described second push-up storage (21) of the second shift register (22) The 7th pin (Rclk pin) all with the 8th pin (DataRClk) connecting read clock signal in external circuit Electrical connection, the 3rd pin (clk) of described second holding register (23) with external circuit connects parallel 9th pin (DataOutClk) electrical connection of the clock signal of data.

Device the most according to claim 7, it is characterised in that when described second push-up storage (21) when using synchronous mode, the parallel data that the 9th pin (DataOutClk) of external circuit connects Clock signal frequency f_DataOutClk, parallel data bit wide N, the of described second push-up storage (21) Write clock signal frequency f that six pins (Wclk) receive_Wclk, and described second push-up storage (21) Read clock signal frequency f that receives of the 7th pin (Rclk)_RclkBetween there is following relation:

$\frac{f_{DataOutClk}}{f_{Wclk}}=\frac{f_{DataOutClk}}{f_{Rclk}}=N.$

Device the most according to claim 7, it is characterised in that when described second push-up storage (21) when using asynchronous mode, the parallel data that the 9th pin (DataOutClk) of external circuit connects Clock signal frequency f_DataOutClk, parallel data bit wide N and described second push-up storage (21) Read clock signal frequency f that receives of the 7th pin (Rclk)_RclkBetween there is following relation:

$\frac{f_{DataOutClk}}{f_{Rclk}}=N.$