CN108462620B - Gilbert-level SpaceWire bus system - Google Patents
Gilbert-level SpaceWire bus system Download PDFInfo
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- CN108462620B CN108462620B CN201810139172.5A CN201810139172A CN108462620B CN 108462620 B CN108462620 B CN 108462620B CN 201810139172 A CN201810139172 A CN 201810139172A CN 108462620 B CN108462620 B CN 108462620B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2589—Bidirectional transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
Abstract
A gigabit class SpaceWire bus system, the system comprising: the device comprises a data transceiving module, a data buffering module, a SpaceWire protocol processing module and a data processing module. The data transceiver module is used for carrying out format conversion on the 16B/20B code and the parallel data of the optical transceiver; the data buffer module is used for synchronizing the asynchronous clock domain and caching data; the SpaceWire protocol processing module is used for receiving and transmitting bus data, identifying control codes and data characters, updating a protocol state, sending uplink data and addresses and receiving downlink data and addresses; the data processing module is used for providing bus interfaces for the SpaceWire protocol processing module, the external CPU, the external memory and the external register and providing conversion of bus protocols on AXI and APB chips. The invention reduces the access times and time, improves the utilization rate of the bus, and meets the requirement of high-speed data transmission of the spacecraft.
Description
Technical Field
The invention relates to a gigabit-class SpaceWire bus system, and belongs to the technical field of high-speed data transmission buses of spacecrafts.
Background
SpaceWire is a full-duplex, bidirectional, serial, point-to-point data bus. In each direction, it transmits the encoded data using a pair of differential signal lines. There are thus four signal lines (D +, D-, S +, S-) in each direction, for a total of eight signal lines in both directions. The SpaceWire standard relates to six levels of content, which are respectively: the device comprises six layers, namely a physical layer, a signal layer, a character layer, a switching layer, a data cladding layer and a network layer. The physical layer standard covers four parts of a cable, a connector, a cable assembly and printed circuit board routing (PCB tracks). The SpaceWire cable comprises 4 groups of independent shielding twisted pairs inside and a layer of shielding material outside. The signal layer standard specifies signal voltage levels, noise margins, and signal coding. The signal layer is encoded with DS (Data-Strobe). The code can transmit the clock signal and the data signal together through two signals D and S. At the receiving end, the recovery of the clock signal is realized by XOR-ing the D signal and the S signal.
Star-Dundee in the United kingdom has implemented SpaceWire bus IP (Intelligent Property) according to the SpaceWire standard, and popularized the IP in the aerospace field, and is currently in the market mainstream. But in a bus system taking the SpaceWire IP of the Star-Dundee company as a core, a physical medium adopts a cable, the bandwidth is generally only hundreds of megabits, and the gigabit level is difficult to achieve; secondly, DS coding is essentially one-way clock with one-way data, if the data transmission rate exceeds 1Gbps, the clock period is less than 1ns, the technical realization difficulty is very high, and therefore the data transmission rate which can be actually achieved is only 200 Mbps; furthermore, the data access interface of the current bus system is 32-bit wide, and the memory needs to be accessed 1 time after 4 SpaceWire data characters (1 data character is 8-bit data) are sent or received, so that the memory access times are large, the memory waiting time is long, and the bus utilization rate is low.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: overcomes the defects of the prior art and provides a Gilbert-level SpaceWire bus system. The data transmission rate of the bus system is improved to be more than 1Gbps, the data width of the memory access interface is increased to 128 bits, the time overhead of accessing the memory is reduced, and the requirement of a spacecraft electronic system on the transmission of the Gbit-level data can be met.
The technical scheme of the invention is as follows:
a gigabit class SpaceWire bus system comprising: the system comprises a data transceiving module, a data buffering module, a SpaceWire protocol processing module and a data access module;
a data receiving and transmitting module: receiving a serial code sent by an external optical transceiver, converting the serial code into parallel data and sending the parallel data to a data buffer module; receiving parallel data sent by the data buffer module, converting the parallel data into serial codes and sending the serial codes to an external optical transceiver;
the data buffer module: receiving parallel data sent by the data transceiver module and the SpaceWire protocol processing module, synchronously processing the parallel data sent by the data transceiver module and the SpaceWire protocol processing module, and sending the synchronized parallel data and the clock to the SpaceWire protocol processing module;
the SpaceWire protocol processing module: receiving the synchronized parallel data and the clock sent by the data buffer module, and reading the parallel data on the rising edge of the clock; receiving downlink data and a downlink data address sent by a data access module, generating parallel data, and sending the generated parallel data and a sending clock generated by the data access module to a data buffer module; extracting configuration information according to a register address in the downlink data address to set a preset parameter, generating uplink data and an address according to the current protocol state and the preset parameter, and sending the uplink data and the address to a data access module;
a data access module: receiving data and addresses sent by an external memory, and sending the data and the addresses to an external CPU and a SpaceWire protocol processing module; receiving data and addresses sent by a SpaceWire protocol processing module and an external CPU, and sending the data and the addresses to an external memory; receiving data and addresses sent by an external register, converting the data and the addresses through an on-chip bus protocol, and sending the converted data and addresses to an external CPU and a SpaceWire protocol processing module; and receiving data and addresses sent by the SpaceWire protocol processing module and an external CPU, and sending the data and the addresses to an external register after protocol conversion.
The data transceiving module includes: a gigabit transmitting module and a gigabit receiving module;
a gigabit transmission module: receiving parallel data sent by the data buffer module, converting the parallel data into serial codes with a gigabit rate, and outputting the serial codes to an external optical transceiver;
a gigabit receiving module: the 16B/20B serial code sent by an external optical transceiver is received, the 16B/20B serial code is converted into parallel data with a gigabit rate, and then the parallel data is output to the data buffer module.
The SpaceWire protocol processing module comprises: the system comprises a receiving control module, a control code processing module, a sending control module, a sending clock module and an operation management module;
a receiving control module: receiving the synchronized parallel data and clock sent by the data buffer module, reading the parallel data at the rising edge of the clock, identifying a control code and a data character in the parallel data, sending the control code to the control code processing module, and sending the data character to the operation management module;
the control code processing module: receiving a control code sent by a receiving control module, extracting a control signal, and then sending the control signal to an operation management module;
the operation management module: receiving a control signal sent by a control code processing module, generating a new protocol state according to a preset parameter and a current protocol state, expanding the control signal into 128-bit uplink data, and sending the 128-bit uplink data and a target address of the uplink data generated by the control signal to an external data access module; receiving data characters sent by a receiving control module, splicing the data characters into 128-bit uplink data, and sending the 128-bit uplink data and a target address of the uplink data generated by the 128-bit uplink data to an external data access module; receiving downlink data and addresses of the downlink data sent by an external data access module, extracting configuration information to set preset parameters if the addresses of the registers are the addresses, and sending the downlink data to a sending control module as 128-bit data if the addresses of the memories are the addresses; sending a control signal to a sending control module; generating a sending rate selection signal according to preset parameters and sending the sending rate selection signal to a sending clock module;
a sending clock module: receiving a sending rate selection signal sent by the operation management module, generating a sending clock signal, and sending the sending clock signal to the sending control module;
a transmission control module: and receiving a transmission control signal, 128-bit data and a transmission clock signal transmitted by the transmission clock module, wherein the transmission control signal, the 128-bit data and the transmission clock signal are transmitted by the operation management module, and when the transmission control signal is at a high level, the 128-bit data is decomposed into a plurality of parallel data and is transmitted to the external data buffer module together with the transmission clock signal.
The data access module includes: an AXI bus interface module and an APB bus interface module;
AXI bus interface module: receiving data and addresses sent by a SpaceWire protocol processing module or a CPU (Central processing Unit), and sending the data and the addresses to an external memory; receiving data and addresses sent by an external CPU and sending the data and the addresses to an external memory;
receiving data and an address sent by an external memory, if the AXI bus transaction is initiated by a SpaceWire protocol processing module, sending the data and the address to the SpaceWire protocol processing module, and if the AXI bus transaction is initiated by an external CPU, sending the data and the address to the external CPU;
receiving data and addresses sent by a SpaceWire protocol processing module or a CPU (Central processing Unit), and sending the data and the addresses to an APB (advanced peripheral bus) bus interface module;
receiving data and an address sent by an APB bus interface module, if the AXI bus transaction is initiated by a SpaceWire protocol processing module, sending the data and the address to the SpaceWire protocol processing module, and if the AXI bus transaction is initiated by an external CPU, sending the data and the address to the external CPU;
APB bus interface module: receiving data and an address of an AXI bus interface module, converting the data and the address by an on-chip bus protocol, and sending the converted data and the converted address to an external register; and receiving data and addresses of an external register, and sending the data and the addresses to the AXI bus interface module after protocol conversion.
The parallel data is 16 bits.
The serial code is a 16B/20B serial code.
The external memory is a 128-bit memory.
Compared with the prior art, the invention has the beneficial effects that:
1) by adopting a 16B/20B coding technology and taking the optical fiber as a physical medium for SpaceWire bus transmission, the upper limit of physical bandwidth is improved, and the maximum data transmission rate can reach 1 Gbps;
2) the data processing adopts a parallel processing mode, so that 16-bit information can be processed in one clock cycle, and the data processing capacity is increased to 16 times of DS coding;
3) the memory access interface with the width of 128 bits is adopted, the data volume of one-time reading and writing is improved, the memory access times and time are reduced in the transmission process, and the bus utilization rate is improved.
Drawings
FIG. 1 is a block diagram of a system according to the present invention;
FIG. 2 is a 16-bit parallel data format;
FIG. 3 is a state diagram of the operation management unit;
fig. 4 is a detailed block diagram of the data access module.
Detailed Description
The specific embodiment is as follows.
(1) System architecture
An example of a system architecture of a gigabit SpaceWire bus system is shown in FIG. 1.
In fig. 1, the bus system comprises: the system comprises 4 core modules, namely a data transceiver module, a data buffer module, a SpaceWire protocol processing module and a data access module, and also comprises an optical transceiver, a CPU, a 128-bit memory and a group of 32-bit registers on the periphery. In each peripheral unit, an optical transceiver is a physical interface for photoelectric signal conversion, a CPU is a carrier for running bus application software, a 128-bit memory is used for storing bus data packets to be sent and received, and a 32-bit register is used for recording bus running state and configuration information. Detailed embodiments of the core module of the bus system are discussed subsequently.
(2) Data receiving and transmitting module
The data transceiver module is designed based on an optical fiber link, the physical bandwidth exceeds 10Gbps, and 16B/20B coding is adopted to transmit data. Receiving a serial code sent by an external optical transceiver, converting the serial code into 16-bit parallel data and sending the data to a data buffer module; and receiving the 16-bit parallel data sent by the data buffer module and sending the data to an external optical transceiver.
The data transceiver module comprises a gigabit transmitting module and a gigabit receiving module. A gigabit transmission module: receiving 16-bit parallel data sent by a data buffer module, converting the data into 16B/20B serial codes with a gigabit rate, and outputting the serial codes to an external optical transceiver; the gigabit receiving module receives the 16B/20B serial code sent by the external optical transceiver, converts the 16B/20B serial code into 16-bit parallel data with a gigabit level rate, and then outputs the data to the data buffer module.
The gigabit transmission module converts the 16-bit parallel data into 16B/20B serial data through a high-speed 16B/20B SERDES; the gigabit receiving module converts the 16B/20B serial data into 16-bit parallel data through the 16B/20B SERDES. The 16B/20BSERDES in the gigabit transmission module and the gigabit receiving module are the same, the signals provided to the data buffer module are 16-bit parallel data and 1-path working clock, and the working clock is divided into a fast clock and a slow clock, wherein the frequency of the fast clock is 166.67 MHz. Since 16 bits of data can be transmitted or received in one clock cycle, the maximum data amount that can be transmitted or received in 1 second is:
it is thus known that the maximum data transmission rate theoretically achievable is 2.133 Gbps.
(3) Data buffer module
The data buffer module synchronizes two asynchronous clocks through a double clock FIFO (First Input First Output, First in First out queue): the clock of the data transceiver module and the clock of the SpaceWire protocol processing module, and the transmitted and received data are cached. The capacity of the FIFO is 1024 bits and 16 bits, which can effectively buffer the problem of inconsistent receiving and transmitting speed caused by clock deviation between two asynchronous systems, thereby enabling the receiving and transmitting process to be coordinated and smooth and transmitting the synchronized 16-bit parallel data and clock to the SpaceWire protocol processing module.
(4) SpaceWire protocol processing module
Receiving the synchronized 16-bit parallel data and the clock sent by the data buffer module, and reading the 16-bit parallel data on the rising edge of the clock;
receiving downlink data and a downlink data address sent by a data access module, generating 16-bit parallel data, and sending the generated 16-bit parallel data and a sending clock generated by the data access module to a data buffer module;
extracting configuration information according to a register address in a downlink data address to set preset parameters;
and generating uplink data and addresses according to the current protocol state and preset parameters and sending the uplink data and the addresses to the data access module.
The space wire protocol IP of the Star-Dundee company is based on DS coding, then the D signal and the S signal are subjected to exclusive OR to generate a clock signal, the D signal is used as a data signal, the data signal of the invention adopts 16-bit parallel data, a fast clock is 166.67MHz signal, and a slow clock is 10MHz signal. Based on the improvement of the two aspects, a receiving control module, a control code processing module, a sending control module, a sending clock module and an operation management module which are matched are designed, so that the maximum data processing capacity exceeds 1 Gbit/s.
1) Receiving control module
The receiving control module firstly needs to identify the control characters and the data characters of the 16-bit parallel data input by the data buffer module. The information identification is premised on the fact that the check bits are correct, otherwise the error signal PARITY _ ERR will be verified. The recognition process is carried out based on the 16-bit parallel data format (as shown in fig. 2) defined in the present invention, the highest two bits are length fields indicating the length of the valid information, where 00 indicates the information length of 4 (representing control characters), 01 indicates the information length of 8 (representing NULL control codes), 10 indicates the information length of 10 (representing data characters), and 11 indicates the information length of 14 (representing time codes). On the basis of information identification, the receiving control module executes the following steps:
step 1: if the information type is the control character FCT, jumping to the step 5 after setting a GOT _ FCT signal;
step 2: if the information type is a NULL control code, setting a GOT _ FIRST _ NULL signal and then jumping to the step 5;
and step 3: if the information type is EOP, EEP or data character, eliminating the high 2-bit additional information of the data character, outputting low 8-bit data, and then executing step 5;
and 4, step 4: setting a GOT _ NCHAR signal and then turning to the step 5;
and 5: calculating a check value according to bitwise XOR, updating a global check signal, and turning to the step 6;
step 6: and sending the PARITY _ ERR, GOT _ FIRST _ NULL, GOT _ FCT and GOT _ NCHAR signals to the control code processing module.
After the above steps are completed, the receiving control module will continue to wait for the arrival of the next 16-bit parallel data, and then start the next processing procedure.
2) Control code processing module
The control code processing module is responsible for calculating the reception CREDIT, generating a CREDIT error signal CREDIT _ ERR to be sent to the operation management module, and sending the signal from the reception control module to the operation management module.
To calculate the receiving credit, the control code processing module internally maintains a virtual receiving buffer with a size of 2KB, defines a receiving START pointer START _ PTR and a receiving END pointer END _ PTR, and has the specific working procedures as follows: in the initial state, START _ PTR and END _ PTR are both cleared to 0, indicating that the receive buffer is empty. Whenever the GOT _ NCHAR signal is active, it indicates that a data word was received, and END _ PTR is incremented in sequence until the difference between END _ PTR and START _ PTR is greater than or equal to the predetermined maximum credit value of 1024, at which point the depletion of the received credit triggers a buffer full signal and further inhibits reception. Assertion of the GOT _ NCHAR signal triggers a read operation to the memory, and each time a successful read operation is performed, the START of reception pointer START _ PTR is sequentially incremented until the difference between END _ PTR and START _ PTR is 0, indicating that all of the received data has been read. If it occurs during the above operation that the difference between the reception end pointer and the reception start pointer is greater than 1024 or less than 0, the CREDIT error signal CREDIT _ ERR is enabled.
3) Transmission control module
The input signals of the transmission control module are three: the transmission control signal sent by the running management module, the 128-bit data and the transmission clock signal sent by the transmission clock module. The main task of this module is to split 128 bits of data into a plurality of 16 bits of parallel data to be sent to the data buffer module along with the transmit clock signal when the transmit control signal is active. The decomposition process of 128-bit long data is as follows: reading 128-bit transmission data into a 128-bit internal register SENDATA _ REG by using a rising edge of a transmission clock when the transmission control signal becomes active; taking out parallel data from the lower 16 bits of the SENDATA _ REG at each rising edge of the sending clock, and then shifting the value of the SENDATA _ REG by 16 bits to the right so that the lower 16 bits are always 16-bit parallel data to be taken out next time; after 8 times of read and right shift operations to the SENDATA _ REG, the decomposition process of the 128-bit data is completed.
4) Transmission clock module
The transmission clock module selects the working clock of the transmission control module according to the transmission rate selection signal transmitted by the operation management module. When the transmission rate selection signal is at a high level, the 166.67MHz fast clock generated by the internal clock management unit is output to the transmission control module as a transmission clock signal. And when the sending rate selection signal is at a low level, outputting the 10MHz slow clock generated by the internal clock management unit as a sending clock signal to the sending control module.
5) Operation management module
Receiving a control signal sent by a control code processing module, generating a new protocol state according to a preset parameter and a current protocol state, expanding the control signal into 128-bit uplink data, and sending the 128-bit uplink data and a target address of the uplink data generated by the control signal to an external data access module; receiving data characters sent by a receiving control module, splicing the data characters into 128-bit uplink data, and sending the 128-bit uplink data and a target address of the uplink data generated by the 128-bit uplink data to an external data access module; receiving downlink data and addresses of the downlink data sent by an external data access module, extracting configuration information to set preset parameters if the addresses of the registers are the addresses, and sending the downlink data to a sending control module as 128-bit data if the addresses of the memories are the addresses; sending a control signal to a sending control module; generating a sending rate selection signal according to preset parameters and sending the sending rate selection signal to a sending clock module;
the implementation of the operation management module is based on a state diagram as shown in fig. 3. Fig. 3 contains 6 states in total: ERR _ RESET, ERR _ WAIT, READY, STARTED, CONNECTING, RUN. The ERR _ RESET is an initial state of the operation management module and enters after an error occurs in the system RESET or operation process; ERR _ WAIT is a waiting state after state RESET, and enters after being in an ERR _ RESET state for 6.4 us; READY is READY and enters 12.8us after being in ERR _ WAIT state; STARTED is a running starting state, entering when LINK _ ENABLE bit in an external register is set to 1 when the external register is in a READY state, and allowing sending of NULL control code and receiving of control information in the STARTED state; the CONNECTING is in a connection state, enters when being in a STARTED state and receiving a GOT _ NULL control signal, and allows to send FCT control codes and NULL control codes and receive control information in the CONNECTING state; RUN is a normal operation state, which is entered when in a CONNECTING state and receiving a GOT _ FCT control signal, and allows FCT control code, NULL control code, and NCHAR data words to be transmitted while allowing data to be received and performing a splicing operation on the data in the RUN state.
The operation management module can output the transmission control signal and the parallel data to the transmission control module in three states of STARTED, CONNECTING and RUN. In a STARTED state, outputting parallel data as a NULL control code when a sending control signal is effective; under the CONNECTING state, when the sending control signal is effective, the output parallel data is FCT or NULL control code; in the RUN state, the parallel data output when the transmit control signal is active is an FCT control code, a NULL control code, or an NCHAR data word.
The sending RATE selection signal output by the running management module to the sending clock module is determined by a SEND _ RATE bit in an external register, and the sending RATE selection signal is in a high level when the bit is 1, otherwise, the sending RATE selection signal is in a low level.
The operation management module generates the uplink data sent by the data access module by receiving the data and executing the splicing operation in the RUN state, the initial value of the 32-bit address is determined by the receiving storage address stored in the external register, and the accumulation calculation is executed after each data receiving to form a new 32-bit address.
(5) Data access module
The data access module provides an access interface to the memory and the register for the SpaceWire protocol processing module and the CPU, as shown in fig. 4. In the example of fig. 4, the data access modules include an AXI bus interface module and an APB bus interface module. The AXI bus interface module provides three groups of interface signals: the system comprises a CPU interface, a protocol processing module (protocol IP) interface and a memory interface, wherein the three groups of interfaces all follow the AXI bus standard and are isomorphic in structure; the APB bus interface module provides a set of interface signals: a register interface, the interface conforming to the APB bus standard.
In the data access module, the AXI on-chip bus is used for interconnecting the bus system SpaceWire protocol processing module, the external CPU and the memory at high speed. The memory is realized by a DPRAM (Dual Port RAM) so that the external CPU and the internal SpaceWire protocol processing module can access the memory simultaneously. The data width of the external memory interface is 128 bits, and the read-write data volume of one access is obviously increased through the oversized data access interface. The low-speed register is hung on the AXI bus by adopting a 128-bit to 32-bit width converter, an AXI to AHB protocol converter, an AHB-APB bus bridge and a 32-bit APB on-chip bus, so that the external CPU and the internal SpaceWire protocol processing module can configure the register and check the state of the register.
Specifically, the method comprises the steps of receiving data and addresses sent by an external memory, and sending the data and the addresses to an external CPU and a SpaceWire protocol processing module; receiving data and addresses sent by a SpaceWire protocol processing module and an external CPU, and sending the data and the addresses to an external memory;
receiving data and addresses sent by an external register, converting the data and the addresses through an on-chip bus protocol, and sending the converted data and addresses to an external CPU and a SpaceWire protocol processing module; and receiving data and addresses sent by the SpaceWire protocol processing module and an external CPU, and sending the data and the addresses to an external register after conversion of the on-chip bus protocol.
Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art.
Claims (7)
1. A gigabit class SpaceWire bus system comprising: the system comprises a data transceiving module, a data buffering module, a SpaceWire protocol processing module and a data access module;
a data receiving and transmitting module: receiving a serial code sent by an external optical transceiver, converting the serial code into parallel data and sending the parallel data to a data buffer module; receiving parallel data sent by the data buffer module, converting the parallel data into serial codes and sending the serial codes to an external optical transceiver;
the data buffer module: receiving parallel data sent by the data transceiver module and the SpaceWire protocol processing module, synchronously processing the parallel data sent by the data transceiver module and the SpaceWire protocol processing module, and sending the synchronized parallel data and the clock to the SpaceWire protocol processing module;
the SpaceWire protocol processing module: receiving the synchronized parallel data and the clock sent by the data buffer module, and reading the parallel data on the rising edge of the clock; receiving downlink data and a downlink data address sent by a data access module, generating parallel data, and sending the generated parallel data and a sending clock generated by the data access module to a data buffer module; extracting configuration information according to an external register address in the downlink data address to set a preset parameter, generating uplink data and an address according to the current protocol state and the preset parameter, and sending the uplink data and the address to a data access module;
a data access module: receiving data and addresses sent by an external memory, and sending the data and the addresses to an external CPU and a SpaceWire protocol processing module; receiving data and addresses sent by a SpaceWire protocol processing module and an external CPU, and sending the data and the addresses to an external memory; receiving data and addresses sent by an external register, converting the data and the addresses through an on-chip bus protocol, and sending the converted data and addresses to an external CPU and a SpaceWire protocol processing module; and receiving data and addresses sent by the SpaceWire protocol processing module and an external CPU, and sending the data and the addresses to an external register after protocol conversion.
2. The gigabit-capable SpaceWire bus system as claimed in claim 1 wherein the data transceiver module comprises: a gigabit transmitting module and a gigabit receiving module;
a gigabit transmission module: receiving parallel data sent by the data buffer module, converting the parallel data into serial codes with a gigabit rate, and outputting the serial codes to an external optical transceiver;
a gigabit receiving module: the serial code sent by an external optical transceiver is received, converted into parallel data with a gigabit rate, and then output to the data buffer module.
3. The gigabit-capable SpaceWire bus system as claimed in claim 1 wherein the SpaceWire protocol processing module comprises: the system comprises a receiving control module, a control code processing module, a sending control module, a sending clock module and an operation management module;
a receiving control module: receiving the synchronized parallel data and clock sent by the data buffer module, reading the parallel data at the rising edge of the clock, identifying a control code and a data character in the parallel data, sending the control code to the control code processing module, and sending the data character to the operation management module;
the control code processing module: receiving a control code sent by a receiving control module, extracting a control signal, and then sending the control signal to an operation management module;
the operation management module: receiving a control signal sent by a control code processing module, generating a new protocol state according to a preset parameter and a current protocol state, expanding the control signal into 128-bit uplink data, and sending the 128-bit uplink data and a target address of the uplink data generated by the control signal to a data access module; receiving data characters sent by a receiving control module, splicing the data characters into 128-bit uplink data, and sending the 128-bit uplink data and a target address of the uplink data generated by the data characters to a data access module; receiving downlink data and addresses of the downlink data sent by a data access module, extracting configuration information to set preset parameters if the addresses are external register addresses, and sending the downlink data to a sending control module as 128-bit data if the addresses are external memory addresses; sending a control signal to a sending control module; generating a sending rate selection signal according to preset parameters and sending the sending rate selection signal to a sending clock module;
a sending clock module: receiving a sending rate selection signal sent by the operation management module, generating a sending clock signal, and sending the sending clock signal to the sending control module;
a transmission control module: and receiving a transmission control signal, 128-bit data and a transmission clock signal transmitted by the transmission clock module, wherein the transmission control signal, the 128-bit data and the transmission clock signal are transmitted by the operation management module, and when the transmission control signal is at a high level, the 128-bit data is decomposed into a plurality of parallel data and is transmitted to the data buffer module together with the transmission clock signal.
4. The gigabit-capable SpaceWire bus system as claimed in claim 1 wherein said data access module comprises: an AXI bus interface module and an APB bus interface module;
AXI bus interface module: receiving data and addresses sent by a SpaceWire protocol processing module or an external CPU, and sending the data and the addresses to an external memory; receiving data and an address sent by an external memory, if the AXI bus transaction is initiated by a SpaceWire protocol processing module, sending the data and the address to the SpaceWire protocol processing module, and if the AXI bus transaction is initiated by an external CPU, sending the data and the address to the external CPU;
receiving data and addresses sent by a SpaceWire protocol processing module or an external CPU, and sending the data and the addresses to an APB bus interface module;
receiving data and an address sent by an APB bus interface module, if the AXI bus transaction is initiated by a SpaceWire protocol processing module, sending the data and the address to the SpaceWire protocol processing module, and if the AXI bus transaction is initiated by an external CPU, sending the data and the address to the external CPU;
APB bus interface module: receiving data and an address of an AXI bus interface module, converting the data and the address by an on-chip bus protocol, and sending the converted data and the converted address to an external register; and receiving data and addresses of an external register, and sending the data and the addresses to the AXI bus interface module after protocol conversion.
5. A gigabit class SpaceWire bus system as claimed in any one of claims 1 to 4 wherein: the parallel data is 16 bits.
6. The gigabit class SpaceWire bus system as recited in claim 5, wherein: the serial code is a 16B/20B serial code.
7. The gigabit class SpaceWire bus system as recited in claim 6 wherein: the external memory is a 128-bit memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810139172.5A CN108462620B (en) | 2018-02-11 | 2018-02-11 | Gilbert-level SpaceWire bus system |
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| CN109831349B (en) * | 2018-12-27 | 2021-02-09 | 中国空间技术研究院 | SpaceWire bus free topology bit error rate test system and method |
| CN110138665B (en) * | 2019-05-10 | 2021-07-09 | 北京控制工程研究所 | Gilbert-level SpaceWire router |
| CN112597085B (en) * | 2020-12-21 | 2022-09-16 | 苏州长风航空电子有限公司 | Method and system for realizing synchronous 422 communication protocol based on AXI bus |
| CN112948294B (en) * | 2021-03-19 | 2024-02-09 | 北京控制工程研究所 | Dual-channel SpaceWire controller for global parallel data receiving and transmitting and SOC (System on chip) oriented and control method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346719A (en) * | 2011-09-20 | 2012-02-08 | 北京国科环宇空间技术有限公司 | High-speed operation method and system for spacecraft |
| CN102946293A (en) * | 2012-09-26 | 2013-02-27 | 中国航天科技集团公司第九研究院第七七一研究所 | DS (data strobe) encoding based parallel reception method and device thereof |
| CN105045763A (en) * | 2015-07-14 | 2015-11-11 | 北京航空航天大学 | FPGA (Field Programmable Gata Array) and multi-core DSP (Digital Signal Processor) based PD (Pulse Doppler) radar signal processing system and parallel realization method therefor |
| CN205103813U (en) * | 2015-06-15 | 2016-03-23 | 珠海欧比特控制工程股份有限公司 | SpaceWire bus node communication module based on PCI interface |
| CN107104737A (en) * | 2017-03-01 | 2017-08-29 | 西安微电子技术研究所 | A kind of node device port extension system and method based on optical fiber interconnections |
-
2018
- 2018-02-11 CN CN201810139172.5A patent/CN108462620B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346719A (en) * | 2011-09-20 | 2012-02-08 | 北京国科环宇空间技术有限公司 | High-speed operation method and system for spacecraft |
| CN102946293A (en) * | 2012-09-26 | 2013-02-27 | 中国航天科技集团公司第九研究院第七七一研究所 | DS (data strobe) encoding based parallel reception method and device thereof |
| CN205103813U (en) * | 2015-06-15 | 2016-03-23 | 珠海欧比特控制工程股份有限公司 | SpaceWire bus node communication module based on PCI interface |
| CN105045763A (en) * | 2015-07-14 | 2015-11-11 | 北京航空航天大学 | FPGA (Field Programmable Gata Array) and multi-core DSP (Digital Signal Processor) based PD (Pulse Doppler) radar signal processing system and parallel realization method therefor |
| CN107104737A (en) * | 2017-03-01 | 2017-08-29 | 西安微电子技术研究所 | A kind of node device port extension system and method based on optical fiber interconnections |
Non-Patent Citations (6)
| Title |
|---|
| A Data Readout System with High-Speed Serial Data Link for Balloonborne X-ray Detectors;Masaharu Nomachi;《IEEE Symposium Conference Record Nuclear Science 2004》;20041022;全文 * |
| MCFLIGH"fTM - SYSTEMS·ON·CIDP FOR AEROSPACE APPLICATIONS;Tatiana Solokhina;《ELSEVIER》;20041231;全文 * |
| Serial Data Link on Advanced TCA Back Plane;M. Nomachi;《14th IEEE-NPSS Real Time Conference》;20050610;全文 * |
| SpaceFibre Port IP Core (GRSPFI);Felix Siegle;《Proceedings of the 7th International SpaceWire Conference》;20161027;第218-222页 * |
| 高速spacewire光纤总线系统研究与实现;姜宏;《2017年全国工业控制计算机年会 论文集》;20171130;全文 * |
| 高速SpaceWire路由器的设计研究;万书芹;《中国电子科学研究院学报》;20100228;全文 * |
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