CN213069802U - Non-homologous clock data transmission system - Google Patents
Non-homologous clock data transmission system Download PDFInfo
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- CN213069802U CN213069802U CN202021754212.6U CN202021754212U CN213069802U CN 213069802 U CN213069802 U CN 213069802U CN 202021754212 U CN202021754212 U CN 202021754212U CN 213069802 U CN213069802 U CN 213069802U
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Abstract
The utility model discloses a non-homologous clock data transmission system, at least including sending terminal and receiving terminal, the sending terminal is used for serial data and through optical fiber transmission to the receiving terminal, the receiving terminal includes serial data acquisition unit, passageway processing unit and output unit at least, wherein, passageway processing unit includes at least that data write in the control unit, data read-out the control unit, buffer memory unit, local clock and passageway output unit, wherein, buffer memory unit is used for opening up three frame data spaces at least with buffer memory channel data; the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference; the data writing control unit and the data reading control unit simultaneously perform data writing operation and data reading operation on the cache unit, and set a reading and writing mechanism as follows: when the address is switched, the data writing control unit controls the writing address to be switched to the cache region which is not pointed by the reading and writing address, and the data reading control unit controls the reading address to be switched to the cache region which is written last time.
Description
Technical Field
The utility model relates to a data communication technical field especially relates to a non-homologous clock data transmission system.
Background
With the increase of transmission rate of data communication systems, the demand of communication cables is higher and higher, especially for some long-distance data communication systems, optical fibers are generally used for long-distance transmission, and generally, the optical fibers only transmit data and do not transmit clock signals. And a reference clock frequency channel is added to the communication cable, which is a large cost consumption for the whole system.
In the above communication system, since the receiving end does not receive the clock signal of the transmission signal, in order to solve the technical problem, the conventional method in the prior art is to perform clock signal recovery at the receiving end, that is, to extract the clock signal according to the received serial data, and then process the serial data by using the clock to recover the digital signal at the receiving end. However, during high-speed data transmission, such as high-speed video signal transmission, the requirement for video signal synchronization is high, the requirement for the receiving end to recover the precision of the sending end clock is greatly increased, the application requirement is often difficult to achieve, and once the clock has a deviation, the video playing of the receiving end generates a non-smooth phenomenon; in addition, in the prior art, hardware is adopted to realize clock signal recovery, and the complexity of the system is greatly increased.
Therefore, in view of the defects in the prior art, a solution is needed to handle data synchronization recovery of a non-source clock data transmission system, and at the same time, to reduce the complexity and cost of the system.
SUMMERY OF THE UTILITY MODEL
In view of this, it is necessary to provide a non-homologous clock data transmission system, in which a local clock is set at a receiving end to recover a data stream, and a cache policy is optimized to reduce the influence of a deviation between clocks at the transmitting end and the receiving end, so that no additional hardware resource needs to be added, and the complexity and cost of the system are greatly reduced.
In order to solve the technical problem existing in the prior art, the technical scheme of the utility model as follows:
the non-homologous clock data transmission system at least comprises a sending end and a receiving end, wherein the sending end is used for transmitting serial data to the receiving end through an optical fiber, the receiving end at least comprises a serial data acquisition unit, a channel processing unit and an output unit, wherein,
the serial data acquisition unit is used for acquiring serial data transmitted on an optical fiber;
the channel processing unit is used for synchronizing the data of the channel;
the output unit is used for outputting the synchronized channel data;
the channel processing unit at least comprises a data writing control unit, a data reading control unit, a cache unit, a local clock and a channel output unit, wherein,
the buffer unit is used for opening up at least three frame data spaces to buffer channel data;
the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the buffer unit frame by taking a local clock as a reference.
As a further improvement, the data write control unit and the data read control unit perform the data write operation and the data read operation to the buffer unit at the same time.
As a further improvement, during address switching, the data write control unit controls the write address to switch to the cache region not pointed by the read/write address, and the data read control unit controls the read address to switch to the cache region written last time.
As a further improvement scheme, the local clock adopts a crystal oscillator with the same type and the same frequency as the sending end.
As a further improvement, the transmitting end is provided with a parallel-to-serial conversion unit, and the parallel-to-serial conversion unit is used for packaging multiple paths of parallel data into serial data.
As a further improvement, the receiving end is further provided with a data unpacking unit, and the data unpacking unit is used for unpacking and distributing the received serial data into multiple paths of parallel data to each data channel.
As a further improvement, each data channel is independently provided with a channel processing unit.
As a further improvement, the data channels share the same channel processing unit.
As a further improvement, each data channel uses the same local clock.
As a further improvement, the system further comprises a storage unit, and the cache unit of each channel opens up storage spaces in different areas of the storage unit.
As a further improvement, the memory unit adopts a DRAM.
As a further improvement, the data write control unit and the data read control unit are integrally provided in the CPU.
Compared with the prior art, the utility model discloses a local crystal oscillator realizes data recovery to through three frame buffer memory strategies, except the accumulation of error, guaranteed that read-out data is continuous. The utility model discloses a data synchronization is realized to the buffer memory, need not to increase hardware resources, greatly reduced the complexity and the cost of system.
Drawings
FIG. 1 is a schematic diagram of a non-source clock data transfer system.
Fig. 2 is a schematic diagram of the principle of the receiving end of the present invention.
Fig. 3 is a schematic diagram of the middle channel processing unit according to the present invention.
Fig. 4 is a schematic diagram of the switching of the read/write address in the present invention.
Fig. 5 is a schematic diagram of the switching of the read/write address when the read rate is faster than the write rate according to the present invention.
Fig. 6 is a schematic diagram of switching between read and write addresses with a write rate faster than a read rate according to the present invention.
The following detailed description of the invention will be made in conjunction with the above-described drawings.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1, it is shown that the utility model provides a non-homologous clock data transmission system's principle schematic diagram, including sending end and receiving terminal at least, the sending end is used for serial data and through optic fibre transmission to receiving terminal, still sets up backup optic fibre usually, when the main optical fibre trouble, effectively ensures the normal communication of system. In a preferred embodiment, high-speed video data is transmitted, such as 12G-SDI (serial Digital interface) standard data for implementing 4K high-definition video transmission, and a parallel-to-serial conversion unit is usually arranged at the transmitting end, and the parallel-to-serial conversion unit is used for packaging multiple parallel data into serial data, such as packaging 3-way parallel 3G-SDI into one-way serial 12G-SDI. In high-speed video data transmission application, continuous output of data needs to be ensured, otherwise, video jitter or stutter and other phenomena can occur, which puts higher requirements on output data synchronization. The purpose of the utility model is to solve the technical problem under the condition of not increasing hardware resources.
Referring to fig. 2, a schematic diagram of a receiving end is shown, which at least includes a serial data obtaining unit, a channel processing unit, and an output unit, where the serial data obtaining unit is configured to obtain serial data transmitted on an optical fiber; the channel processing unit is used for synchronizing the data of the channel; the output unit is used for outputting the synchronized channel data.
In a preferred embodiment, in order to realize multiple parallel data outputs, the receiving end is further provided with a data unpacking unit, and the data unpacking unit is used for unpacking and distributing the received serial data into multiple parallel data to each data channel. The data channels can share the same channel processing unit, and the data channels can share the same channel processing unit through switching of the high-speed switch; or a channel processing unit can be independently arranged in each data channel to improve the parallel output effect. Further, each data channel uses the same local clock.
Referring to fig. 3, the schematic diagram of the channel processing unit of the present invention is shown, the channel processing unit at least includes a data write-in control unit, a data read-out control unit, a buffer unit, a local clock and a channel output unit, wherein the buffer unit is configured to at least open up three frame data spaces for buffering channel data; the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference; the data writing control unit and the data reading control unit simultaneously perform data writing operation and data reading operation on the cache unit, and set a reading and writing mechanism as follows: when the address is switched, the data writing control unit controls the writing address to be switched to the cache region which is not pointed by the reading and writing address, and the data reading control unit controls the reading address to be switched to the cache region which is written last time.
In order to make the data of the sending end and the data of the receiving end as synchronous as possible, the local clock of the receiving end adopts a crystal oscillator with the same type and the same frequency as the sending end. However, the crystal oscillators always have a deviation, that is, the crystal oscillators at the transmitting end and the receiving end cannot be completely the same, even if the error between the two is less than 20ppm, if the frequency of the crystal oscillator is 148.5MHz, one synchronization needs to be performed in about 277.78 hours at the shortest time, otherwise, as the error accumulates, the video output by the receiving end has a serious time difference, which results in unstable data output.
In order to ensure stable output of data, the prior art generally adopts an enlarged buffer space, and then no matter how large the buffer space is adopted, the internal memory is full or empty due to different writing and reading rates, so that data is cut off and error accumulation is still caused.
Referring to fig. 4, a schematic diagram of the synchronization strategy according to the present invention is shown, and a three-frame buffer is taken as an example to describe the implementation process of the strategy. Firstly, a cache unit opens up three memory areas, namely a unit A, a unit B and a unit C, for caching three frame data in a single channel. The utility model is arranged for the three buffer machines, firstly, the reading operation and the writing operation of the three buffer units are carried out simultaneously, and the writing speed of the buffer is the speed of the sending end; the read speed of the buffer is determined by the local clock, which is typically infinitely close to the transmit side clock. Meanwhile, when the read-write address is switched, the data write-in control unit controls the write address to be switched to the cache region which is not pointed by the read-write address, and the data read-out control unit controls the read address to be switched to the cache region which is written at the last time. Specifically, the data write control unit controls writing of one frame data into the unit a. After completing the data writing operation of one frame, the writing address is switched to the unit B, and at this time, the data reading control unit controls the reading address to point to the unit a (the buffer area of the last writing) and performs the reading operation to read the data frame of the last writing. After the write operation of the unit B is completed, the write address is switched to the unit C (the write address is switched to the cache region which is not pointed by the read-write address). After the read operation of the unit A is finished, the read address is switched to the unit B, and the operation is repeated.
Because write in and read rate is different, must have the error, the utility model discloses just adopt the accumulation of above-mentioned mechanism elimination error, guaranteed that read data is continuous. The specific principle is as follows:
when the read rate is faster than the write rate, as shown in fig. 5, when the read operation for the cell a is completed, the write operation for the cell B is not completed yet, and at this time, the last written area is still the cell a, the read operation will read the cell a again, that is, the same frame data is read twice. Therefore, when the reading rate is faster than the writing rate, the asynchronous problem caused by clock rate deviation is eliminated by repeatedly outputting one frame of data. When the write rate is higher than the read rate, errors are accumulated continuously due to speed difference, the situation of fig. 6 always occurs at a certain moment, when the read operation on the unit a is not completed, the write operation continuously writes the units B and C, at this time, the read address points to the unit a, the write address points to the unit C, and since the read address is not switched after a delay, although the data of the unit B is not read, the write address is always switched to an area which is not pointed by the read/write address, and the write address is switched to the unit B to overwrite the data of the unit. That is, when the write rate is faster than the read rate, the accumulation of errors is eliminated by overwriting one frame data, and the input and output are resynchronized.
In a preferred embodiment, the data caching system further comprises a storage unit, the storage unit adopts a DRAM, and the cache unit of each channel realizes data caching by adopting a direct memory access technology for opening up storage spaces in different areas of the storage unit.
In a preferred embodiment, the data write control unit and the data read control unit are integrally provided in the CPU.
The above description of the embodiments is only intended to help understand the method of the present invention and its core ideas. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. The non-homologous clock data transmission system is characterized by at least comprising a sending end and a receiving end, wherein the sending end is used for transmitting serial data to the receiving end through an optical fiber, the receiving end at least comprises a serial data acquisition unit, a channel processing unit and an output unit, wherein,
the serial data acquisition unit is used for acquiring serial data transmitted on an optical fiber;
the channel processing unit is used for synchronizing the data of the channel;
the output unit is used for outputting the synchronized channel data;
the channel processing unit at least comprises a data writing control unit, a data reading control unit, a cache unit, a local clock and a channel output unit, wherein,
the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference;
the buffer unit is used for opening up at least three frame data spaces to buffer the channel data.
2. The non-source clock data transfer system of claim 1, wherein the data write control unit and the data read control unit perform the data write operation and the data read operation on the buffer unit simultaneously.
3. The non-source clock data transmission system according to claim 2, wherein, during address switching, the data write control unit controls the write address to switch to the cache region not pointed to by the read/write address, and the data read control unit controls the read address to switch to the cache region written last time.
4. The system according to claim 3, wherein the local clock employs a crystal oscillator with the same type and frequency as the sending end.
5. The non-homologous clock data transmission system according to claim 3, wherein the transmitting end is provided with a parallel-to-serial conversion unit, and the parallel-to-serial conversion unit is configured to encapsulate multiple paths of parallel data into serial data; the receiving end is also provided with a data unpacking unit which is used for unpacking and distributing the received serial data into a plurality of paths of parallel data to each data channel.
6. The non-source clock data transfer system of claim 5 wherein each data lane has a lane processing unit independently disposed.
7. The non-source clock data transfer system of claim 5 wherein the data lanes share the same lane processing unit.
8. The non-source clock data transfer system of claim 6 wherein each data lane uses the same local clock.
9. The non-homologous clock data transmission system according to claim 6, further comprising a storage unit, wherein the buffer unit of each channel opens up storage spaces in different areas of the storage unit; the storage unit adopts a DRAM.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112052204A (en) * | 2020-08-20 | 2020-12-08 | 浙江树人学院（浙江树人大学） | Non-homologous clock data transmission system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112052204A (en) * | 2020-08-20 | 2020-12-08 | 浙江树人学院（浙江树人大学） | Non-homologous clock data transmission system |
| CN112052204B (en) * | 2020-08-20 | 2022-08-12 | 浙江树人学院（浙江树人大学） | Non-homologous clock data transmission system |
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Address after: 2016 Jiangxia Road, Yangxunqiao Town, Keqiao District, Hangzhou City, Zhejiang Province Patentee after: ZHEJIANG SHUREN College (ZHEJIANG SHUREN University) Address before: 310015 No. 8 Shuren street, Hangzhou, Zhejiang, Gongshu District Patentee before: ZHEJIANG SHUREN College (ZHEJIANG SHUREN University) |
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