CN112052204A - Non-homologous clock data transmission system - Google Patents
Non-homologous clock data transmission system Download PDFInfo
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 19
- 238000012545 processing Methods 0.000 claims abstract description 20
- 239000013307 optical fiber Substances 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims description 7
- 238000012546 transfer Methods 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 11
- 238000011084 recovery Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 208000003028 Stuttering Diseases 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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Abstract
The invention discloses a non-homologous clock data transmission system, which at least comprises a sending end and a receiving end, wherein the sending end is used for transmitting serial data to the receiving end through an optical fiber, and the receiving end at least comprises a serial data acquisition unit, a channel processing unit and an output unit, wherein the channel processing unit at least comprises a data writing control unit, a data reading control unit, a cache unit, a local clock and a channel output unit, and the cache unit is used for at least opening up three frame data spaces to cache channel data; the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference; the data writing control unit and the data reading control unit simultaneously perform data writing operation and data reading operation on the cache unit, and set a reading and writing mechanism as follows: when the address is switched, the data writing control unit controls the writing address to be switched to the cache region which is not pointed by the reading and writing address, and the data reading control unit controls the reading address to be switched to the cache region which is written last time.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a non-homologous clock data transmission system.
Background
With the increase of transmission rate of data communication systems, the demand of communication cables is higher and higher, especially for some long-distance data communication systems, optical fibers are generally used for long-distance transmission, and generally, the optical fibers only transmit data and do not transmit clock signals. And a reference clock frequency channel is added to the communication cable, which is a large cost consumption for the whole system.
In the above communication system, since the receiving end does not receive the clock signal of the transmission signal, in order to solve the technical problem, the conventional method in the prior art is to perform clock signal recovery at the receiving end, that is, to extract the clock signal according to the received serial data, and then process the serial data by using the clock to recover the digital signal at the receiving end. However, during high-speed data transmission, such as high-speed video signal transmission, the requirement for video signal synchronization is high, the requirement for the receiving end to recover the precision of the sending end clock is greatly increased, the application requirement is often difficult to achieve, and once the clock has a deviation, the video playing of the receiving end generates a non-smooth phenomenon; in addition, in the prior art, hardware is adopted to realize clock signal recovery, and the complexity of the system is greatly increased.
Therefore, in view of the defects in the prior art, a solution is needed to handle data synchronization recovery of a non-source clock data transmission system, and at the same time, to reduce the complexity and cost of the system.
Disclosure of Invention
In view of this, it is necessary to provide a non-homologous clock data transmission system, in which a local clock is set at a receiving end to recover a data stream, and a cache policy is optimized to reduce the influence of a deviation between clocks at the transmitting end and the receiving end, so that no additional hardware resource needs to be added, and the complexity and cost of the system are greatly reduced.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
the non-homologous clock data transmission system at least comprises a sending end and a receiving end, wherein the sending end is used for transmitting serial data to the receiving end through an optical fiber, the receiving end at least comprises a serial data acquisition unit, a channel processing unit and an output unit, wherein,
the serial data acquisition unit is used for acquiring serial data transmitted on an optical fiber;
the channel processing unit is used for synchronizing the data of the channel;
the output unit is used for outputting the synchronized channel data;
the channel processing unit at least comprises a data writing control unit, a data reading control unit, a cache unit, a local clock and a channel output unit, wherein,
the buffer unit is used for opening up at least three frame data spaces to buffer channel data;
the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference; the data writing control unit and the data reading control unit simultaneously perform data writing operation and data reading operation on the cache unit, and set a reading and writing mechanism as follows: when the address is switched, the data writing control unit controls the writing address to be switched to the cache region which is not pointed by the reading and writing address, and the data reading control unit controls the reading address to be switched to the cache region which is written last time.
As a further improvement scheme, the local clock adopts a crystal oscillator with the same type and the same frequency as the sending end.
As a further improvement, the transmitting end is provided with a parallel-to-serial conversion unit, and the parallel-to-serial conversion unit is used for packaging multiple paths of parallel data into serial data.
As a further improvement, the receiving end is further provided with a data unpacking unit, and the data unpacking unit is used for unpacking and distributing the received serial data into multiple paths of parallel data to each data channel.
As a further improvement, each data channel is independently provided with a channel processing unit.
As a further improvement, the data channels share the same channel processing unit.
As a further improvement, each data channel uses the same local clock.
As a further improvement, the system further comprises a storage unit, and the cache unit of each channel opens up storage spaces in different areas of the storage unit.
As a further improvement, the memory unit adopts a DRAM.
As a further improvement, the data write control unit and the data read control unit are integrally provided in the CPU.
Compared with the prior art, the data recovery method and the data recovery device adopt the local crystal oscillator to realize data recovery, and ensure the continuity of read data by optimizing a cache strategy, except the accumulation of errors. The invention can realize data synchronization by adopting software without increasing hardware resources, thereby greatly reducing the complexity and the cost of the system.
Drawings
FIG. 1 is a schematic diagram of a non-source clock data transfer system.
Fig. 2 is a schematic diagram of a receiving end according to the present invention.
FIG. 3 is a schematic diagram of a channel processing unit according to the present invention.
FIG. 4 is a diagram illustrating read/write address switching according to the present invention.
FIG. 5 is a diagram illustrating the switching of read and write addresses when the read rate is faster than the write rate.
FIG. 6 is a diagram illustrating switching of read/write addresses with a write rate faster than a read rate according to the present invention.
FIG. 7 is a block diagram illustrating a process of data recovery at a receiving end in a non-homologous clock data transmission system according to the present invention.
The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1, a schematic diagram of a non-homologous clock data transmission system provided by the present invention is shown, which at least includes a transmitting end and a receiving end, where the transmitting end is used to transmit serial data to the receiving end through an optical fiber, and a backup optical fiber is usually provided, so that when a main optical fiber fails, normal communication of the system is effectively ensured. In a preferred embodiment, high-speed video data is transmitted, such as 12G-SDI (serial Digital interface) standard data for implementing 4K high-definition video transmission, and a parallel-to-serial conversion unit is usually arranged at the transmitting end, and the parallel-to-serial conversion unit is used for packaging multiple parallel data into serial data, such as packaging 3-way parallel 3G-SDI into one-way serial 12G-SDI. In high-speed video data transmission application, continuous output of data needs to be ensured, otherwise, video jitter or stutter and other phenomena can occur, which puts higher requirements on output data synchronization. The object of the present invention is to solve the above technical problem without increasing hardware resources.
Referring to fig. 2, a schematic diagram of a receiving end is shown, which at least includes a serial data obtaining unit, a channel processing unit, and an output unit, where the serial data obtaining unit is configured to obtain serial data transmitted on an optical fiber; the channel processing unit is used for synchronizing the data of the channel; the output unit is used for outputting the synchronized channel data.
In a preferred embodiment, in order to realize multiple parallel data outputs, the receiving end is further provided with a data unpacking unit, and the data unpacking unit is used for unpacking and distributing the received serial data into multiple parallel data to each data channel. The data channels can share the same channel processing unit, and the data channels can share the same channel processing unit through switching of the high-speed switch; or a channel processing unit can be independently arranged in each data channel to improve the parallel output effect. Further, each data channel uses the same local clock.
Referring to fig. 3, which is a schematic diagram illustrating a principle of a channel processing unit according to the present invention, the channel processing unit at least includes a data write-in control unit, a data read-out control unit, a buffer unit, a local clock, and a channel output unit, wherein the buffer unit is configured to open up at least three frame data spaces to buffer channel data; the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference; the data writing control unit and the data reading control unit simultaneously perform data writing operation and data reading operation on the cache unit, and set a reading and writing mechanism as follows: when the address is switched, the data writing control unit controls the writing address to be switched to the cache region which is not pointed by the reading and writing address, and the data reading control unit controls the reading address to be switched to the cache region which is written last time.
In order to make the data of the sending end and the data of the receiving end as synchronous as possible, the local clock of the receiving end adopts a crystal oscillator with the same type and the same frequency as the sending end. However, the crystal oscillators always have a deviation, that is, the crystal oscillators at the transmitting end and the receiving end cannot be completely the same, even if the error between the two is less than 20ppm, if the frequency of the crystal oscillator is 148.5MHz, one synchronization needs to be performed in about 277.78 hours at the shortest time, otherwise, as the error accumulates, the video output by the receiving end has a serious time difference, which results in unstable data output.
In order to ensure stable output of data, the prior art generally adopts an enlarged buffer space, and then no matter how large the buffer space is adopted, the internal memory is full or empty due to different writing and reading rates, so that data is cut off and error accumulation is still caused.
Referring to fig. 4, a schematic diagram of the synchronization strategy of the present invention is shown, and the implementation process of the strategy is described by taking three-frame buffering as an example. Firstly, a cache unit opens up three memory areas, namely a unit A, a unit B and a unit C, for caching three frame data in a single channel. Firstly, reading operation and writing operation of three buffer units are carried out simultaneously, and the writing speed of the buffer is the speed of a sending end; the read speed of the buffer is determined by the local clock, which is typically infinitely close to the transmit side clock. Meanwhile, when the read-write address is switched, the data write-in control unit controls the write address to be switched to the cache region which is not pointed by the read-write address, and the data read-out control unit controls the read address to be switched to the cache region which is written at the last time. Specifically, the data write control unit controls writing of one frame data into the unit a. After completing the data writing operation of one frame, the writing address is switched to the unit B, and at this time, the data reading control unit controls the reading address to point to the unit a (the buffer area of the last writing) and performs the reading operation to read the data frame of the last writing. After the write operation of the unit B is completed, the write address is switched to the unit C (the write address is switched to the cache region which is not pointed by the read-write address). After the read operation of the unit A is finished, the read address is switched to the unit B, and the operation is repeated.
Because the writing speed and the reading speed are different, errors inevitably exist, and the invention adopts the mechanism to eliminate the accumulation of the errors and ensure the continuity of the read data. The specific principle is as follows:
when the read rate is faster than the write rate, as shown in fig. 5, when the read operation for the cell a is completed, the write operation for the cell B is not completed yet, and at this time, the last written area is still the cell a, the read operation will read the cell a again, that is, the same frame data is read twice. Therefore, when the reading rate is faster than the writing rate, the asynchronous problem caused by clock rate deviation is eliminated by repeatedly outputting one frame of data. When the write rate is higher than the read rate, errors are accumulated continuously due to speed difference, the situation of fig. 6 always occurs at a certain moment, when the read operation on the unit a is not completed, the write operation continuously writes the units B and C, at this time, the read address points to the unit a, the write address points to the unit C, and since the read address is not switched after a delay, although the data of the unit B is not read, the write address is always switched to an area which is not pointed by the read/write address, and the write address is switched to the unit B to overwrite the data of the unit. That is, when the write rate is faster than the read rate, the accumulation of errors is eliminated by overwriting one frame data, and the input and output are resynchronized.
In a preferred embodiment, the data caching system further comprises a storage unit, the storage unit adopts a DRAM, and the cache unit of each channel realizes data caching by adopting a direct memory access technology for opening up storage spaces in different areas of the storage unit.
In a preferred embodiment, the data write control unit and the data read control unit are integrally provided in the CPU.
Referring to fig. 7, the present invention also discloses a data recovery method for a non-homologous clock data transmission system, where a sending end packages multiple paths of parallel data into serial data and transmits the serial data to a receiving end through an optical fiber, and the receiving end performs at least the following steps:
step S1: acquiring serial data;
step S2: unpacking and distributing the serial data into multi-path parallel data;
step S3: in each parallel channel, writing data into a cache frame by frame;
step S4: reading the cache data frame by taking a local clock as a reference;
step S5: outputting all channel data in parallel;
wherein, the buffer memory of each channel at least opens up three frame buffer memory spaces, and sets up the following read-write mechanism: when the address is switched, the writing address is always switched to the area which is not pointed by the reading and writing address, and the reading address is always switched to the last writing area.
By adopting the technical scheme, the invention eliminates the accumulation of errors by optimizing the storage strategy and utilizing a read-write mechanism, and effectively ensures the continuity of read data by repeatedly outputting or covering one frame of data when the input and the output are asynchronous. The specific working principle is shown in fig. 4-6 and the related description above, and will not be described herein again.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The non-homologous clock data transmission system is characterized by at least comprising a sending end and a receiving end, wherein the sending end is used for transmitting serial data to the receiving end through an optical fiber, the receiving end at least comprises a serial data acquisition unit, a channel processing unit and an output unit, wherein,
the serial data acquisition unit is used for acquiring serial data transmitted on an optical fiber;
the channel processing unit is used for synchronizing the data of the channel;
the output unit is used for outputting the synchronized channel data;
the channel processing unit at least comprises a data writing control unit, a data reading control unit, a cache unit, a local clock and a channel output unit, wherein,
the buffer unit is used for opening up at least three frame data spaces to buffer channel data;
the data write-in control unit is used for writing the channel data into the cache frame by frame; the data reading control unit is used for reading data from the cache unit frame by taking a local clock as a reference; the data writing control unit and the data reading control unit simultaneously perform data writing operation and data reading operation on the cache unit, and set a reading and writing mechanism as follows: when the address is switched, the data writing control unit controls the writing address to be switched to the cache region which is not pointed by the reading and writing address, and the data reading control unit controls the reading address to be switched to the cache region which is written last time.
2. The system according to claim 1, wherein the local clock employs a crystal oscillator with the same type and frequency as the sending end.
3. The non-homologous clock data transmission system according to claim 1 or 2, wherein the transmitting end is provided with a parallel-to-serial conversion unit, and the parallel-to-serial conversion unit is configured to encapsulate multiple paths of parallel data into serial data.
4. The non-source clock data transmission system of claim 3, wherein the receiving end is further provided with a data unpacking unit, and the data unpacking unit is configured to unpack and distribute the received serial data into multiple parallel data channels for each data channel.
5. The non-source clock data transfer system of claim 4 wherein each data lane has a lane processing unit independently disposed.
6. The non-source clock data transfer system of claim 4 wherein the data lanes share the same lane processing unit.
7. The non-source clock data transfer system of claim 5 wherein each data lane uses the same local clock.
8. The non-source clock data transfer system of claim 5, further comprising a storage unit, wherein the buffer unit of each channel is configured to open up storage space in different areas of the storage unit.
9. The non-source clock data transfer system of claim 8, wherein the memory unit is a DRAM.
10. The non-source clock data transfer system of claim 3, wherein the data write control unit and the data read control unit are integrally provided in the CPU.
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| CN202210814401.5A CN115203091A (en) | 2020-08-20 | 2020-08-20 | Data recovery method of non-homologous clock data transmission system |
| CN202010845938.9A CN112052204B (en) | 2020-08-20 | 2020-08-20 | Non-homologous clock data transmission system |
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| CN202010845938.9A CN112052204B (en) | 2020-08-20 | 2020-08-20 | Non-homologous clock data transmission system |
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| CN115203091A (en) | 2022-10-18 |
| CN112052204B (en) | 2022-08-12 |
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