CN101236528A - Ping-pong control method and apparatus - Google Patents
Ping-pong control method and apparatus Download PDFInfo
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- CN101236528A CN101236528A CNA2008100263891A CN200810026389A CN101236528A CN 101236528 A CN101236528 A CN 101236528A CN A2008100263891 A CNA2008100263891 A CN A2008100263891A CN 200810026389 A CN200810026389 A CN 200810026389A CN 101236528 A CN101236528 A CN 101236528A
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Abstract
The embodiment of the invention discloses a method for ping-pong control, comprising the following steps that: data writing is performed on at least three cache units in turn under the control of a write control signal which is emitted by a data transmit leg, and data writing on the cache units are performed under the state of non-read data of the cache units; data reading is performed on the at least three cache units in turn according to cycle under the control of a timing count signal. The embodiment of the invention also provides a device for ping-pong control. By adoption of the embodiment of the invention, a plurality of cache units are used for realizing alternating read-write operation in a data cache area, and time window of data writing can be prolonged.
Description
Technical field
The present invention relates to the metadata cache technology, relate in particular to a kind of method and device of the control of rattling.
Background technology
Ping-pong buffer (Ping Pong Buffer) mechanism is a kind of relatively cache way of increase data bandwidth commonly used.Can be used in any one needs in the system that read operation and write operation carry out simultaneously, also is method commonly used in special IC (ASIC, the Application Specific Integrated Circuit) design, is used for data stream is carried out control and treatment.
Referring to Fig. 1, be the composition synoptic diagram of the table tennis control that provides of prior art.
The treatment scheme of table tennis control is: input traffic is assigned to two data buffer zones by " input traffic selected cell " during with data stream etc., at first buffer circle, the data flow cache of input is arrived " data buffering module 0 "; At second buffer circle, switching by " input traffic selected cell ", the data flow cache of input is arrived " data buffering module 1 ", simultaneously first cycle data of " data buffering module 0 " buffer memory is passed through the selection of " output stream selected cell ", deliver to " dataflow computing processing module " and carry out calculation process; At the 3rd buffer circle, switching once more by " input traffic selected cell ", the data flow cache of input is arrived " data buffering module 0 ", simultaneously the data of the second period of " data buffering module 1 " buffer memory are switched by " output stream selected cell ", delivered to " dataflow computing processing module " and carry out calculation process.So circulation.
The table tennis control that prior art provides, relatively Chang Yong method is to use two twoport random cache devices (RAM, Random Access Memory) as data buffer area, and two ports of every block RAM are defined as respectively to be read port and writes inbound port.And the periodic energizing signal makes at a time that as the table tennis control signal inbound port of writing of one of them dual port RAM is opened, and reads port shutdown; Simultaneously, the port of reading of another dual port RAM is opened, and writes port shutdown, and so no matter when reading and writing can not operated same block RAM simultaneously, avoided read/write conflict, and two block RAMs use same set of address for read/write circuit.
The inventor finds that above-mentioned existing table tennis control has following shortcoming in implementing process of the present invention:
Table tennis control signal of the prior art is a regularly energizing signal of one-period, externally equipment is when data buffer area writes data, if external unit can not accurately be known the timing of table tennis control signal, the table tennis control signal is overturn in the write data process so, data can write two buffers, cause the data write error mistake; And write data has identical time window with read data, is not suitable for the slow situation of the speed of write data than read data.
Summary of the invention
The embodiment of the invention provides a kind of method and device of the control of rattling, and uses a plurality of data buffer storage units to realize read-write operation alternately, can prolong the time window of write data.
Be the above-mentioned technical matters that solves, the embodiment of the invention provides a kind of method that realizes ping-pong operation, and described method comprises:
Under the control of the write control signal that data receiver is sent, successively at least three buffer units are carried out write data, and be under the non-read data state of described buffer unit, to carry out the write data of buffer unit; Under the control of timer counter signal, successively described at least three buffer units are carried out read data by the cycle.Correspondingly, the embodiment of the invention also provides a kind of device of the control of rattling, and described device comprises:
Cache module comprises at least three buffer units;
The write data control module is used under the control of the write control signal that data receiver is sent, and successively described at least three buffer units is carried out write data, and is to carry out under the non-read data state of described buffer unit to the write data of buffer unit;
The read data control module is used to produce the timer counter signal, and under the control of described timer counter signal, successively described at least three buffer units is carried out read data by the cycle.
Method and device that the table tennis that implementing the embodiment of the invention provides is controlled have following beneficial effect:
Carry out write operation by data receiver control buffer unit and switch, can avoid that buffer unit switches in writing the process of same frame data, cause the problem of data write error mistake; And in data buffer area, use a plurality of buffer units to realize read-write operation alternately, can prolong the time window of write data.
Description of drawings
Fig. 1 is the composition synoptic diagram of the table tennis control that provides of prior art;
Fig. 2 is the composition synoptic diagram of the device of the table tennis control that provides of the embodiment of the invention;
Fig. 3 is the composition synoptic diagram of write data control module in installing as shown in Figure 2;
Fig. 4 is the composition synoptic diagram of read data control module in installing as shown in Figure 2;
Fig. 5 is the schematic flow sheet of write data of the method for the table tennis control that provides of the embodiment of the invention;
Fig. 6 is the schematic flow sheet of read data of the method for the table tennis control that provides of the embodiment of the invention;
Fig. 7 is the electrical block diagram of the device of the table tennis control that provides of the embodiment of the invention;
Fig. 8 is the structural representation of write control circuit of the device of the table tennis control that provides of the embodiment of the invention;
Fig. 9 is the synoptic diagram of access time window of the device of table tennis control as shown in Figure 7.
Embodiment
Referring to Fig. 2, be the composition synoptic diagram of the device of the table tennis control that provides of the embodiment of the invention;
The device of described table tennis control mainly comprises:
Write data control module 1 is used for circularly each buffer unit being carried out write data successively under the control of write control signal, and the write data of a certain buffer unit is carried out under the non-read data state of described buffer unit; Described write control signal is sent by data receiver, shows that described data receiver will issue new frame data;
Read data control module 3 is used to produce the timer counter signal, and under the control of described timer counter signal, successively each buffer unit is carried out read data by the cycle;
Because read data is under the control of timer counter signal, periodically in turn from each buffer unit sense data, so by increasing the number of buffer unit, can prolong each buffer unit and be in time window under the non-read data state, promptly prolong the time window of write data.Adopt at least three buffer units, can make the read data time window of write data time window, can solve the problem of writing rate less than read rate more than or equal to twice.
Referring to Fig. 3, be the composition synoptic diagram of write data control module in installing as shown in Figure 2;
Write data control module 1 comprises:
Write buffer memory selected cell 12, be used for selecting the value of signal to select the corresponding cache unit to carry out write operation according to writing buffer memory; For example, when the value of writing buffer memory selection signal is 0, select buffer unit 0 to carry out data writing operation; When the value of writing buffer memory selection signal is 1, select buffer unit 1 to carry out data writing operation; The rest may be inferred.
Referring to Fig. 4, be the composition synoptic diagram of read data control module 3 in installing as shown in Figure 2;
Described read data control module comprises:
Timer counter unit 31 is used to produce the timer counter signal, and described timer counter signal carries out timer counter by the cycle, the frame number of the data that indication need be read; When reaching timing, described timer counter signal points to next frame number.
Read buffer memory selected cell 32, be used for when timer counter signal generation saltus step, select frame number to read with the data that the timer counter signal conforms to; The frame number of described data is when buffer unit is carried out write operation, writes buffer unit together in company with data, is used to indicate the order of reading of described data.
Referring to Fig. 5, be the schematic flow sheet of write data of the method for the table tennis control that provides of the embodiment of the invention;
At step S100, whether receive the write control signal of data receiver, if not, execution in step S101, if, execution in step S102 then; Described write control signal is sent by data receiver, shows that described data receiver will issue new frame data;
At step S101, do not receive write control signal, to write buffer memory and select the currency of signal to remain unchanged, write operation does not switch;
At step S102, receive write control signal, promptly data receiver will write new frame data to data buffer area, then select the currency of signal to carry out add-one operation to writing buffer memory, and write operation switches to next buffer unit; When writing buffer memory and select signal to be added to n-1, carry out add-one operation once more and then return 0, wherein n is the number of buffer unit; For example, when using three buffer units, receive write control signal after, when selecting the currency of signal to carry out add-one operation to writing buffer memory, from 0 to 2, after calculating 2, if when receiving write control signal once more, write buffer memory and select the value of signal to return 0, circulation successively.
At step S103, select the value of signal to select corresponding buffer unit to carry out write operation according to writing buffer memory;
For example, be 0 when writing buffer memory selection signal, write operation switches to buffer unit 0; When writing buffer memory selection signal is 1, and write operation switches to buffer unit 1; When writing buffer memory selection signal is n-1, and write operation switches to buffer unit n-1; The rest may be inferred.
Referring to Fig. 6, be the schematic flow sheet of read data of the method for the table tennis control that provides of the embodiment of the invention; At step S200, each buffer unit has the identical address of a cover, and all to set in advance be data output enable state, and when receiving when reading address information, all buffer units are all exported the data in the appropriate address;
At step S201, the timer counter signal carries out timer counter by the cycle, the frame number of the data that indication need be read; When arriving timing, then described timer counter signal jumps to next frame number;
At step S202, when timer counter signal generation saltus step, inquire about the frame number of the data of all buffer unit outputs; The frame number of described data is when buffer unit is carried out write operation, writes buffer unit together in company with data, is used to indicate the order of reading of described data;
At step S203, select frame number to read with the data that described timer counter signal conforms to.
Referring to Fig. 7, be the electrical block diagram of the device of the table tennis control that provides of the embodiment of the invention;
Be that example describes with data signal processor (DSP, Digital Signal Processing) as data receiver below.Various signals among Fig. 7 are described below:
Rpipa_ctrl selects signal for reading buffer memory;
Radr is for reading the address;
Dsp_addr is the DSP write address;
Dsp_data is the DSP write data;
Dsp_wren is that DSP is with imitating signal;
Dsp_ce selects useful signal for the DSP sheet;
Wpipa_ctrl selects signal for writing buffer memory;
Use three dual port RAMs in the device of as shown in Figure 7 table tennis control, be respectively RAM0, RAM1, RAM2, be used for data cachedly, realized read-write operation alternately; The A mouth is defined as and reads port in each buffer, and the B mouth is defined as writes inbound port.The control signal of write data and read data is produced by two different Controlling Source respectively, wherein, write buffer memory select signal wpipa_ctrl be control under, produce by write control circuit; Reading buffer memory selects signal rpipa_ctrl to produce by reading control circuit.
Data transmission unit DSP will be in the time will issuing new frame data, control and write buffer memory and select signal wpipa_ctrl to carry out add-one operation by sending write control signal, and with chip selection signal dsp_ce with obtain specific buffer write the permission signal, particularly, under the effective situation of chip selection signal dsp_ce, wpipa_ctrl is 00 o'clock, has only the inbound port of writing of RAM0 to open, other RAM writes port shutdown, and write operation switches to buffer RAM0; Wpipa_ctrl is 01 o'clock, and is same, has only the inbound port of writing of RAM1 to open, and write operation switches to buffer RAM1; Wpipa_ctrl is 10 o'clock, and is same, has only the inbound port of writing of RAM2 to open, and write operation switches to buffer RAM2; When the buffer write operation was effective, this buffer received write data information and the write address information that DSP issues, and writes data in corresponding address.
The principle of buffer being carried out read data is: the port of reading of each RAM all is in data output enable state, when reading the address information input, three block RAMs all can be exported the data in the appropriate address, select signal rpipa_ctrl to select the correct data of frame number to read by reading buffer memory again.The frame number of described data is when RAM is carried out write operation, writes together in company with data, and is stored among the RAM, is used to indicate these data when to be read out.
Reading buffer memory selects signal rpipa_ctrl to produce by reading control circuit.Read control circuit inside and include a timer conter, the timer counter signal carries out timer counter by the cycle, the frame number of the data that indication need be read; When timing arrives, then described timer counter signal jumps to next frame number, the frame number of three data that RAM exported of inquiry, and generate and read the data that buffer memory selects signal rpipa_ctrl to select frame number to conform to and read.
The device of the table tennis control that the embodiment of the invention provides, described data buffer area also can use the buffer unit more than three to constitute, described buffer unit also is not limited to dual port RAM, also can use single port RAM, FIFO storeies such as (First Input First Output).
Referring to Fig. 8, be the structural representation of write control circuit of the device of the table tennis control that provides of the embodiment of the invention; Various signals are described below among the figure:
Dsp_addr is the DSP write address;
Dsp_wdata is the DSP write data;
Dsp_wren is that DSP is with imitating signal;
Dsp_ce selects useful signal for the DSP sheet;
Pipa_ctrl selects signal for writing buffer memory;
DSP is used for sending data and write control signal to buffer area as data receiver; As shown in the figure, reserve an address, when DSP writes particular value toward this address, illustrate that DSP will issue new frame data to DSP.As shown in FIG., the write control signal that described DSP sends be dsp_addr, dsp_wdata, dsp_wren signal and dsp_ce signal with after the enable signal that draws, when this enable signal is effective, show that DSP will write new frame data to buffer area, then select the currency of signal pipa_ctrl to carry out add-one operation write operation; If described enable signal is invalid, then keep the currency of pipa_ctrl constant.
The write control circuit inside that the embodiment of the invention provides is provided with counter, is used for the pipa_ctrl signal is carried out computing; For corresponding, use 2bit (2) counter to illustrate below with three buffers in as shown in Figure 7 the device.
Described counter selects the currency of signal pipa_ctrl to carry out add-one operation to writing buffer memory, from 0 to 2, after the value of pipa_ctrl signal calculates 2, if receive the write control signal of DSP once more, then the value of pipa_ctrl signal returns 0, and promptly the pipa_ctrl signal is by 00 to 01, again to 10, return 00, successively circulation.
Need to prove, be that example describes with the counter of 2bit only here, if when the device of table tennis control uses n buffer, then the minimum number of bits m of counter is as follows:
Work as log
2 nDuring for integer, m is log
2 n
Work as log
2 nDuring for non-integer, m is log
2 nAdd 1 again after the round numbers.
Referring to Fig. 9, be the synoptic diagram of access time window of the device of table tennis control as shown in Figure 7.
The write data and the read data of the device of the table tennis control that the embodiment of the invention provides are described below in conjunction with Fig. 9
Time window, and the beneficial effect that brings in actual applications.
As shown in Figure 9, use three block RAMs to be illustrated, when RAM is operated, control at any one time, write data all is among the different RAM with read data.Read data is an operation at the uniform velocity, and the timer counter signal switches with cycle t, and t arrives whenever timing, just point to next RAM, successively RAM is carried out read data, the data in every block RAM can run through at time t, after running through a block RAM, read operation switches to another block RAM.Simultaneously, also circularly each RAM is carried out write data successively, and control is carried out under the non-read data state of described buffer unit to the write data of a certain buffer unit.The time window of write data and read data is specific as follows:
In first cycle, RAM1 is carried out read data;
At second period, RAM2 is carried out read data; Simultaneously, in first and second cycles, write data data0, and before the period 3 arrives, write data data0 to RAM0;
In the period 3, RAM0 is carried out read data, sense data data0; Simultaneously, in first and second cycles, after data data0 had write, when data receiver issued new frame data again, write data switched to RAM1, writes data data1 to RAM1, and had write data data1 before the period 4 arrives;
The 4th cycle, RAM1 is carried out read data, sense data data1;
And the like carry out read-write operation.
This shows that the write data of a certain buffer unit is controlled under the non-read data state of this buffer unit and carries out, promptly the number of buffer unit is many more, for single buffer unit, the time that is in non-read data state is just long more.So the device of the table tennis that the embodiment of the invention provides control uses a plurality of buffer units, can prolong the time window of write data.
The time window T of write data
wComputing formula as follows:
T
w＝(N-1)×t；
Wherein N (N 〉=3) is the number of buffer unit, and t is the cycle (also being the cycle of read data) of timer counter signal.Adopt the embodiment of the invention, can make the read data time window of write data time window, can solve the problem of writing rate less than read rate more than or equal to twice.
The device of the table tennis control that the embodiment of the invention provided can be applicable to high speed downlink packet and inserts in (HSDPA, High Speed Downlink Packages Access) Channel Modulation and the addressable port circuit.
The data that the HSDPA channel sends are 2ms frames, and the data that at every turn send to modulation circuit can use up behind 2ms, and institute thinks assurance modulation circuit operate as normal continuously, and HSDPA need send continuous Frame.Generally speaking, coded data is issued by outside DSP, sends modulation circuit to by the HSDPA channel again.It is very high that HSDPA uses the 2ms frame to require for the timing of DSP, because many times DSP also will handle the data of other channel, load is very big, and DSP is difficult to guarantee in each 2ms data distributing is finished.For the normal execution that guarantees to read and write just needs to use the table tennis control structure.The device of the table tennis control that the embodiment of the invention provided is applied in HSDPA Channel Modulation and the addressable port circuit, the timer counter signal is set to switch by the 2ms cycle, and adopt the structure of three buffer units, can realize that the time window that DSP issues data extends to 4ms, and write operation is controlled by DSP, avoided DSP when writing same frame data, buffer unit switches and causes the problem of data write error mistake.
Above-mentioned is that example describes with HSDPA Channel Modulation and addressable port circuit only, and the present invention can be applied to needing in the system that read data and write data carry out simultaneously of other equally.
The method and the device of the control of table tennis that the embodiment of the invention provided carry out write operation by data receiver control buffer unit and switch, and can avoid that buffer unit switches in writing the process of same frame data, cause the problem of data write error mistake; And in data buffer area, use a plurality of buffer units to realize read-write operation alternately, can prolong the time window of write data.
Above disclosed is a kind of preferred embodiment of the present invention only, can not limit the present invention's interest field certainly with this, and therefore the equivalent variations of doing according to claim of the present invention still belongs to the scope that the present invention is contained.
Claims (10)
1, a kind of method of the control of rattling is characterized in that, comprising:
Under the control of the write control signal that data receiver is sent, successively at least three buffer units are carried out write data, and be under the non-read data state of described buffer unit, to carry out the write data of buffer unit; Under the control of timer counter signal, successively described at least three buffer units are carried out read data by the cycle.
2, the method for table tennis as claimed in claim 1 control is characterized in that, described method of successively at least three buffer units being carried out write data under the control of the write control signal that data receiver is sent comprises:
After receiving the write control signal that data receiver sends, select the currency of signal to carry out add-one operation to writing buffer memory;
Select the value of signal to select the corresponding cache unit according to writing buffer memory, and write data to described buffer unit.
3, the method for table tennis as claimed in claim 2 control is characterized in that, when described when writing buffer memory and selecting the value of signal to be added to n-1, receive write control signal once more after, the then described buffer memory of writing selects the value of signal to return 0, circulation successively; Wherein, n is the number of described buffer unit.
4, the method for table tennis as claimed in claim 1 control is characterized in that, describedly successively the method that described at least three buffer units carry out read data is comprised by the cycle under the control of timer counter signal:
Receive read address information after, each buffer unit output data;
During timer counter signal generation saltus step, inquire about the frame number in the data that each buffer unit exports;
Select frame number to read with the data that the timer counter signal conforms to.
5, as the method for claim 1 or 4 described table tennis controls, it is characterized in that described timer counter signal carries out timer counter by the cycle, the frame number of the data that indication need be read; When reaching timing, described timer counter signal points to next frame number.
6, a kind of device of the control of rattling is characterized in that described device comprises:
Cache module comprises at least three buffer units;
The write data control module is used under the control of the write control signal that data receiver is sent, and successively described at least three buffer units is carried out write data, and is to carry out under the non-read data state of described buffer unit to the write data of buffer unit;
The read data control module is used to produce the timer counter signal, and under the control of described timer counter signal, successively described at least three buffer units is carried out read data by the cycle.
7, the device of table tennis control as claimed in claim 6 is characterized in that the write data control module comprises:
Signal processing unit, receive write control signal after, select the currency of signal to carry out add-one operation to writing buffer memory, indication is carried out write operation to next buffer unit;
Write the buffer memory selected cell, select the value of signal to select the corresponding cache unit to carry out write data according to writing buffer memory.
8, the device of table tennis control as claimed in claim 6 is characterized in that described read data control module comprises:
The timer counter unit is used to produce the timer counter signal, and described timer counter signal carries out timer counter by the cycle, the frame number of the data that indication need be read; When arriving timing, described timer counter signal points to next frame number;
Read the buffer memory selected cell, when timer counter signal generation saltus step, select frame number to read with the data that the timer counter signal conforms to.
9, as the device of claim 7 or 8 described table tennis controls, it is characterized in that described signal processing unit comprises counter, described counter selects the currency of signal to carry out add-one operation to writing buffer memory after receiving write control signal; When counting n-1, carry out add-one operation once more and then return 0, successively circulation; Wherein, n is the number of described buffer unit.
10, the device of table tennis control as claimed in claim 9 is characterized in that described cache module is made of at least three double-port RAMs, and two ports of each random access memory are defined as respectively to be write inbound port and read port; When described timer counter signal generation saltus step, the output data that port is respectively read in scanning selects frame number to read with the data that described timer counter signal conforms to; Under the control of the write control signal that data receiver is sent, select the value of signal according to writing buffer memory, the inbound port of writing of corresponding random access memory is changed to data and writes enable state, under the state of the non-read data of described random access memory, write data to the said write port.
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