CN108234818A - A kind of video frame deposits the implementation method that wheel seeks operative algorithm - Google Patents
A kind of video frame deposits the implementation method that wheel seeks operative algorithm Download PDFInfo
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- CN108234818A CN108234818A CN201711323132.8A CN201711323132A CN108234818A CN 108234818 A CN108234818 A CN 108234818A CN 201711323132 A CN201711323132 A CN 201711323132A CN 108234818 A CN108234818 A CN 108234818A
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- read
- video frame
- video
- signal
- gate array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
Abstract
It is deposited present invention is disclosed a kind of video frame and takes turns the implementation method for seeking operative algorithm, applied in airborne cockpit display, including field programmable gate array FPGA, included the following steps:The three section operating procedures that video signal clock unifies step, video signal line field synchronization unifies step, video frame is deposited.Present invention can apply in airborne cockpit display, deposit ping-pong operation method compared to traditional video frame, the video frame of the invention realized deposits wheel and seeks the situation that operation can thoroughly solve the disconnected frame of dynamic menu appearance, tear, and picture display effect is relatively sharp, stablizes.
Description
Technical field
It is deposited the present invention relates to a kind of video frame and takes turns the implementation method for seeking operative algorithm, belong to the technology neck of Computer Vision
Domain.
Background technology
In modern Airborne integrated display system, the vision signal for often having multichannel difference sequential is sent to airborne indicator,
Airborne indicator can only carry out picture with a set of fixed sequential during actual displayed and show, therefore just need to regard multichannel
The sequential of frequency signal carries out unification.
Traditional sequential unified approach is the carry RAM memory outside FPGA, and RAM is divided into two by FPGA by address field
A section A, B, are written and read A, B section in the way of " ping-pong operation " in turn.But it is inconsistent due to read-write sequence, into
During row A, B sections read-write sequence switches, it may appear that the data portion for being written into or reading inside A or B is present frame, separately
A problem of part is former frame.If the video of input is dynamic menu, the content of present frame and former frame picture is necessarily deposited
In difference, finally show the problem of just will appear " disconnected frame " or " tear " on display picture, seriously affect picture display effect.
Invention content
Present invention aim to address above-mentioned the deficiencies in the prior art, having differences property of multi-channel video signal can influence picture
The problem of display effect, provides a kind of video frame and deposits the implementation method that wheel seeks operative algorithm.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of video frame deposits wheel and seeks the implementation method of operative algorithm, applied in airborne cockpit display, including field-programmable
Logic gate array FPGA, it is characterised in that include the following steps:
S1, video signal clock unify step, and the First Input First Output FIFO in field programmable gate array FPGA is made
For line buffer, First Input First Output FIFO is write data into, then with the second road video letter with the clock of first via vision signal
Number clock data are read from First Input First Output FIFO, realize first via vision signal and the second tunnel vision signal
Clock is unified;
S2, video signal line field synchronization unify step, and one group of RAM memory of field programmable gate array FPGA carries is existing
Field programmable logic gate array FPGA internal logics control the read-write operation of RAM memory, with the row of first via vision signal, field
Synchronizing signal is write data into RAM memory, then on the basis of the row of the second tunnel vision signal, field sync signal by data from
It is read in RAM memory, it is achieved thereby that the unification of first via video synchronization signal and the second road video synchronization signal;
The three section operating procedures that S3, video frame are deposited,
Field programmable gate array FPGA is distinguished by address field when operation RAM memory frame is deposited, is classified as 3 areas
Between A, B, C, read-write operation sequence by following logic perform,
When writing A, B or C is read;
When writing B, C or A is read;
When writing C, A or B is read.
The beneficial effects are mainly as follows:
It can be applied in airborne cockpit display, deposit ping-pong operation method compared to traditional video frame, what the present invention realized regards
Frequency frame deposits wheel and seeks the situation that operation can thoroughly solve the disconnected frame of dynamic menu appearance, tear, and picture display effect is relatively sharp, steady
It is fixed.
Description of the drawings
Fig. 1 is that a kind of video frame of the present invention deposits the structure diagram that wheel seeks the implementation method of operative algorithm.
Specific embodiment
The present invention provides a kind of video frame and deposits the implementation method that wheel seeks operative algorithm.Below in conjunction with attached drawing to the technology of the present invention
Scheme is described in detail, so that it is more readily understood and grasps.
A kind of video frame deposits the implementation method that wheel seeks operative algorithm, and applied in airborne cockpit display, hardware forms
On by 1 FPGA, then add external 1 group of RAM memory composition, by video clock unified modules, row buffering FIFO inside FPGA
Module, RAM control modules three parts composition, as shown in Figure 1.The method takes following steps:
1)The clock of vision signal is unified;
Using altera corp FPGA as core devices, using its abundant on piece FIFO resource as row buffering Buffer, with
The clock of vision signal writes data into FIFO all the way, then is read data from FIFO with the clock of the second tunnel vision signal,
It is it is achieved thereby that the clock of two-path video signal is unified;
2)The row field synchronization of vision signal is unified;
One group of RAM memory of carry, FPGA internal logics control its read-write operation outside FPGA.With first via vision signal
Row, field sync signal write data into RAM, then on the basis of the row of the second tunnel vision signal, field sync signal, by data from
It is read in RAM, it is achieved thereby that the unification of two-path video synchronizing signal;
3)The three section modes of operation that video frame is deposited;
FPGA is distinguished when operation external RAM frame is deposited by address field, is classified as 3 sections A, B, C, read-write operation sequence
It is performed by following logic:
When writing A, B or C is read.After if C is run through, A not yet writes, then after the C that resumes studies;
When writing B, C or A is read.After if A is run through, B not yet writes, then after the A that resumes studies;
When writing C, A or B is read.After if B is run through, C not yet writes, then after the B that resumes studies.
By above description it can be found that a kind of video frame of the present invention deposits the implementation method that wheel seeks operative algorithm, can apply
In airborne cockpit display, ping-pong operation method is deposited compared to traditional video frame, the video frame that the present invention realizes is deposited wheel and sought
Operation can thoroughly solve the situation that dynamic menu disconnected frame occurs, tears, and picture display effect is relatively sharp, stablizes.
Technical scheme of the present invention is fully described above, it should be noted that specific embodiment party of the invention
Formula is simultaneously not limited by the description set out above, the Spirit Essence of those of ordinary skill in the art according to the present invention structure, method or
All technical solutions that function etc. is formed using equivalents or equivalent transformation, all fall within protection scope of the present invention
Within.
Claims (1)
1. a kind of video frame deposits the implementation method that wheel seeks operative algorithm, applied in airborne cockpit display, can be compiled including scene
Journey logic gate array FPGA, it is characterised in that include the following steps:
S1, video signal clock unify step, and the First Input First Output FIFO in field programmable gate array FPGA is made
For line buffer, First Input First Output FIFO is write data into, then with the second road video letter with the clock of first via vision signal
Number clock data are read from First Input First Output FIFO, realize first via vision signal and the second tunnel vision signal
Clock is unified;
S2, video signal line field synchronization unify step, and one group of RAM memory of field programmable gate array FPGA carries is existing
Field programmable logic gate array FPGA internal logics control the read-write operation of RAM memory, with the row of first via vision signal, field
Synchronizing signal is write data into RAM memory, then on the basis of the row of the second tunnel vision signal, field sync signal by data from
It is read in RAM memory, it is achieved thereby that the unification of first via video synchronization signal and the second road video synchronization signal;
The three section operating procedures that S3, video frame are deposited,
Field programmable gate array FPGA is distinguished by address field when operation RAM memory frame is deposited, is classified as 3 areas
Between A, B, C, read-write operation sequence by following logic perform,
When writing A, B or C is read;
When writing B, C or A is read;
When writing C, A or B is read.
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CN201711323132.8A CN108234818B (en) | 2017-12-13 | 2017-12-13 | Method for realizing video frame memory round searching operation algorithm |
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CN201711323132.8A CN108234818B (en) | 2017-12-13 | 2017-12-13 | Method for realizing video frame memory round searching operation algorithm |
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CN108234818B CN108234818B (en) | 2020-10-20 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101236528A (en) * | 2008-02-20 | 2008-08-06 | 华为技术有限公司 | Ping-pong control method and apparatus |
CN102663987A (en) * | 2012-03-19 | 2012-09-12 | 京东方科技集团股份有限公司 | Display driving method and display driving device of dual-channel video signals |
US20150347023A1 (en) * | 2011-08-04 | 2015-12-03 | Alexandr Konovalov | Memory coalescing computer-implemented method, system, apparatus and computer-readable media |
CN105872432A (en) * | 2016-04-21 | 2016-08-17 | 天津大学 | Rapid self-adaptive frame rate conversion device and method |
CN106791488A (en) * | 2016-12-28 | 2017-05-31 | 浙江宇视科技有限公司 | A kind of synchronous tiled display methods and device |
-
2017
- 2017-12-13 CN CN201711323132.8A patent/CN108234818B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101236528A (en) * | 2008-02-20 | 2008-08-06 | 华为技术有限公司 | Ping-pong control method and apparatus |
US20150347023A1 (en) * | 2011-08-04 | 2015-12-03 | Alexandr Konovalov | Memory coalescing computer-implemented method, system, apparatus and computer-readable media |
CN102663987A (en) * | 2012-03-19 | 2012-09-12 | 京东方科技集团股份有限公司 | Display driving method and display driving device of dual-channel video signals |
CN105872432A (en) * | 2016-04-21 | 2016-08-17 | 天津大学 | Rapid self-adaptive frame rate conversion device and method |
CN106791488A (en) * | 2016-12-28 | 2017-05-31 | 浙江宇视科技有限公司 | A kind of synchronous tiled display methods and device |
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