CN102663987A - Display driving method and display driving device of dual-channel video signals - Google Patents
Display driving method and display driving device of dual-channel video signals Download PDFInfo
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- CN102663987A CN102663987A CN2012100733319A CN201210073331A CN102663987A CN 102663987 A CN102663987 A CN 102663987A CN 2012100733319 A CN2012100733319 A CN 2012100733319A CN 201210073331 A CN201210073331 A CN 201210073331A CN 102663987 A CN102663987 A CN 102663987A
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- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
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Abstract
Embodiments of the invention disclose a display driving method and a display driving device of dual-channel video signals, relating the field of signal processing. The method and the device can merge dual-channel video signals into one-channel video signal containing dual-channel video information, wherein the dual-channel video signals are different in clock frequencies and completely different in contents. The method comprises reading and temporarily storing first video signals and second video signals in an interval of a clock period, and outputting the read and temporarily stored first and second video signals in the same clock period, wherein sub-pixels of the outputted first and second video signals are assigned at intervals. The method and the device of the invention are applied in dual-vision display.
Description
Technical field
The present invention relates to the signal Processing field, relate in particular to a kind of display drive method and device thereof of two-way vision signal.
Background technology
The development of display technique has brought double-vision display to people, and this display can demonstrate different images on same display screen, and represents respectively to the user who is positioned at display left side and right side.
Such as, on automobile, the driver need check GPS through display, and the passenger on the front passenger's seat wants to watch entertainment through display simultaneously, and a regular display can not satisfy both sides' demand certainly simultaneously.Double vision shows that this new technology can address this problem well.When showing the information of GPS to the driver, double-vision display can also show the entertainment that the passenger wants to the passenger.
But; The inventor finds in realizing process of the present invention; Double-vision display of the prior art also fails to solve well with two different fully independently vision signals of clock frequency problem that contains the vision signal of two video image informations simultaneously that permeates, and this makes troubles for application of double-vision display.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of display drive method and device thereof of two-way vision signal, can be with the two-way clock frequency the inequality and diverse vision signal of content merge into one the tunnel comprise two-path video information vision signal.
For solving the problems of the technologies described above, the display drive method of two-way vision signal of the present invention and device thereof adopt following technical scheme:
A kind of display drive method of two-way vision signal, said two-way vision signal comprises first vision signal and second vision signal, said method comprises:
Read and temporary first vision signal and second vision signal with the interval of a clock period;
Read and temporary first vision signal and the output of second vision signal said with the identical clock period, the sub-pixel of exporting first vision signal and second vision signal is intervally arranged.
To read and temporary first vision signal and second vision signal are specially at the interval of a clock period:
To read second vision signal and be temporarily stored in the fifo registers in the interval of clock period of one second vision signal;
Read with the interval of clock period of one first vision signal and to be temporarily stored in second vision signal in the fifo registers and to be temporarily stored in the RAS;
Interval with clock period of one first vision signal is read first vision signal and is temporarily stored in second vision signal in the RAS, and said first vision signal that reads and second vision signal are temporarily stored in the impact damper.
Said said first vision signal that reads and second vision signal are temporarily stored in the impact damper is specially:
The sub-pixel data of said first vision signal that reads and second vision signal is temporarily stored in the impact damper at interval.
A kind of display drive apparatus of two-way vision signal, said two-way vision signal comprises first vision signal and second vision signal, said device comprises:
Reading cells is used for reading and temporary first vision signal and second vision signal with the interval of a clock period;
Output unit is used for reading and temporary first vision signal and the output of second vision signal said with the identical clock period, and the sub-pixel of exporting first vision signal and second vision signal is intervally arranged.
Said reading cells comprises:
First reads memory module, be used for reading second vision signal and being temporarily stored in fifo registers with the interval of clock period of one second vision signal,
With
Be used for reading second vision signal that is temporarily stored in fifo registers and being temporarily stored in the RAS with the interval of clock period of one first vision signal;
Second reads memory module; Be used for second vision signal that reads first vision signal and be temporarily stored in RAS with the interval of clock period of one first vision signal, and said first vision signal that reads and second vision signal are temporarily stored in the impact damper.
Said second reads memory module specifically is used for:
Interval with clock period of one first vision signal is read first vision signal and is temporarily stored in second vision signal in the RAS, and the sub-pixel data of said first vision signal that reads and second vision signal is temporarily stored in the impact damper at interval.
In technical scheme of the present invention; Read and temporary first vision signal and second vision signal with the interval of a clock period; Afterwards, read and temporary first vision signal and the output of second vision signal said with the identical clock period, temporary synchronously and export simultaneously through first vision signal that will read and second vision signal; And the sub-pixel of exporting first vision signal and second vision signal is intervally arranged; Be equivalent to export one the tunnel through handling and comprise the vision signal of two-path video signal content, through the disparity barrier on the double vision display panel or the effect of lenticulation, the effect that the double vision that can realize ideal shows.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the display drive method process flow diagram one of two-way vision signal in the embodiment of the invention;
Fig. 2 is the display drive method flowchart 2 of two-way vision signal in the embodiment of the invention;
Fig. 3 is the second vision signal sequential chart in the embodiment of the invention;
Fig. 4 is the first vision signal sequential chart in the embodiment of the invention;
Fig. 5 is a buffer stores space synoptic diagram in the embodiment of the invention;
Fig. 6 is the display drive apparatus synoptic diagram of two-way vision signal in the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one
The embodiment of the invention provides a kind of display drive method of two-way vision signal, and said two-way vision signal comprises first vision signal and second vision signal, and is as shown in Figure 1, and this method comprises:
Step S101, read and temporary first vision signal and second vision signal with the interval of a clock period;
In order to be implemented in the purpose that shows the two-path video signal on the display panel simultaneously synchronously, each two field picture to the multipotency of each road vision signal shows the content of half pixel on this display panel.In the prior art; Each clock period; One tunnel vision signal is to the data of a pixel of display device input, so, in order can on same display screen, to show the two-path video signal simultaneously and to guarantee certain display resolution; Concerning each road vision signal, read this road vision signal with the interval of a clock period and promptly mean a pixel data that reads this road vision signal with the interval of a pixel.
After respectively first vision signal and second vision signal being read with the interval of a clock period; First vision signal and second vision signal through reading are kept in synchronously and are exported simultaneously, can realize first vision signal and second vision signal are shown on same display panel simultaneously synchronously.
As shown in Figure 2, step S101 is specially:
Step S1011, to read second vision signal and be temporarily stored in the fifo registers in the interval of clock period of one second vision signal;
As shown in Figure 3; In time period, the second vision signal enable signal is a high level at t1, and this was illustrated in this time period; When each second vision signal rising edge of clock signal arrives; Second vision signal is upgraded the pixel data on the data bus of display device, and before the next second vision signal rising edge of clock signal arrived, the pixel data on the data bus remained unchanged.
Second counter among Fig. 3 is a binary addition counter, and the second vision signal enable signal is the enable signal of second counter, and when the second vision signal enable signal was high level, second counter was activated, and begins to carry out plus coujnt.When the second vision signal enable signal was high level and the arrival of the second vision signal rising edge of clock signal, second counter was done a binary addition computing; And when the second vision signal enable signal becomes low level, second counter O reset.Particularly; The value of second counter is zero before arriving the zero hour of t1 time period, gets into t1 after the time period, when first rising edge of the second vision signal clock signal arrives; Second counter originally is being to add 1 on 0 the output valve, and then the output valve of second counter becomes 1; When second rising edge of the second vision signal clock signal arrived, second counter was to originally being that 1 output valve adds 1, then according to the binary addition rule; The output valve strain of second counter is 10; But second counter is a up counter, and output valve has only one, and then this moment, second counter was got 10 end position 0; House first place 1, this moment, the output valve of second counter became 0 by 1.
Fifo registers is called for short FIFO, and FIFO is a kind of typical high-speed buffer device, and the reading and writing data of synchronization fifo drives through outside clock signal, is applicable to video data stream is at a high speed carried out buffer memory.In embodiments of the present invention; It receives second counter and the second vision signal clock signal driven in common; In the output valve of second counter is that the 1 and second vision signal clock signal is when being negative edge; FIFO is temporarily stored in the storage space in the FIFO from the pixel data that data bus reads second vision signal, then can be known by Fig. 3, at t2 in the time period; FIFO is the data on the readout data bus not; Then between the pixel data that reads each time of FIFO and the preceding pixel data that once reads at interval a clock period do not carry out reads pixel data, then when second vision signal is imported the pixel data of a two field picture to the data bus of display device after, FIFO has in fact only read and has kept in half pixel data of second this two field picture of vision signal.
Need to prove that binary figure place that the storage space of FIFO can be stored just is the number of bits of a pixel data, then each storage space in the FIFO can only be stored a pixel data.
Step S1012, read with the interval of clock period of one first vision signal and to be temporarily stored in second vision signal in the fifo registers and to be temporarily stored in the RAS;
As shown in Figure 4, similar with Fig. 3, at t3 in the time period; The first vision signal enable signal is a high level; In the section, when the first vision signal rising edge of clock signal arrived, first vision signal was upgraded the pixel data in another data bus at this moment.Similar with second counter, the first vision signal enable signal is the enable signal of first counter, and when the first vision signal enable signal was low level, the output valve of first counter was always 0; When the first vision signal enable signal is high level; The output valve of first counter changes when each first vision signal rising edge of clock signal arrives; Because first counter is the same with second counter to be a binary addition counter, then the output valve of first counter is the same with second counter changes between 1 and 0.Can know by Fig. 4 that specifically at t3 in the time period, when the first vision signal rising edge of clock signal arrived, the output valve of first counter became 1 or become 0 by 1 by 0.
RAS is called for short RAM, the output valve of first counter be 0 and FIFO in when pixel data is arranged; Read a pixel data in the FIFO and write in the storage space in the RAM; What the pixel data that reads of RAM all write RAM each time writes address storage space pointed, after RAM finishes to write, writes the address and upgrades; RAM adds 1 existing writing on the address, it is adjacent to write the storage space that points to the address before storage space that writing after the renewal pointed to the address and the renewal.
In the output valve of first counter is 0 but in the FIFO during no pixel data, RAM does not carry out read-write operation, simultaneously, does not change the address that writes of pointing to storage space yet.
Need to prove that the characteristics of FIFO are that order writes data orders output data, a half-pixel data that the is equivalent to second vision signal according to pixels input sequence of data is carried out buffer memory.
In the prior art; In vision signal after the data bus of display device input one-row pixels data; Vision signal gets into the crack time in the ranks, and in the ranks the crack is in the time in this section, and vision signal is suspended to the display device input pixel data; Be expert at after end off time, vision signal is to the pixel data of display device input next line.
Similarly, after vision signal was imported the pixel data of a complete frame to display device, vision signal can get into the frame gap time, and in the time, vision signal is suspended to the display device input pixel data at frame gap.The length of frame gap time is the several times of horizontal-scanning interval, and the concrete length of horizontal-scanning interval is the data transfer time and crack time sum in the ranks.
When second vision signal is in the ranks crack time or frame gap during the time, second vision signal is suspended to the display device input pixel data, and the number of the pixel data of FIFO stored does not increase.And this moment, no matter whether the first vision signal enable signal still was high level; All having first counter is moment of 0; Off time or frame gap are in the time so be expert at, if having pixel data in the FIFO, RAM continues to carry out the task of reading FIFO interior pixel data; There are pixel data off time or frame gap time in the FIFO before arriving even be expert at, and all can be emptied by the reading of RAM-write activity through the residual pixel data in the FIFO after arbitrary off time.
Further; The price of high capacity FIFO is comparatively high; From the consideration of cost, the capacity of FIFO that is used for video data is carried out buffer memory is less, in embodiments of the present invention; The minimum capacity of FIFO is the half the of one-row pixels data size, and the minimum capacity of RAM can be designed to the size of a half-pixel data of a two field picture.
Special; The process frame gap is after the time; When the view data of next frame arrived, when RAM learnt that according to the control signal of second vision signal pixel data of second vision signal input this moment is first pixel data of a two field picture, RAM write address zero setting with it.
Step S1013, read first vision signal and be temporarily stored in second vision signal in the RAS, and said first vision signal that reads and second vision signal are temporarily stored in the impact damper with the interval of clock period of one first vision signal.
Particularly, the sub-pixel data with said first vision signal that reads and second vision signal is temporarily stored in the impact damper at interval.
As shown in Figure 4; At t3 in the time period; First vision signal is to the display device input pixel data; When the output valve of first counter is the negative edge arrival of the 1 and first vision signal clock signal; Impact damper read simultaneously first vision signal pixel data and second vision signal pixel data and the mode that two pixel datas are stored with sub-pixel at interval is stored in six storage spaces in the impact damper successively, as shown in Figure 5, be six storage spaces of impact damper; 1a, 1b, three storage spaces of 1c are used to deposit three subpixels data of a pixel of first vision signal, and 2a, 2b, three storage spaces of 2c are used to deposit three subpixels data of a pixel of second vision signal.
The pixel data of first vision signal that impact damper reads is from the data bus of first vision signal input data; The pixel data of second vision signal that is read is from a storage space in the RAM; A pixel data in impact damper reads RAM, RAM reads the address with it and adds 1.
Need to prove; When the control signal of first vision signal shows that first vision signal is when display device is imported the picture signal of a new frame; RAM reads address zero setting with it; Point to first storage space in the RAM, a pixel data in impact damper reads RAM, RAM reads the address with it and adds 1.
Step S102, read and temporary first vision signal and the output of second vision signal said with the identical clock period, the sub-pixel of exporting first vision signal and second vision signal is intervally arranged.
Because first vision signal and second vision signal are fully independently vision signals of two-way, so the clock of two-path video signal does not have fixed phase relation, even the clock frequency of two-path video signal is inequality.In order can on same display panel, to show simultaneously; After reaching purpose that clock, the frequency of first vision signal and second vision signal is unified through temporary first vision signal and second vision signal, will pass through the first temporary vision signal and second vision signal again with identical clock period output.
In embodiments of the present invention, the outputting video signal clock signal is identical with the first vision signal clock signal, and the outputting video signal enable signal is the time-delay of the first vision signal enable signal, and delay time is the one-period of the first vision signal clock signal.When the outputting video signal enable signal is high level and the arrival of the first vision signal rising edge of clock signal; Impact damper exports the data in storage space 1a, 2b, the 1c to the outputting video signal bus; When the next first vision signal rising edge of clock signal arrives; Impact damper exports the data in storage space 2a, 1b, the 2c to the outputting video signal bus; When display panel shows; On the display panel laterally two adjacent pixels show two pixel datas seeing off when two adjacent rising edges arrive respectively, through the disparity barrier on the double vision display panel or the effect of lenticulation, can reach and make way for the purpose that display left side and the user on right side see different video images.
In the technical scheme of present embodiment; Read and temporary first vision signal and second vision signal with the interval of a clock period; Afterwards, read and temporary first vision signal and the output of second vision signal said with the identical clock period, temporary synchronously and export simultaneously through first vision signal that will read and second vision signal; And the sub-pixel of exporting first vision signal and second vision signal is intervally arranged; Be equivalent to export one the tunnel through handling and comprise the vision signal of two-path video signal content, through the disparity barrier on the double vision display panel or the effect of lenticulation, the effect that the double vision that can realize ideal shows.
Embodiment two
The embodiment of the invention provides a kind of display drive apparatus of two-way vision signal, and is as shown in Figure 6, and this device comprises:
Reading cells 11 is used for reading and temporary first vision signal and second vision signal with the interval of a clock period;
In order to be implemented in the purpose that shows the two-path video signal on the display panel simultaneously synchronously, each two field picture to the multipotency of each road vision signal shows the content of half pixel on this display panel.In the prior art; Each clock period; One tunnel vision signal is to the data of a pixel of display device input, so, in order can on same display screen, to show the two-path video signal simultaneously and to guarantee certain display resolution; Concerning each road vision signal, reading cells 11 reads this road vision signal with the interval of a clock period and promptly means a pixel data that reads this road vision signal with the interval of a pixel.
After respectively first vision signal and second vision signal being read with the interval of a clock period; First vision signal and second vision signal through reading are kept in synchronously and are exported simultaneously, can realize first vision signal and second vision signal are shown on same display panel simultaneously synchronously.
As shown in Figure 6, shown in reading cells 11 specifically comprise:
First reads memory module 111; Be used for reading second vision signal and being temporarily stored in fifo registers and being used for reading second vision signal that is temporarily stored in fifo registers and being temporarily stored in the RAS with the interval of clock period of one first vision signal with the interval of clock period of one second vision signal;
Particularly, as shown in Figure 3, at t1 in the time period; The second vision signal enable signal is a high level; This was illustrated in this time period, and when each second vision signal rising edge of clock signal arrived, second vision signal was upgraded the pixel data on the data bus of display device; Before the next second vision signal rising edge of clock signal arrived, the pixel data on the data bus remained unchanged.
Second counter among Fig. 3 is a binary addition counter, and the second vision signal enable signal is the enable signal of second counter, and when the second vision signal enable signal was high level, second counter was activated, and begins to carry out plus coujnt.When the second vision signal enable signal was high level and the arrival of the second vision signal rising edge of clock signal, second counter was done a binary addition computing; And when the second vision signal enable signal becomes low level, second counter O reset.Particularly; The value of second counter is zero before arriving the zero hour of t1 time period, gets into t1 after the time period, when first rising edge of the second vision signal clock signal arrives; Second counter originally is being to add 1 on 0 the output valve, and then the output valve of second counter becomes 1; When second rising edge of the second vision signal clock signal arrived, second counter was to originally being that 1 output valve adds 1, then according to the binary addition rule; The output valve strain of second counter is 10; But second counter is a up counter, and output valve has only one, and then this moment, second counter was got 10 end position 0; House first place 1, this moment, the output valve of second counter became 0 by 1.
Fifo registers is called for short FIFO, and FIFO is a kind of typical high-speed buffer device, and the reading and writing data of synchronization fifo drives through outside clock signal, is applicable to video data stream is at a high speed carried out buffer memory.In embodiments of the present invention; It receives second counter and the second vision signal clock signal driven in common; In the output valve of second counter is that the 1 and second vision signal clock signal is when being negative edge; FIFO is temporarily stored in the storage space in the FIFO from the pixel data that data bus reads second vision signal, then can be known by Fig. 3, at t2 in the time period; FIFO is the data on the readout data bus not; Then between the pixel data that reads each time of FIFO and the preceding pixel data that once reads at interval a clock period do not carry out reads pixel data, then when second vision signal is imported the pixel data of a two field picture to the data bus of display device after, FIFO has in fact only read and has kept in half pixel data of second this two field picture of vision signal.
Need to prove that binary figure place that the storage space of FIFO can be stored just is the number of bits of a pixel data, then each storage space in the FIFO can only be stored a pixel data.
As shown in Figure 4, similar with Fig. 3, at t3 in the time period; The first vision signal enable signal is a high level; In the section, when the first vision signal rising edge of clock signal arrived, first vision signal was upgraded the pixel data in its data bus at this moment.Similar with second counter, the first vision signal enable signal is the enable signal of first counter, and when the first vision signal enable signal was low level, the output valve of first counter was always 0; When the first vision signal enable signal is high level; The output valve of first counter changes when each first vision signal rising edge of clock signal arrives; Because first counter is the same with second counter to be a binary addition counter, then the output valve of first counter is the same with second counter changes between 1 and 0.Can know by Fig. 4 that specifically at t3 in the time period, when the first vision signal rising edge of clock signal arrived, the output valve of first counter became 1 or become 0 by 1 by 0.
RAS is called for short RAM, the output valve of first counter be 0 and FIFO in when pixel data is arranged; Read a pixel data in the FIFO and write in the storage space in the RAM; What the pixel data that reads of RAM all write RAM each time writes address storage space pointed, after RAM finishes to write, writes the address and upgrades; RAM adds 1 existing writing on the address, it is adjacent to write the storage space that points to the address before storage space that writing after the renewal pointed to the address and the renewal.
In the output valve of first counter is 0 but in the FIFO during no pixel data, RAM does not carry out read-write operation, simultaneously, does not change the address that writes of pointing to storage space yet.
Need to prove that the characteristics of FIFO are that order writes data orders output data, a half-pixel data that the is equivalent to second vision signal according to pixels input sequence of data is carried out buffer memory.
In the prior art; In vision signal after the data bus of display device input one-row pixels data; Vision signal gets into the crack time in the ranks, and in the ranks the crack is in the time in this section, and vision signal is suspended to the display device input pixel data; Be expert at after end off time, vision signal is to the pixel data of display device input next line.
Similarly, after vision signal was imported the pixel data of a complete frame to display device, vision signal can get into the frame gap time, and in the time, vision signal is suspended to the display device input pixel data at frame gap.The length of frame gap time is the several times of horizontal-scanning interval, and the concrete length of horizontal-scanning interval is the data transfer time and crack time sum in the ranks.
When second vision signal is in the ranks crack time or frame gap during the time, second vision signal is suspended to the display device input pixel data, and the number of the pixel data of FIFO stored does not increase.And this moment, no matter whether the first vision signal enable signal still was high level; All having first counter is moment of 0; Off time or frame gap are in the time so be expert at, if having pixel data in the FIFO, RAM continues to carry out the task of reading FIFO interior pixel data; There are pixel data off time or frame gap time in the FIFO before arriving even be expert at, and all can be emptied by the reading of RAM-write activity through the residual pixel data in the FIFO after arbitrary off time.
Further; The price of high capacity FIFO is comparatively high; From the consideration of cost, the capacity of FIFO that is used for video data is carried out buffer memory is less, in embodiments of the present invention; The minimum capacity of FIFO is the half the of one-row pixels data size, and the minimum capacity of RAM can be designed to the size of a half-pixel data of a two field picture.
Special; The process frame gap is after the time; When the view data of next frame arrived, when RAM learnt that according to the control signal of second vision signal pixel data of second vision signal input this moment is first pixel data of a two field picture, RAM write address zero setting with it.
Second reads memory module 112; Be used for second vision signal that reads first vision signal and be temporarily stored in RAS with the interval of clock period of one first vision signal, and said first vision signal that reads and second vision signal are temporarily stored in the impact damper.
Said second reads memory module 112 specifically is used for: second vision signal that reads first vision signal and be temporarily stored in RAS with the interval of clock period of one first vision signal, and the sub-pixel data of said first vision signal that reads and second vision signal is temporarily stored in the impact damper at interval.
As shown in Figure 4; At t3 in the time period; First vision signal is to the display device input pixel data; When the output valve of first counter is the negative edge arrival of the 1 and first vision signal clock signal; Impact damper read simultaneously first vision signal pixel data and second vision signal pixel data and the mode that two pixel datas are stored with sub-pixel at interval is stored in six storage spaces in the impact damper successively, as shown in Figure 5, be six storage spaces of impact damper; 1a, 1b, three storage spaces of 1c are used to deposit three subpixels data of a pixel of first vision signal, and 2a, 2b, three storage spaces of 2c are used to deposit three subpixels data of a pixel of second vision signal.
The pixel data of first vision signal that impact damper reads is from the data bus of first vision signal input data; The pixel data of second vision signal that is read is from a storage space in the RAM; A pixel data in impact damper reads RAM, RAM reads the address with it and adds 1.
Need to prove; When the control signal of first vision signal shows that first vision signal is when display device is imported the picture signal of a new frame; RAM reads address zero setting with it; Point to first storage space in the RAM, a pixel data in impact damper reads RAM, RAM reads the address with it and adds 1.
Because first vision signal and second vision signal are fully independently vision signals of two-way, so the clock of two-path video signal does not have fixed phase relation, even the clock frequency of two-path video signal is inequality.In order can on same display panel, to show simultaneously; After reaching purpose that clock, the frequency of first vision signal and second vision signal is unified through temporary first vision signal and second vision signal, output unit 12 will pass through the first temporary vision signal and second vision signal again with identical clock period output.
In embodiments of the present invention, the outputting video signal clock signal is identical with the first vision signal clock signal, and the outputting video signal enable signal is the time-delay of the first vision signal enable signal, and delay time is the one-period of the first vision signal clock signal.When the outputting video signal enable signal is high level and the arrival of the first vision signal rising edge of clock signal; Impact damper exports the data in storage space 1a, 2b, the 1c to the outputting video signal bus; When the next first vision signal rising edge of clock signal arrives; Impact damper exports the data in storage space 2a, 1b, the 2c to the outputting video signal bus; When display panel shows; On the display panel laterally two adjacent pixels show two pixel datas seeing off when two adjacent rising edges arrive respectively, through the disparity barrier on the double vision display panel or the effect of lenticulation, can reach and make way for the purpose that display left side and the user on right side see different video images.
In the technical scheme of present embodiment; Read and temporary first vision signal and second vision signal with the interval of a clock period; Afterwards, read and temporary first vision signal and the output of second vision signal said with the identical clock period, temporary synchronously and export simultaneously through first vision signal that will read and second vision signal; And the sub-pixel of exporting first vision signal and second vision signal is intervally arranged; Be equivalent to export one the tunnel through handling and comprise the vision signal of two-path video signal content, through the disparity barrier on the double vision display panel or the effect of lenticulation, the effect that the double vision that can realize ideal shows.
Through the description of above embodiment, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential common hardware, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding; The part that technical scheme of the present invention contributes to prior art in essence in other words can be come out with the embodied of software product, and this computer software product is stored in the storage medium that can read, like the floppy disk of computing machine; Hard disk or CD etc.; Comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technician who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of said claim.
Claims (6)
1. the display drive method of a two-way vision signal, said two-way vision signal comprises first vision signal and second vision signal, it is characterized in that, said method comprises:
Read and temporary first vision signal and second vision signal with the interval of a clock period;
Read and temporary first vision signal and the output of second vision signal said with the identical clock period, the sub-pixel of exporting first vision signal and second vision signal is intervally arranged.
2. method according to claim 1 is characterized in that, to read and temporary first vision signal and second vision signal are specially at the interval of a clock period:
To read second vision signal and be temporarily stored in the fifo registers in the interval of clock period of one second vision signal;
Read with the interval of clock period of one first vision signal and to be temporarily stored in second vision signal in the fifo registers and to be temporarily stored in the RAS;
Interval with clock period of one first vision signal is read first vision signal and is temporarily stored in second vision signal in the RAS, and said first vision signal that reads and second vision signal are temporarily stored in the impact damper.
3. method according to claim 2 is characterized in that, said said first vision signal that reads and second vision signal are temporarily stored in the impact damper is specially:
The sub-pixel data of said first vision signal that reads and second vision signal is temporarily stored in the impact damper at interval.
4. the display drive apparatus of a two-way vision signal, said two-way vision signal comprises first vision signal and second vision signal, it is characterized in that, said device comprises:
Reading cells is used for reading and temporary first vision signal and second vision signal with the interval of a clock period;
Output unit is used for reading and temporary first vision signal and the output of second vision signal said with the identical clock period, and the sub-pixel of exporting first vision signal and second vision signal is intervally arranged.
5. device according to claim 4 is characterized in that, said reading cells comprises:
First reads memory module, be used for reading second vision signal and being temporarily stored in fifo registers with the interval of clock period of one second vision signal,
With
Be used for reading second vision signal that is temporarily stored in fifo registers and being temporarily stored in the RAS with the interval of clock period of one first vision signal;
Second reads memory module; Be used for second vision signal that reads first vision signal and be temporarily stored in RAS with the interval of clock period of one first vision signal, and said first vision signal that reads and second vision signal are temporarily stored in the impact damper.
6. device according to claim 5 is characterized in that, said second reads memory module specifically is used for:
Interval with clock period of one first vision signal is read first vision signal and is temporarily stored in second vision signal in the RAS, and the sub-pixel data of said first vision signal that reads and second vision signal is temporarily stored in the impact damper at interval.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210073331.9A CN102663987B (en) | 2012-03-19 | 2012-03-19 | Display driving method and display driving device of dual-channel video signals |
| PCT/CN2012/084003 WO2013139126A1 (en) | 2012-03-19 | 2012-11-02 | Display driving method of dual-channel video signals, and device thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210073331.9A CN102663987B (en) | 2012-03-19 | 2012-03-19 | Display driving method and display driving device of dual-channel video signals |
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| CN102663987B CN102663987B (en) | 2015-04-01 |
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| WO (1) | WO2013139126A1 (en) |
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| WO2013139126A1 (en) * | 2012-03-19 | 2013-09-26 | 京东方科技集团股份有限公司 | Display driving method of dual-channel video signals, and device thereof |
| CN108234818A (en) * | 2017-12-13 | 2018-06-29 | 苏州长风航空电子有限公司 | A kind of video frame deposits the implementation method that wheel seeks operative algorithm |
| CN110072124A (en) * | 2018-01-24 | 2019-07-30 | 杭州海康威视数字技术股份有限公司 | A kind of pair of vision signal carries out compound method, apparatus and electronic equipment |
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| CN102663987B (en) * | 2012-03-19 | 2015-04-01 | 京东方科技集团股份有限公司 | Display driving method and display driving device of dual-channel video signals |
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- 2012-03-19 CN CN201210073331.9A patent/CN102663987B/en not_active Expired - Fee Related
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| WO1996041328A1 (en) * | 1995-06-07 | 1996-12-19 | Seiko Epson Corporation | Computer system with dual-panel lcd display |
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| CN108234818A (en) * | 2017-12-13 | 2018-06-29 | 苏州长风航空电子有限公司 | A kind of video frame deposits the implementation method that wheel seeks operative algorithm |
| CN110072124A (en) * | 2018-01-24 | 2019-07-30 | 杭州海康威视数字技术股份有限公司 | A kind of pair of vision signal carries out compound method, apparatus and electronic equipment |
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Also Published As
| Publication number | Publication date |
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| WO2013139126A1 (en) | 2013-09-26 |
| CN102663987B (en) | 2015-04-01 |
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