CN102625086A

CN102625086A - DDR2 (Double Data Rate 2) storage method and system for high-definition digital matrix

Info

Publication number: CN102625086A
Application number: CN2012100818302A
Authority: CN
Inventors: 吴亮
Original assignee: Shenzhen Infinova Ltd
Current assignee: Shenzhen Infinova Ltd
Priority date: 2012-03-26
Filing date: 2012-03-26
Publication date: 2012-08-01
Anticipated expiration: 2032-03-26
Also published as: CN102625086B

Abstract

The invention provides a DDR2 (Double Data Rate 2) storage method and system for a high-definition digital matrix. The DDR2 storage method comprises the steps of: writing SDI (Serial Digital Interface) video signals, which are transmitted by a front-end camera and are processed and controlled by an FPGA (Field Program Gate Array), into a DDR2 storage; meanwhile, reading data from the storage by the FPGA, and processing and converting the data into SDI signals to be transmitted to a rear-end monitor for display, by the FPGA; detecting whether video input is available or not by the FPGA; and if not, controlling the DDR2 storage to continuously output complete video images, which are stored into the DDR2 finally, for the longest time 2S by a DDR2 controller in the FPGA. In such a way, not only is the continuous display of video signals realized, but also the rear-end monitor is prevented from a blank screen phenomenon.

Description

A kind of DDR2 storage means and system that is used for the high-definition digital matrix

Technical field

The application relates to protection and monitor field, particularly a kind of DDR2 storage means and system that is used for the high-definition digital matrix.

Background technology

High-definition digital SDI matrix is an incompressible high definition watch-dog; Transmission be the high definition SDI vision signal of non-compression, the whole system scheme comprises front end such as video camera, quick, the center is controlled like switching matrix; Rear end display device such as DVR, monitor etc., these all need support the SDI video.Like this rear end display device is had higher requirement, the high definition monitor needs the interface of SDI, supports the video of various SDI forms to show.But the high definition monitor cost of this band SDI interface is all than higher, and the high definition monitor application of band HDMI interface is more extensive.Our demonstration just can be changeed the boxcar of HDMI through SDI like this, changes into to output to the HDMI monitor again behind the HDMI signal and show.But this can bring an other problem again; Sdi signal outputs to the HDMI monitor again through the boxcar that SDI changes HDMI; This can show the signal video frequency of SDI bring delay, particularly carries out after video channel switches through the high-definition digital matrix, and sdi signal has a process of growing out of nothing; Time-delay can be very big, and the characteristic that this nothing of just being known as with sdi signal is delayed time is not inconsistent.Though be not the time-delay of being introduced by sdi signal itself, the client uses switches and when showing, can the have an appointment blank screen phenomenon of 2S of monitor is just very inconvenient for the application of SDI.Based on this, we consider the memory technology of a kind of DDR2, and when the high definition matrix switched sdi signal, matrix can be at the new image of the longest 2S of output that continues before switching image stabilization, and this image is the last display image of that passage before switching.After new Switch Video picture signal is stable; That channel image after will switching is again exported; The SDI vision signal that has guaranteed matrix output like this is one section continuous images signal; Avoid the process that sdi signal grows out of nothing in the handoff procedure, also just avoided the phenomenon of monitor blank screen in the handoff procedure.

Summary of the invention

The present invention has proposed a kind of DDR2 storage means and system that is used for the high-definition digital matrix in order to solve the phenomenon of back end monitor blank screen.

For realizing above-mentioned purpose; The present invention proposes a kind of DDR2 storage means that is used for the high-definition digital matrix, and wherein the SDI vision signal that transmits of front-end camera is transferred to FPGA after treatment, writes in the DDR2 memory through processing and the control of FPGA; The DDR2 of FPGA control simultaneously memory; Reading of data from this memory, and be converted into sdi signal and send to back end monitor and show FPGA will detect whether video input is arranged through handling; If there is not video input, the DDR2 controller among the FPGA can control the DDR2 memory continue the output maximum duration be 2S deposit the complete video image among the DDR2 at last in.

Further, when video is imported, detect and whether write the FIFO remaining space greater than burst length in the said DDR2 controller; If then controller produces the request of writing, and enable signal is write in generation; The video data of input is write writing among the fifo of DDR2 controller; Until writing the data that expired a burst length, send this moment and write the CMD order, in the DDR2 memory, write video data.

Further; When writing a full frame image data in the said DDR2 memory; Said DDR2 controller switches bank, begins to write new data from the first address of next bank, the data that deposit in before overriding; Bring in constant renewal in the data that deposit in like this, guarantee there is the complete view data of two frames among the DDR2 always.

Further, the process of reading of data is in the DDR2 memory, to write to have expired a frame image data, and CMD is read in transmission orders the controller to DDR2; Produce simultaneously and read enable signal; Reading of data is read fifo to the DDR2 controller from the DDR2 memory, when the DDR2 controller read burst length data are arranged in the fifo time, said DDR2 controller produces read request and generates and reads to enable; With data from the DDR2 controller read read the fifo, be transferred to back end monitor and show.

The present invention also proposes a kind of DDR2 storage system that is used for the high-definition digital matrix; Comprise front-end camera, FPGA, DDR2 memory and back end monitor; Wherein the SDI vision signal that transmits of front-end camera is transferred to FPGA after treatment; Processing and control through FPGA write in the DDR2 memory, the DDR2 of FPGA control simultaneously memory, reading of data from this memory; And be converted into sdi signal and send to back end monitor and show through handling; FPGA will detect whether video input is arranged, if there is not the video input, the DDR2 controller among the FPGA can control the DDR2 memory continue the output maximum duration be 2S deposit the complete video image among the DDR2 at last in.

The present invention also proposes a kind of high-definition digital matrix, comprises above-mentioned DDR2 storage system.

Through technique scheme, both realized the continuous demonstration of vision signal, avoid occurring the phenomenon of back end monitor blank screen, realized the real-time demonstration of vision signal, for the user provides convenience in the application of SDI.

Description of drawings

Fig. 1 is the system block diagram of embodiment of the invention high-definition digital matrix D DR2 storage;

Fig. 2 is that embodiment of the invention DDR2 writes control flow chart;

Fig. 3 is that embodiment of the invention DDR2 reads control flow chart.

Embodiment:

The system block diagram of high-definition digital matrix D DR2 storage is as shown in Figure 1, the SDI vision signal process that front-end camera transmits

A series of processing is transferred to FPGA, writes in the DDR2 memory through processing and the control of FPGA, and the DDR2 of FPGA control simultaneously memory, reading of data from this memory, and be converted into sdi signal and send to back end monitor and show through handling.Concrete process is the switching of SDI vision signal through the switching chip, passes through the signal compensation of cable equalizer EQ again, is transferred to FPGA and imports as video.The sdi signal of serial is converted into parallel vision signal through a series of processing of the SDI IP kernel among the FPGA; Pass through the DDR2 controller among the FPGA again; Vision signal is write among the DDR2, and the DDR2 of DDR2 controller control simultaneously reads out vision signal from DDR2; Export the SDI vision signal of serial again through the processing of SDI IP kernel, pass to outside monitor and show.

Wherein when carrying out video switch; Owing to switching nonsynchronous reason between time spent and the unlike signal, the interruption of a period of time can appear in the video input of FPGA, at this moment; FPGA will detect whether the video input is arranged; If there is not video input, the DDR2 controller among the FPGA can control the DDR2 memory continue the output maximum duration be 2S deposit the complete video image among the DDR2 at last in

Guarantee that video image does not interrupt, thereby avoid occurring the phenomenon of back end monitor blank screen.During through the SDI transmission video signal; In the signal except comprising effective video data; Also comprise some supplementarys; As indicate the SAV EAV that video transmission finishes with sign that video transmission begins, and wherein there are F, V, three parameters of H to be used for indicating the vision signal position among SAV and the EAV, just can know through the variation that detects these three parameters whether the vision signal input is arranged.

It is as shown in Figure 2 that DDR2 writes control flow.Whether wherein FPGA detects always has the video input, and when video was imported, whether what detection DDR2 controller was interior write the FIFO remaining space greater than burst length; If then controller produces the request of writing, and enable signal is write in generation; The video data of input is write writing among the fifo of DDR2 controller; Until writing the data that expired a burst length, send this moment and write the CMD order, in the DDR2 memory, write video data.FPGA judges the size of a two field picture through the form that detects video image; When writing a full frame image data in the DDR2 memory; Said DDR2 controller switches bank, begins to write new data from the first address of next bank, the data that deposit in before overriding; Bring in constant renewal in the data that deposit in like this, guarantee there is the complete view data of two frames among the DDR2 always.

The control procedure of wherein writing a full two field picture is following: sdi signal has multiple form, and the size of a two field picture of different-format is also different.We store two field picture size with the bank of DDR2, are example with 720P60: sdi signal one two field picture of 720P60 form has 750 row, and every row has the data (10bit Y-signal and 10bit C signal) of 1650 20bit.The DDR2 chip of selecting for use in the scheme is k4t1g164qf; Have 13 row addresses, 10 to rank address, 3 bank addresses, data bit is that 3 data can be stored in 16,4 addresses; The required rank addresses of sdi signal of storage one frame 720P60 form adds up to like this: the address of 1650*750*4/3=1650000. each bank is since 1; When the address count down to 1650000, explain that this bank has stored the view data of a frame, write data successively from first address again behind the switching bank.The sdi signal control mode of various forms is consistent, the appearance not of uniform size of a two field picture just, and it is also different to make that each bank stores the address size of a frame.

Wherein Bank switching controls process is following: selected 1,2,3 three bank store data in the DDR2 memory, and each bank stores the image of a frame.For the sdi signal with a kind of form, the image data amount of each frame is fixed, and so just storing a two field picture corresponding to each bank has fixing address space.After having stored a two field picture, address space moves on to the first address of next bank, begins to store the image of next frame, overrides original data, bank1-successively on this bank address simultaneously>bankk2->bank3->bank1 ... Storage in turn.In like manner, the reading of data image also is the same principle from the DDR2 the inside, successively from bank3->bank1->bank2->bank3 ... Read in turn.But when the clock frequency of storage and reading of data is different, store successively again and reading of data after need judging.Judging when storing at every turn and reading current " writing bank " and " reading bank ", is " writing fast " or " reading fast " thereby obtain current states.When " write fast ", need repeat to write a two field picture to current bank, when " reading fast ", repeat to read the view data in the current bank.When guaranteeing that like this read-write frequency is inconsistent, the data of storing at every turn and reading in the ddr2 all are complete two field pictures.

It is as shown in Figure 3 that DDR2 reads control flow.In DDR2, writing has expired a frame image data; Transmission is read CMD and is ordered the controller to DDR2, produces simultaneously and reads enable signal, and reading of data is read fifo to the DDR2 controller from the DDR2 memory; When the DDR2 controller read burst length data are arranged in the fifo time; Controller produces read request and generates and reads to enable, with data from the DDR2 controller read read the fifo, be transferred to back end monitor and show.

Owing to have two frame data all the time among the DDR2, when no video was imported, matrix still can continue dateout and show to back end monitor.When the video input recovered, FPGA write into the DDR2 memory through the DDR2 controller with data again, brought in constant renewal in the data among the DDR2, so just can show up-to-date vision signal again, realized the real-time demonstration of vision signal.

Characteristics of the present invention and effect are in this way, have both realized the continuous demonstration of vision signal, avoid occurring the phenomenon of back end monitor blank screen, have realized the real-time demonstration of vision signal, for the user provides convenience in the application of SDI.

Claims

1. DDR2 storage means that is used for the high-definition digital matrix; Wherein the SDI vision signal that transmits of front-end camera is transferred to FPGA after treatment; Processing and control through FPGA write in the DDR2 memory, the DDR2 of FPGA control simultaneously memory, reading of data from this memory; And be converted into sdi signal and send to back end monitor and show through handling; It is characterized in that: FPGA will detect whether video input is arranged, if there is not the video input, the DDR2 controller among the FPGA can control the DDR2 memory continue the output maximum duration be 2S deposit the complete video image among the DDR2 at last in.

2. storage means according to claim 1 is characterized in that: the process that wherein writes data is when video is imported, and detects whether to write the FIFO remaining space greater than burst length in the said DDR2 controller; If then controller produces the request of writing, and enable signal is write in generation; The video data of input is write writing among the fifo of DDR2 controller; Until writing the data that expired a burst length, send this moment and write the CMD order, in the DDR2 memory, write video data.

3. storage means according to claim 2; It is characterized in that: when writing a full frame image data in the said DDR2 memory; Said DDR2 controller switches bank, begins to write new data from the first address of next bank, the data that deposit in before overriding; Bring in constant renewal in the data that deposit in like this, guarantee there is the complete view data of two frames among the DDR2 always.

4. storage means according to claim 1; It is characterized in that: wherein the process of reading of data is in the DDR2 memory, to write to have expired a frame image data; Transmission is read CMD and is ordered the controller to DDR2, produces simultaneously and reads enable signal, and reading of data is read fifo to the DDR2 controller from the DDR2 memory; When the DDR2 controller read burst length data are arranged in the fifo time; Said DDR2 controller produces read request and generates and reads to enable, with data from the DDR2 controller read read the fifo, be transferred to back end monitor and show.

5. storage means according to claim 2; It is characterized in that: three parameters of F, V, H with among sign video transmission SAV that begins and the EAV that indicates the video transmission end are come instruction video signal position, just can know through the variation that detects these three parameters whether the vision signal input is arranged.

6. according to the described storage means of one of claim 1-5, it is characterized in that: selected 1,2,3 three bank store data in the said DDR2 memory, and each bank stores the image of a frame.

7. DDR2 storage system that is used for the high-definition digital matrix; Comprise front-end camera, FPGA, DDR2 memory and back end monitor; Wherein the SDI vision signal that transmits of front-end camera is transferred to FPGA after treatment; Processing and control through FPGA write in the DDR2 memory, the DDR2 of FPGA control simultaneously memory, reading of data from this memory; And be converted into sdi signal and send to back end monitor and show through handling; It is characterized in that: FPGA will detect whether video input is arranged, if there is not the video input, the DDR2 controller among the FPGA can control the DDR2 memory continue the output maximum duration be 2S deposit the complete video image among the DDR2 at last in.

8. according to DDR2 storage system as claimed in claim 7, it is characterized in that: selected 1,2,3 three bank store data in the said DDR2 memory, and each bank stores the image of a frame.

9. a high-definition digital matrix comprises claim 7 or 8 described DDR2 storage systems.