CN102750244A - Transmitting device and transmitting method of graded buffer direct memory access (DMA) - Google Patents
Transmitting device and transmitting method of graded buffer direct memory access (DMA) Download PDFInfo
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Abstract
The invention is suitable for the field of chip design, and particularly discloses a transmitting device and a transmitting method of graded buffer direct memory access (DMA). When a large amount of data is transmitted to a memory controller, a design method of a direct memory access primary storage control circuit is provided. An uploaded DMA buffer is divided into a large primary buffer and a small front buffer, the primary buffer adopts a single-port memory, and therefore chip area is reduced greatly while transmission stability of data between balanced double data rate (DDR) and a peripheral device is guaranteed.
Description
Technical field
The present invention relates to the chip design field, relate in particular to DMA (Direct Memery Access, the directly memory access) read/writing control method from mass data to DDR (Double Data Rate synchronous dynamic data-carrier store), the Apparatus and system that transmit.
Background technology
In chip design, the mutual process of mass data takes place in the real-time peripheral hardware and the chip system main memory DDR that are usually directed to a big data quantity.Because peripheral hardware passivity and to the constancy of data demand; Accurately controllability with DDR main memory feedback information; In chip design, use a big FIFO (First Input First Output often; FIFO) chip is keeping apart between peripheral data and the DDR response, and sudden in order to level and smooth DDR response, guarantees the harmony of peripheral data transmission.
Existing method often adopts full asynchronous design; The asynchronous data read/writing control method adopts asynchronous FIFO mode to realize usually; Promptly with dual port random access storer (Random Access Memory; RAM) after Gray code conversion is carried out in address, judge that through the distance of judgement address the sky of FIFO is expired state, and with its handshake as cross clock domain.Said method can be isolated by the good treatment cross clock domain, is applicable to the situation of fixed-direction data transmission in enormous quantities, particularly the main selection of full asynchronous process.But when increasing along with chip DDR control end competition complexity, DDR institute feedback data is very inhomogeneous, and FIFO needs that therefore are used to isolate peripheral hardware and DDR are very big, the constancy of the sudden and peripheral hardware demand of could level and smooth well DDR holding.
RAM generally has two kinds of twoport and single port: the RAM of twoport can carry out read operation and write operation simultaneously, shares a slice region of memory, in the content that a port writes, can take out in the identical address read of another port; And the RAM of single port has only a cover read/write address, and some moment can only be accomplished the operation to RAM by equipment, but area has only RAM half the of twoport.
When there is synchronized relation in peripheral hardware clock and DDR control clock; If adopt the method for time-sharing multiplex (TimeDvision Multiplex Accesss); The dual port RAM of this bulk is replaced to single port RAM; Become one of chip design acreage reduction important means, and the starting point of invention is provided at exactly in the DMA data transmission, with the single port RAM replacement solution that dual port RAM encountered problems.
Summary of the invention
In view of this; The purpose of the embodiment of the invention is to provide a kind of DMA two ports FIFO (twoport FIFO) is replaced to single port memory (Spram; Single port RAM) the method for designing and the method for designing of corresponding control logic; When being intended to guarantee that data transmission is stable between balance DDR and the peripheral hardware, dwindle chip area as far as possible.
For solving above technical matters; The technical scheme that the embodiment of the invention provides is: a kind of DMA conveyer of classification buffering; Comprise some peripheral hardware ends, a main control end, a DMA single port host buffer and a host buffer controller and a front buffer and a front buffer controller, wherein:
Said peripheral hardware end is used for directive sending/reception request msg evenly;
Said main control end, transmission/receptions request of the formula response peripheral hardware end that is used to burst out, response is then accomplished in finite time;
Said single port host buffer under the scheduling of said host buffer controller, is used at the uniform velocity request of data and the main control end contradiction of formula between handling of bursting out of level and smooth peripheral hardware end, and when normal operating condition, said peripheral hardware end can directly be visited said single port host buffer; When data volume reaches pre-set threshold value in the said single port host buffer, start DMA access request to said main control end by said host buffer controller;
Said front buffer under the scheduling of said front buffer controller, is used for when said main control end responds the DMA request of said peripheral hardware end, starting said front buffer and admitting the request of said peripheral hardware end data sent.
More excellent ground; Said front buffer can be accomplished the gap location that the DMA request response and the said peripheral hardware end of said peripheral hardware end are visited said single port host buffer in said main control end; The content of said front buffer is progressively moved in the said single port main buffering region, be merged into a complete data volume.
More excellent ground, said single port host buffer can before said peripheral hardware end is initiated the DMA request, be moved the partial data in the said single port host buffer in the said front buffer when the request of peripheral hardware end is read request in advance.
More excellent ground, said front buffer is single port RAM.
More excellent ground, said front buffer is a dual port RAM.
The embodiment of the invention also provides a kind of DMA transfer approach of classification buffering, comprising:
The peripheral hardware end is directive sending/reception request msg evenly;
Burst out transmission/receptions request of formula response peripheral hardware end of main control end, response is then accomplished in finite time;
The single port host buffer under the scheduling of host buffer controller, at the uniform velocity request of data and the main control end contradiction between the formula processing of bursting out of level and smooth peripheral hardware end, wherein: when normal operating condition, the peripheral hardware end is directly visited the single port host buffer; When data volume reached pre-set threshold value in the single port host buffer, the host buffer controller started the DMA access request to main control end;
Front buffer when main control end responds the DMA request of said peripheral hardware end, starts front buffer and admits the request of peripheral hardware end data sent under the scheduling of front buffer controller.
More excellent ground, front buffer is accomplished the DMA request response of peripheral hardware end and the gap location of peripheral hardware end visit single port host buffer in main control end, and the content of front buffer is progressively moved in the single port main buffering region, is merged into a complete data volume.
More excellent ground when the single port host buffer is read request in the request of peripheral hardware end, before the peripheral hardware end is initiated the DMA request, is moved the partial data in the single port host buffer in the front buffer in advance.
More excellent ground, according to the peripheral hardware end at the uniform velocity burst out contradiction peak value between the formula processing of request of data and main control end confirm the visit degree of depth of single port host buffer.
The visit degree of depth of front buffer is confirmed according to burst out formula response time, peripheral hardware end request data quantity summation and the peak value of the ratio of peripheral hardware end data access frequency of main control end in more excellent ground.
Compared with prior art; When the embodiment of the invention provides a kind of mass data to transmit toward Memory Controller Hub; A kind of method for designing of dma control circuit splits into big host buffer and very little front buffer through uploading DMA buffering buffer, and host buffer is used single port memory; Be able to reduce significantly chip area, and guarantee the stable of data transmission between balance DDR and the peripheral hardware.
Description of drawings
Fig. 1 is the control signal synoptic diagram of existing DMA conveyer;
Fig. 2 is the theory diagram of DMA conveyer one embodiment of classification buffering of the present invention;
Fig. 3 is the control signal synoptic diagram among Fig. 2;
Fig. 4 is the sequential chart of DMA transfer approach one embodiment of classification buffering of the present invention.
Embodiment
Core of the present invention is to split into host buffer and very little front buffer with uploading DMA buffer (buffering); Host buffer is with single port memory (storer), thereby is able to guaranteeing between balance DDR and the peripheral hardware that data transmission reduces chip area in stable significantly.
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Referring to Fig. 1, be the control signal synoptic diagram of existing DMA conveyer, the DDR of its main control end is owing to be that multithreading is handled; Always be in busy condition; For the request of CPU visit DDR or miscellaneous equipment visit DDR, can not be in time corresponding, in case but respond then in finite time, accomplish Request Processing.Sudden for level and smooth DDR response guarantees the harmony of peripheral data transmission be provided with big twoport DMA buffer, thereby chip area to be bigger.
In this scheme; Twoport DMA buffe relates to Read_clk (reading clock), Read_en (reading to enable), Read_addr (reading the address), Read_data (read data); And Write_clk (writing clock), Write_en (write and enable), Write_addr (write address), Write_data control signals such as (write datas); They are by buffer control unit (scheming not shown) uniform dispatching, and the frequency of read signal is greater than the frequency of write signal (Freq_rclk＞Freq_wclk).
Different with it, the present invention will upload DMA buffer and split into very big host buffer and very little front buffer, and wherein host buffer is used single port memory, thereby can effectively dwindle chip area.
Referring to Fig. 2, express an embodiment of the DMA conveyer of classification buffering of the present invention.This DMA that is used for the big data quantity transmission sends and control device embodiment realizes like this; It mainly comprises following components: at the uniform velocity data initiation/reception peripheral hardware end 200, the formula that bursts out Data Receiving/transmission main control end 400, DMA single port host buffer 200 and parts such as host buffer controller 100, front buffer 500 and front buffer controller 600, wherein:
Data initiation/reception peripheral hardware end 200 at the uniform velocity, directed endlessly to main control end 400 transmission/request msgs.Because peripheral hardware end 200 is to compare main control end 400 speed more at the uniform velocity to initiate request of data; And main control end 400 is owing to be that multithreading is handled and always is in busy condition; Therefore the request to certain peripheral hardware can not in time respond, in case but response then in finite time completion to the Request Processing of peripheral hardware end 200.
For this reason, (single port RAM spram) then is used for the contradiction that bursts out and handle of at the uniform velocity request of data and master control of level and smooth peripheral hardware to single port host buffer 300.The visit degree of depth of the spram of this single port host buffer 300 is selected according to the peak value of contradiction between peripheral hardware in the reality and the master control.
Single port host buffer 300 work under 100 scheduling of host buffer controller; Its steering logic is: when normal operation; When perhaps the master control of not burst out of the read-write control signal of single port host buffer 300 was shared, peripheral hardware end 200 had the direct access right to single port host buffer 300; When the data volume in the single port host buffer 300 reaches certain preset threshold, the DMA access request that DMA host buffer controller 100 starts main control end 400.
When the DMA of main control end 400 response peripheral hardware ends asks, with the access rights of the spram that occupies single port host buffer 300 fully.And at this moment in order to prevent the loss of data of external unit transmission/request, start front buffer 500 and be used to admit the 200 data sent requests of peripheral hardware end.
When main control end 400 is accomplished the DMA request response to peripheral hardware end 200; Peripheral hardware end 200 recovers the access control power to the spram of host buffer 300; But because peripheral hardware end 200 also has the partial data request to be deposited with in the front buffer 500; Therefore at the gap location of peripheral hardware end 200 visit spram, the content of front buffer 500 will progressively be moved single port host buffer 200, be merged into a complete data volume.
When peripheral hardware end 200 request of data are read request; Before peripheral hardware end 200 is initiated the DMA request,, move in advance in the front buffer 500 single port host buffer 300 partial data; In the time of can guaranteeing 300 visits of 400 pairs of single port host buffers of main control end, offer peripheral data by front buffer 500.
The degree of depth in front buffer district 500 is by the burst out peak value decision of summation and peripheral data access frequency ratio of data volume of formula response time, peripheral hardware request of master control.And front buffer 500 is very little owing to the degree of depth, and no matter adopting single port RAM still is that dual port RAM can.And use dual port RAM can simplify the steering logic of front buffer 500, but not very big to area effect.
Referring to Fig. 3; For single port DMA buffe in the scheme shown in Figure 2 relates to control signal; Comprise Write_bus (write bus), CLK (clock), Wen (write and enable), Wdata (write data), Waddr (write address) etc., they are by host buffer controller 100 uniform dispatching.Likewise, the frequency of read signal is greater than the frequency of write signal (Freq_rclk＞Freq_wclk).
Relate to two paths among Fig. 3: article one is represented " DDR does not visit big DMA buffer ", and promptly peripheral hardware can directly be write and lead among the big buffer; The upper left corner in second path is provided with one " not gate ", expression " DDR is just visiting big DMA buffe ", and promptly peripheral hardware must be write front buffer and gets on, and this is a key point of the present invention.
On aforementioned basis, describe in the face of the DMA transfer approach of classification buffering of the present invention down.
Referring to Fig. 4, represent the sequential of the DMA transfer approach of classification buffering of the present invention, its detailed process is:
The peripheral hardware end is directive sending/reception request msg (process 1) evenly;
When main control end is nonbusy condition, burst out transmission/receptions request of formula response peripheral hardware end of main control end, the completion (process 6) in finite time of response back;
When main control end is busy condition, the single port host buffer under the scheduling of host buffer controller, at the uniform velocity request of data and the main control end contradiction between the formula processing of bursting out of level and smooth peripheral hardware end, wherein:
When normal operating condition, the peripheral hardware end is directly visited single port host buffer (process 3);
When data volume reached pre-set threshold value in the single port host buffer, the host buffer controller started the DMA access request (process 5) to main control end;
Front buffer when main control end responds the DMA request of said peripheral hardware end, starts front buffer and admits peripheral hardware end data sent request (process 7) under the scheduling of front buffer controller.
Simultaneously, front buffer is accomplished the DMA request response of peripheral hardware end and the gap location of peripheral hardware end visit single port host buffer in main control end, and the content of front buffer is progressively moved in the single port main buffering region, is merged into a complete data volume (process 8).
Especially,,, the request of peripheral hardware end before the peripheral hardware end is initiated the DMA request, the partial data in the single port host buffer is moved in the front buffer in advance when being read request at the single port host buffer.
In this transfer approach, according to the peripheral hardware end at the uniform velocity request of data and the main control end contradiction peak value of formula between handling that burst out confirm the visit degree of depth of single port host buffer; Simultaneously, confirm the visit degree of depth of front buffer according to burst out formula response time, peripheral hardware end request data quantity summation and the peak value of the ratio of peripheral hardware end data access frequency of main control end.
Above embodiment splits into big host buffer and very little front buffer through uploading DMA buffering buffer, and host buffer use single port memory, thereby is able to reduce significantly chip area, and the stablizing of data transmission between assurance balance DDR and the peripheral hardware.
Below be of the present invention one concrete application example, briefly be described below.
Application example
The peripheral hardware terminal is camera (video camera) camera, when recording DV, basically based on the clock about 40M; Continue in DDR, to send into image data; Carry out the video coding by CPU again, be transferred in the SD card (safe digital card) and store, carry out image preview on the lcd screen simultaneously.
The controller of Camera and DDR controller are operated in same frequency 120M, and just in time 3 cycles are seen a picture element off by the camera controller.
Because lcd screen is to obtain data presentation endlessly, so the DMA priority of LCD is the highest, the DMA request of DDR preferential answering LCD.For improving DMA efficient, each equipment DMA application all is 256 bytes at every turn.
Through the statistical estimation of system, it is 2048 data buffering that the dma controller of camera needs the degree of depth, and the burst work when could the level and smooth system in devoid of risk ground busy causes in time responding the DMA request of camera.Otherwise the overflow status of writing of camera data buffering takes place easily.
Owing to be continuation address visit, the DDR controller is served the data access of 256 bytes at every turn, needs 54 cycles, adds the expense of control signal, wants 60 seeervice cycles altogether.In a single day promptly when camera initiated the DMA request, it is uncertain what begins to obtain the real response time, but obtain service response, will in 60 cycles, accomplish service at most, and DDR just discharges the read-write of DMA single port host buffer is controlled after accomplishing.
And within this 60 cycles, the data of nearly 20 pixels need buffering, consider that the frequency ratio of DDR controller clock and camera data acquisition clock possibly change, and for the purpose of therefore guarding, the size in front buffer district is 32 pixels.
When initial, per 3 cycles of camera are write a pixel (describe for simplifying, think that here a pixel is exactly a byte, have only brightness one road component, two components of colourity are described and ignored) in this literary composition toward big buffer the inside.And this moment, front buffer was in idle condition.
When the write address of big buffer reached 256, CC (camera controller, camera control unit) started the DMA request and uploads data.Because DDRC (DDR controller, DDR controller) is in busy condition always, when CC obtained DMA request affirmation, the write address of big buffer had arrived 280.
After CC obtained DMA request affirmation, the read-write control of big buffer was by give DDRC fully, and this moment, CC latched CC to the write address of big buffer, and started the front buffer district simultaneously.
At the DMA request viability of DDRC to CC, CC continues on the address of address 281,282,283, to write data, and only there is a notional offset address 280 address this moment 0 in front buffer district, the state when promptly the bigbuffer control is transferred.
When CC had altogether toward 300 addresses, preposition buffer write road, DDRC had accomplished the DMA services request of CC---and 256 bytes among the big buffer are all read away, and discharged the control of big buffer.When CC continued in big buffer, to insert next data, the address of filling was 301, increased successively later on.
Because average 3 cycles of CC are inserted 1 picture element toward big buffer, so in fact big buffer also has time of 2/3 to be in the free time.So content of 20 picture elements in the front buffer; Can be before CC writes new data on 311 addresses; Utilize the gap that these data are moved 280～299 the address space of big buffer fully, accomplish move after, the front buffer district gets into idle condition once more.
When next time, CC initiated new DMA request, address 256～511 space content among the big buffer were continuous content, and similarly action goes round and begins again.
Only be preferred implementation of the present invention below, should be pointed out that above-mentioned preferred implementation should not be regarded as limitation of the present invention, protection scope of the present invention should be as the criterion with claim institute restricted portion.For those skilled in the art, do not breaking away from the spirit and scope of the present invention, can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (10)
1. the DMA conveyer of a classification buffering is characterized in that, comprises some peripheral hardware ends, a main control end, a DMA single port host buffer and a host buffer controller and a front buffer and a front buffer controller, wherein:
Said peripheral hardware end is used for directive sending/reception request msg evenly;
Said main control end, transmission/receptions request of the formula response peripheral hardware end that is used to burst out, response is then accomplished in finite time;
Said single port host buffer under the scheduling of said host buffer controller, is used at the uniform velocity request of data and the main control end contradiction of formula between handling of bursting out of level and smooth peripheral hardware end, and when normal operating condition, said peripheral hardware end can directly be visited said single port host buffer; When data volume reaches pre-set threshold value in the said single port host buffer, start DMA access request to said main control end by said host buffer controller;
Said front buffer under the scheduling of said front buffer controller, is used for when said main control end responds the DMA request of said peripheral hardware end, starting said front buffer and admitting the request of said peripheral hardware end data sent.
2. the DMA conveyer of classification buffering as claimed in claim 1; It is characterized in that; Said front buffer can be accomplished the gap location that the DMA request response and the said peripheral hardware end of said peripheral hardware end are visited said single port host buffer in said main control end; The content of said front buffer is progressively moved in the said single port main buffering region, be merged into a complete data volume.
3. the DMA conveyer of classification buffering as claimed in claim 1; It is characterized in that; Said single port host buffer can before said peripheral hardware end is initiated the DMA request, be moved the partial data in the said single port host buffer in the said front buffer when the request of peripheral hardware end is read request in advance.
4. like the DMA conveyer of claim 1,2 or 3 described classification bufferings, it is characterized in that said front buffer is single port RAM.
5. like the DMA conveyer of claim 1,2 or 3 described classification bufferings, it is characterized in that said front buffer is a dual port RAM.
6. the DMA transfer approach of a classification buffering is characterized in that, comprising:
The peripheral hardware end is directive sending/reception request msg evenly;
Burst out transmission/receptions request of formula response peripheral hardware end of main control end, response is then accomplished in finite time;
The single port host buffer under the scheduling of host buffer controller, at the uniform velocity request of data and the main control end contradiction between the formula processing of bursting out of level and smooth peripheral hardware end, wherein: when normal operating condition, the peripheral hardware end is directly visited the single port host buffer; When data volume reached pre-set threshold value in the single port host buffer, the host buffer controller started the DMA access request to main control end;
Front buffer when main control end responds the DMA request of said peripheral hardware end, starts front buffer and admits the request of peripheral hardware end data sent under the scheduling of front buffer controller.
7. the DMA transfer approach of classification buffering as claimed in claim 6; It is characterized in that; Front buffer is accomplished the DMA request response of peripheral hardware end and the gap location of peripheral hardware end visit single port host buffer in main control end; The content of front buffer is progressively moved in the single port main buffering region, be merged into a complete data volume.
8. the DMA transfer approach of classification buffering as claimed in claim 6 is characterized in that, when the single port host buffer is read request in the request of peripheral hardware end, before the peripheral hardware end is initiated the DMA request, the partial data in the single port host buffer is moved in the front buffer in advance.
9. like the DMA transfer approach of claim 6,7 or 8 described classifications buffering, it is characterized in that, according to the peripheral hardware end at the uniform velocity burst out contradiction peak value between the formula processing of request of data and main control end confirm the visit degree of depth of single port host buffer.
10. like the DMA transfer approach of claim 6,7 or 8 described classifications buffering, it is characterized in that, confirm the visit degree of depth of front buffer according to burst out formula response time, peripheral hardware end request data quantity summation and the peak value of the ratio of peripheral hardware end data access frequency of main control end.
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| US9563572B2 (en) | 2014-12-10 | 2017-02-07 | International Business Machines Corporation | Migrating buffer for direct memory access in a computer system |
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