CN104125424A - FPGA (Field Programmable Gate Array) high-speed variable-frame video memory design method - Google Patents
FPGA (Field Programmable Gate Array) high-speed variable-frame video memory design method Download PDFInfo
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array) high-speed variable-frame video memory design method. The method comprises the following steps: starting to send video source data through a video source end; initializing a DDR (Double Data Rate) storage; receiving the data through the front-end asynchronous FIFO (First In First Out); writing the data of the front-end asynchronous FIFO in the DDR storage while the data size cached by the front-end asynchronous FIFO reaches a threshold; reading data to a rear-end asynchronous FIFO through the DDR storage while the data stored in the DDR storage reaches a frame; starting a dot-screen module to send the data into a screen while the data size in the rear-end asynchronous FIFO reaches the threshold, wherein the storage address space in the DDR storage is divided into three areas according to the size of a single-frame image, wherein the three areas are respectively marked as A, B and C; operating a DDR controller to control the read-write operation of the DDR storage to be alternatively performed once among the areas A, B and C. The method has the advantages that various video signals can be flexibly processed, like caching, efficient transmission and frame varying.
Description
Technical field
The present invention relates to a kind of high speed, variable frame video video memory method for designing based on FPGA.
Background technology
Field programmable logic device FPGA is with its processing speed at a high speed, design has been widely used in various engineering designs flexibly, and DDR memory is as the functional module under FPGA platform, rely on its disposal ability at a high speed to make it in video video memory solution, obtain significant progress.Along with the high speed development of electronic technology, the function of display device is more and more diversified, the amount of information of transmission is also increasing, video video memory design in the past is all difficult to nowadays diversified functional requirement of reply, and FPGA with its at a high speed, design flexibly, just catering to this development need.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of high speed, variable frame video video memory method for designing based on FPGA is provided, this method for designing controls by DDR controller buffer memory, transmission and the processing of change frame that DDR memory completes video, can carry out high efficiency of transmission and become the processing flexibly such as frame the various vision signals in DDR limited memory bandwidth.
The present invention is achieved by the following technical solutions:
High speed based on FPGA, a variable frame video video memory method for designing, comprise the steps:
A, utilize field programmable logic device FPGA that video source and screen are coupled together, wherein in PFGA, be provided with DDR memory, control the DDR controller of DDR memory and connect respectively front end asynchronous FIFO and the rear end asynchronous FIFO of DDR memory input and output;
B, video source start to send video source data, carry out the operation of DDR initialize memory simultaneously;
After C, DDR initialize memory complete, DDR memory starts to detect the frame head of video source data, enters in front end asynchronous FIFO when starting receiver, video source data after the frame head of finding a certain frame;
D, start to send handshake notice DDR controller carry out data and read after the data volume of front end asynchronous FIFO buffer memory arrives threshold value, wherein the threshold value of front end asynchronous FIFO is the amount of reading and writing data of DDR memory single burst;
E, DDR memory start from front end asynchronous FIFO, to read and data writing after receiving handshake, and the memory address space of DDR memory inside is divided into three regions by single-frame images size and is designated as respectively A, B, C, and every region is a two field picture size; When starting read operation after the data of judging DDR memory and received a frame, the data of reading are sent into buffer memory in the asynchronous FIFO of rear end; Read-write operation single between A, B, tri-regions of C by DDR controller control DDR memory hockets, and carrys out the volume of transmitted data of balance front and back end by the number of times of DDR memory read and write in the co-ordination unit time;
F, when the data volume of rear end asynchronous FIFO buffer memory arrives after threshold value, start-up point panel module takes out data and sends to screen from the asynchronous FIFO of rear end, the threshold value of rear end asynchronous FIFO is the amount of reading and writing data of DDR memory single burst; Wherein, the speed that reads the arbitrary address space two field picture of A, B, C of DDR memory is that the some screen data rate of delivery of sending into screen according to aft terminal panel module decides, the frame per second higher or lower than front end video source by DDR controller control point screen frame per second as required;
Said method need be followed: a video source volume of transmitted data per second+panel module is sent into screen volume of transmitted data <DDR memory per second actual processing bandwidth per second, and the video source DDR of entering memory data per second amount and the DDR of reading memory data amount per second can not exceed respectively the half of DDR memory disposal ability per second.
As the preferred implementation of technique scheme, described step e, in F, in the time selecting to improve some screen frame per second, DDR memory data reading speed can be faster than writing speed, in the time that the first frame data enter DDR memory, first write A address space, when A address space writes after frame data, start the second frame data that arrive to write B address space, at this moment the view data in A address space can be read and be sent into holding point panel module in the asynchronous FIFO of rear end and send into screen, when A address space has read a two field picture, and B address space is not also write while expiring frame data, again transferring these frame data from A address space sends, repeat as required this process repeatedly, until having write the second frame, B address space enters image, if B address space has write the second frame and entered image, and A address space does not also run through frame data, at this moment A address space is also occupied, and B address space has just write the data of present frame, and at this moment the data of video source will start to write C address space, and run through after these frame data when A address space, detect that B address space has write frame data, and then jump to B address space and carry out data and read, at this moment just formed the state that B reads, C writes, this equates that A reads, B writes fashionable state, so circulation can reach an effect that improves some screen frame per second.
As the preferred implementation of technique scheme, in described step e, F, in the time selecting to reduce some screen frame per second, need to write fashionable elder generation at DDR memory A and B address space have been write respectively to frame data, and then when writing C address space, start to carry out the read operation of the first frame from A address space, preferentially wait for that A address space runs through after a frame redirect, write and just jump to A address space and carry out; Now start the read operation of B address space the second frame, preferentially wait for that B address space runs through after a frame redirect, write and just jump to B address space and carry out; Now start the read operation of C address space the 3rd frame, preferentially wait for that C address space runs through after a frame redirect, write and just jump to C address space and carry out, so circulation can reach an effect that reduces some screen frame per second.
As the preferred implementation of technique scheme, in described step e, DDR memory there will be four kinds of possible situations: (1) does not reach threshold value when the storage of front end asynchronous FIFO data, rear end asynchronous FIFO data storage reaches threshold value, at this moment DDR memory does not need to carry out read-write operation, is idle period; (2) when the storage of front end asynchronous FIFO data reaches threshold value, and rear end asynchronous FIFO data storage also reaches threshold value, and at this moment DDR memory only need to carry out write operation; (3) when the storage of front end asynchronous FIFO data does not reach threshold value, rear end asynchronous FIFO storage does not reach threshold value yet, and at this moment DDR memory only need to carry out read operation; (4) when the storage of front end asynchronous FIFO data reaches threshold value, rear end asynchronous FIFO does not reach threshold value, is at this moment DDR memory peak busy hour, and read and write all needs to operate; Now DDR controller control DDR memory is taked to read and write the mode that single hockets and is coordinated, until jump out this busy condition.
As the preferred implementation of technique scheme, in described step e, A, B in DDR memory, tri-regions of C are three independent address spaces or three continuation address spaces.
As the preferred implementation of technique scheme, what described DDR memory read that band is wider than a panel module send screen bandwidth, in the time occurring that rear end asynchronous FIFO is fast full, DDR controller control DDR memory stops read operation holding point panel module the data in the asynchronous FIFO of rear end is passed out to screen, thereby reaches dynamic equilibrium.
The present invention has the following advantages compared to existing technology:
(1) DDR controller provides simple video frame rate translation function, can realize in DDR memory effective bandwidth high frame per second and transfer the video output that low frame per second or low frame per second transfer high frame per second to.
(2) be respectively arranged with front end asynchronous FIFO and rear end asynchronous FIFO in DDR memory front-end and back-end, make input clock and the output clock of FIFO can be completely asynchronous, there is inconsistent situation with the speed of DDR memory data writing stream in the video source data stream sending due to video source, coordinates to ensure that by front end asynchronous FIFO front end data can not lose because of the operating process of DDR memory; Equally, rear end asynchronous FIFO is the data volume relation between screen bandwidth of sending that reads bandwidth and some panel module in order to coordinate DDR memory; So that whole process reaches stable dynamic equilibrium, simultaneously for DDR memory provides data-interface flexibly.
(3) in this method, a video source volume of transmitted data per second+panel module is sent into screen volume of transmitted data <DDR memory per second actual processing bandwidth per second, and the video source DDR of entering memory data per second amount and the DDR of reading memory data amount per second can not exceed respectively the half of DDR memory disposal ability per second, and the threshold value that front end asynchronous FIFO and rear end asynchronous FIFO is all provided with to lower limit, has effectively prevented that front end asynchronous FIFO from occurring that spill-over goes out and prevented that rear end asynchronous FIFO from occurring that sky overflows.
(4) hocket by read-write operation single between A, B, tri-regions of C of DDR controller control DDR memory, carry out the volume of transmitted data of balance front and back end by the number of times of DDR memory read and write in the co-ordination unit time, thereby ensured the stable transfer of data, and DDR memory transfer speed is high.
Brief description of the drawings
Fig. 1 is video video memory method for designing flow chart of the present invention.
Fig. 2 is video video memory design frame chart of the present invention.
Embodiment
Below embodiments of the invention are elaborated, the present embodiment is implemented under taking technical solution of the present invention as prerequisite, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Refer to Fig. 1, Fig. 2, a kind of high speed, variable frame video video memory method for designing based on FPGA that the present embodiment provides, comprises the steps:
A, utilize field programmable logic device FPGA that video source and screen are coupled together, wherein in PFGA, be provided with DDR memory, control the DDR controller of DDR memory and connect respectively front end asynchronous FIFO and the rear end asynchronous FIFO of DDR memory input and output;
B, video source start to send video source data, carry out the operation of DDR initialize memory simultaneously;
C, DDR memory need to be configured and the sequence of operations such as verification in the time powering on, this is by the operating time taking more than general 200us, by the time after DDR initialize memory completes, DDR memory starts to detect the frame head of video source data, enters in front end asynchronous FIFO when starting receiver, video source data after the frame head of finding a certain frame;
D, after the data volume of front end asynchronous FIFO buffer memory arrives threshold value, start to send handshake notice DDR controller and carry out data and read, because DDR memory read data speed wants fast with respect to video source enters the speed of data, therefore need to arrange the threshold value of a storage lower limit to front end asynchronous FIFO, ensure that front end asynchronous FIFO can not overflow by sky, wherein the threshold value of front end asynchronous FIFO is the amount of reading and writing data of DDR memory single burst;
E, DDR memory start from front end asynchronous FIFO, to read and data writing after receiving handshake, and the memory address space of DDR memory inside is divided into three regions by single-frame images size and is designated as respectively A, B, C, and every region is a two field picture size; When starting read operation after the data of judging DDR memory and received a frame, the data of reading are sent into buffer memory in the asynchronous FIFO of rear end; Read-write operation single between A, B, tri-regions of C by DDR controller control DDR memory hockets, and carrys out the volume of transmitted data of balance front and back end by the number of times of DDR memory read and write in the co-ordination unit time;
F, when the data volume of rear end asynchronous FIFO buffer memory arrives after threshold value, start-up point panel module takes out data and sends to screen from the asynchronous FIFO of rear end, the threshold value of rear end asynchronous FIFO is the amount of reading and writing data of DDR memory single burst; Wherein, the speed that reads the arbitrary address space two field picture of A, B, C of DDR memory is that the some screen data rate of delivery of sending into screen according to aft terminal panel module decides, the frame per second higher or lower than front end video source by DDR controller control point screen frame per second as required;
In said method, need to follow: a video source volume of transmitted data per second+panel module is sent into screen volume of transmitted data <DDR memory per second actual processing bandwidth per second, and the video source DDR of entering memory data per second amount and the DDR of reading memory data amount per second can not exceed respectively the half of DDR memory disposal ability per second, this is in order to prevent that front end asynchronous FIFO from occurring that spill-over goes out and prevents that rear end asynchronous FIFO from occurring that sky overflows.
Wherein, step e, in F, in the time selecting to improve some screen frame per second, DDR memory data reading speed can be faster than writing speed, in the time that the first frame data enter DDR memory, first write A address space, when A address space writes after frame data, start the second frame data that arrive to write B address space, at this moment the view data in A address space can be read and be sent into holding point panel module in the asynchronous FIFO of rear end and send into screen, when A address space has read a two field picture, when probably B address space is not also write full frame data, at this moment can again transfer these frame data from A address space sends, repeat as required this process repeatedly, this is relevant with the ratio of carrying frame, and because the ratio of carrying frame may not be ratio of integers, for example mention 60 frames from 25 frames, when this will cause B address space to write the second frame entering image, A address space does not also run through frame data, at this moment A address space is also occupied, and B address space has just write the data of present frame, therefore need to open up C address space and coordinate this relation, at this moment the data of video source will start to write C address space, and run through after these frame data when A address space, detect that B address space has write frame data, and then jump to B address space and carry out data and read, at this moment just formed the state that B reads, C writes, this equates that A reads, B writes fashionable state, so circulation can reach an effect that improves some screen frame per second.
Wherein, in step e, F, in the time selecting to reduce some screen frame per second, DDR memory data reading speed can be slower than writing speed, need to write and fashionablely first A and B address space write respectively to frame data at DDR memory, and then when writing C address space, the read operation of the first frame be carried out in beginning from A address space, preferential wait for that A address space runs through after a frame redirect, write and just jump to A address space and carry out; Now start the read operation of B address space the second frame, preferentially wait for that B address space runs through after a frame redirect, write and just jump to B address space and carry out; Now start the read operation of C address space the 3rd frame, preferentially wait for that C address space runs through after a frame redirect, write and just jump to C address space and carry out, so circulation can reach an effect that reduces some screen frame per second.
In step e, A, B in DDR memory, tri-regions of C can be three continuation address spaces, can be also three independently address spaces.Address space is relatively saved in continuation address space, improve the utilance of memory space, but in program, the initial address in three regions need to calculate, and be fixed position, and inheritance is not strong; And but although independent address space is convenient to amendment is relatively taken address space, inapplicable for the DDR memory that memory space is less; Therefore can select voluntarily according to the memory space of DDR memory.In running, DDR memory there will be four kinds of possible situations: (1) does not reach threshold value when the storage of front end asynchronous FIFO data, rear end asynchronous FIFO data storage reaches threshold value, and at this moment DDR memory does not need to carry out read-write operation, is idle period; (2) when the storage of front end asynchronous FIFO data reaches threshold value, and rear end asynchronous FIFO data storage also reaches threshold value, and at this moment DDR memory only need to carry out write operation; (3) when the storage of front end asynchronous FIFO data does not reach threshold value, rear end asynchronous FIFO storage does not reach threshold value yet, and at this moment DDR memory only need to carry out read operation; (4) when the storage of front end asynchronous FIFO data reaches threshold value, rear end asynchronous FIFO does not reach threshold value, is at this moment DDR memory peak busy hour, and read and write all needs to operate; Now DDR controller control DDR memory is taked to read and write the mode that single hockets and is coordinated, until jump out this busy condition.
In step F, rear end asynchronous FIFO is also the data volume relation between screen bandwidth of sending that reads bandwidth and some panel module in order to coordinate DDR memory.What DDR memory read that band is wider than a panel module send screen bandwidth, the situation that does not have data to send in the asynchronous FIFO of rear end while sending screen in order to prevent a panel module, in the time occurring that rear end asynchronous FIFO is fast full, DDR controller control DDR memory stops read operation holding point panel module the data in the asynchronous FIFO of rear end is passed out to screen, thereby reaches dynamic equilibrium.
These are only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (6)
1. the high speed based on FPGA, a variable frame video video memory method for designing, is characterized in that, comprises the steps:
A, utilize field programmable logic device FPGA that video source and screen are coupled together, wherein in PFGA, be provided with DDR memory, control the DDR controller of DDR memory and connect respectively front end asynchronous FIFO and the rear end asynchronous FIFO of DDR memory input and output;
B, video source start to send video source data, carry out the operation of DDR initialize memory simultaneously;
After C, DDR initialize memory complete, DDR memory starts to detect the frame head of video source data, enters in front end asynchronous FIFO when starting receiver, video source data after the frame head of finding a certain frame;
D, start to send handshake notice DDR controller carry out data and read after the data volume of front end asynchronous FIFO buffer memory arrives threshold value, wherein the threshold value of front end asynchronous FIFO is the amount of reading and writing data of DDR memory single burst;
E, DDR memory start from front end asynchronous FIFO, to read and data writing after receiving handshake, and the memory address space of DDR memory inside is divided into three regions by single-frame images size and is designated as respectively A, B, C, and every region is a two field picture size; When starting read operation after the data of judging DDR memory and received a frame, the data of reading are sent into buffer memory in the asynchronous FIFO of rear end; Read-write operation single between A, B, tri-regions of C by DDR controller control DDR memory hockets, and carrys out the volume of transmitted data of balance front and back end by the number of times of DDR memory read and write in the co-ordination unit time;
F, when the data volume of rear end asynchronous FIFO buffer memory arrives after threshold value, start-up point panel module takes out data and sends to screen from the asynchronous FIFO of rear end, the threshold value of rear end asynchronous FIFO is the amount of reading and writing data of DDR memory single burst; Wherein, the speed that reads the arbitrary address space two field picture of A, B, C of DDR memory is that the some screen data rate of delivery of sending into screen according to aft terminal panel module decides, the frame per second higher or lower than front end video source by DDR controller control point screen frame per second as required;
Said method need be followed: a video source volume of transmitted data per second+panel module is sent into screen volume of transmitted data <DDR memory per second actual processing bandwidth per second, and the video source DDR of entering memory data per second amount and the DDR of reading memory data amount per second can not exceed respectively the half of DDR memory disposal ability per second.
2. a kind of high speed based on FPGA as claimed in claim 1, variable frame video video memory method for designing, it is characterized in that, described step e, in F, in the time selecting to improve some screen frame per second, DDR memory data reading speed can be faster than writing speed, in the time that the first frame data enter DDR memory, first write A address space, when A address space writes after frame data, start the second frame data that arrive to write B address space, at this moment the view data in A address space can be read and be sent into holding point panel module in the asynchronous FIFO of rear end and send into screen, when A address space has read a two field picture, and B address space is not also write while expiring frame data, again transferring these frame data from A address space sends, repeat as required this process repeatedly, until having write the second frame, B address space enters image, if B address space has write the second frame and entered image, and A address space does not also run through frame data, at this moment A address space is also occupied, and B address space has just write the data of present frame, and at this moment the data of video source will start to write C address space, and run through after these frame data when A address space, detect that B address space has write frame data, and then jump to B address space and carry out data and read, at this moment just formed the state that B reads, C writes, this equates that A reads, B writes fashionable state, so circulation can reach an effect that improves some screen frame per second.
3. a kind of high speed, variable frame video video memory method for designing based on FPGA as claimed in claim 1, it is characterized in that, in described step e, F, in the time selecting to reduce some screen frame per second, need to write and fashionablely first A and B address space write respectively to frame data at DDR memory, and then when writing C address space, the read operation of the first frame be carried out in beginning from A address space, preferential wait for that A address space runs through after a frame redirect, write and just jump to A address space and carry out; Now start the read operation of B address space the second frame, preferentially wait for that B address space runs through after a frame redirect, write and just jump to B address space and carry out; Now start the read operation of C address space the 3rd frame, preferentially wait for that C address space runs through after a frame redirect, write and just jump to C address space and carry out, so circulation can reach an effect that reduces some screen frame per second.
4. a kind of high speed, the variable frame video video memory method for designing based on FPGA as described in as arbitrary in claims 1 to 3, it is characterized in that, in described step e, DDR memory there will be four kinds of possible situations: (1) does not reach threshold value when the storage of front end asynchronous FIFO data, rear end asynchronous FIFO data storage reaches threshold value, at this moment DDR memory does not need to carry out read-write operation, is idle period; (2) when the storage of front end asynchronous FIFO data reaches threshold value, and rear end asynchronous FIFO data storage also reaches threshold value, and at this moment DDR memory only need to carry out write operation; (3) when the storage of front end asynchronous FIFO data does not reach threshold value, rear end asynchronous FIFO storage does not reach threshold value yet, and at this moment DDR memory only need to carry out read operation; (4) when the storage of front end asynchronous FIFO data reaches threshold value, rear end asynchronous FIFO does not reach threshold value, is at this moment DDR memory peak busy hour, and read and write all needs to operate; Now DDR controller control DDR memory is taked to read and write the mode that single hockets and is coordinated, until jump out this busy condition.
5. a kind of high speed, variable frame video video memory method for designing based on FPGA as claimed in claim 4, is characterized in that, in described step e, A, B in DDR memory, tri-regions of C are three independent address spaces or three continuation address spaces.
6. a kind of high speed, variable frame video video memory method for designing based on FPGA as claimed in claim 5, it is characterized in that, what described DDR memory read that band is wider than a panel module send screen bandwidth, in the time occurring that rear end asynchronous FIFO is fast full, DDR controller control DDR memory stops read operation holding point panel module the data in the asynchronous FIFO of rear end is passed out to screen, thereby reaches dynamic equilibrium.
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