CN110933255B - Two-path asynchronous DVI video synchronization method based on FPGA - Google Patents
Two-path asynchronous DVI video synchronization method based on FPGA Download PDFInfo
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Abstract
The invention relates to a two-path asynchronous DVI video synchronization method based on FPGA, wherein the first path of EVS input DVI video WRITEs data into a WRITE _ FIFO memory according to a data effective signal DE of the first path of EVS input DVI video. In the WRITE state, the controller reads out EVS video data from the WRITE _ FIFO and WRITEs the EVS video data into an external high-speed memory; in the READ state, the controller READs out EVS video data from the external high-speed memory and writes the EVS video data into the READ _ FIFO. In order to ensure the integrity of the EVS video frame data synchronized to the SVS clock domain, an arbitration mechanism is added in the controller, and the EVS video data is READ from the READ _ FIFO memory by the second path of SVS input DVI video according to the data valid signal DE of the second path of SVS input DVI video. Therefore, the input video data of the EVS clock domain is synchronized into the SVS clock domain, and the synchronization of two paths of asynchronous DVI videos of the EVS and the SVS is completed. The synchronization of two paths of asynchronous DVI videos can be realized by using less resources; an arbitration mechanism is added to ensure the integrity of each frame of video image data after clock domain crossing synchronization; the video synchronization process is real-time.
Description
Technical Field
The invention belongs to the field of video processing, and relates to a method for synchronizing two paths of asynchronous DVI videos based on an FPGA (field programmable gate array), which realizes synchronization of two paths of asynchronous DVI input videos of an EVS (EVS) and an SVS (singular value system) in a head-up view system and is convenient for subsequent fusion of the EVS and the SVS videos.
Background
The head-up view system (HVS) is an advanced avionics system formed by integrating a head-up display (HUD), an Enhanced View System (EVS) and a composite view system (SVS). A number of studies and practices have shown that heads-up vision systems can significantly improve flight safety, particularly the ability of aircraft to take off and land in low visibility.
The realization of the head-up view system needs the fusion of an EVS video picture and an SVS video picture, but the EVS and the SVS are two paths of asynchronous DVI videos, so the premise of realizing the fusion of the EVS and the SVS videos is to synchronize the two paths of asynchronous DVI videos of the EVS and the SVS.
Disclosure of Invention
Technical problem to be solved
In order to avoid the defects of the prior art, the invention provides a method for synchronizing two paths of asynchronous DVI videos based on an FPGA (field programmable gate array), which realizes the synchronization of two paths of asynchronous DVI input videos of an EVS (extended visual system) and an SVS (singular value system) in a head-up visual system and is convenient for the subsequent fusion of the EVS and the SVS videos.
Technical scheme
A two-way asynchronous DVI video synchronization method based on FPGA is characterized by comprising a WRITE _ FIFO memory, a controller and a READ _ FIFO memory; the controller realizes the read-write control of EVS video data by using a state machine; the internal state machine has five states, namely an initial state IDLE, a WRITE waiting state WRITE _ WAIT, a WRITE state WRITE, a READ waiting state READ _ WAIT and a READ state READ; an arbitration mechanism is added in the controller to ensure the integrity of each frame of image data of the EVS video synchronized to the SVS clock domain;
the synchronization process is as follows:
writing data into a WRITE _ FIFO memory according to a data effective signal DE of a first path of EVS input DVI video;
after power-on, the controller enters a WRITE _ WAIT state from an IDLE state; waiting for the prog _ empty signal of the WRITE _ FIFO to be 0, enabling the controller to enter a WRITE state from a WRITE _ WAIT state, and otherwise, entering a READ _ WAIT state; in the WRITE state, the controller READs the EVS video data from the WRITE _ FIFO and WRITEs the EVS video data into an external high-speed memory, and then enters the READ _ WAIT state; adding one to the WRITE address WRITE _ addr of each WRITE data in the WRITE state; in the READ _ WAIT state, when a prog _ full signal of the READ _ FIFO is 0 and a READ _ start signal is 1, the controller enters the READ state, otherwise, the controller enters the WRITE _ WAIT state; in the READ state, the controller READs the EVS video data from the external high-speed memory, WRITEs the EVS video data into the READ _ FIFO, and enters the WRITE _ WAIT state. Adding one to each READ address READ _ addr when reading one data in the READ state;
when the field synchronizing signal VSYNC of the DVI video input by the second SVS is effective and the write address write _ addr is not equal to 0, the read _ start signal is 1, and the read _ addr represents the starting read state;
repeatedly reading or deleting the picture data of one complete frame of the EVS video by utilizing an arbitration mechanism in the controller, so that two paths of videos are synchronized:
selecting A, B two buffers in external cache memory, each buffer buffering one frame of EVS video data; with the EVS video resolution of 1280 multiplied by 1024, the frame number of 60, the clock frequency of 108M, the spatial depth of the buffer A, B of 1310720, the address of the buffer A is in the interval of [0, 1310719], and the address of the buffer B is in the interval of [1310720, 2621439 ]; the clock deviation of the two clock domains is 1 percent at most, 1080000 more data are read or written from the external high-speed memory by the fast clock domain than the slow clock domain per second, and 36000 more data are read or written from the external high-speed memory by the fast clock domain than the slow clock domain in two frames; when the controller is in a READ state, if the READ address READ _ addr is 0 and the write address write _ addr is in a [0, 35999] interval, then the READ address READ _ addr risks to catch up with the write address write _ addr, the READ address READ _ addr is changed to 1310720, and then one frame of EVS picture data is repeatedly READ; when the controller is in a WRITE state, if the WRITE address WRITE _ addr is 1310720 and the read address read _ addr is in a [1310720,1346719] interval, at this time, the risk that the WRITE address WRITE _ addr catches up with the read address read _ addr occurs, and the WRITE address WRITE _ addr is made to be 0, namely, one frame of EVS picture data is deleted in a covering manner;
when the second path of SVS input DVI video READs the EVS video data from the READ _ FIFO memory according to the data valid signal DE.
Advantageous effects
The invention provides a two-path asynchronous DVI video synchronization method based on an FPGA. The first path of EVS input DVI video WRITEs data into a WRITE _ FIFO memory according to the data valid signal DE. The controller realizes the read-write control of the EVS video data by using the state machine. In the WRITE state, the controller reads out EVS video data from the WRITE _ FIFO and WRITEs the EVS video data into an external high-speed memory; in the READ state, the controller READs out EVS video data from the external high-speed memory and writes the EVS video data into the READ _ FIFO. Since EVS and SVS video belong to two different clock domains, there is a difference in frequency between the two clock domains. In order to ensure the integrity of the picture data of each frame of the EVS video synchronized into the SVS clock domain, an arbitration mechanism is added in the controller, and the basic principle is to repeatedly read or delete the picture data of one complete frame of the EVS video. The second path of SVS input DVI video READs the EVS video data from the READ _ FIFO memory according to the data valid signal DE. Therefore, the input video data of the EVS clock domain is synchronized into the SVS clock domain, and the synchronization of two paths of asynchronous DVI videos of the EVS and the SVS is completed.
The invention has the advantages that: the invention provides a method for synchronizing two paths of asynchronous DVI videos based on an FPGA (field programmable gate array), which firstly provides and logically realizes the synchronization of two paths of asynchronous DVI videos of an EVS (Ethernet visual System) and an SVS (singular value System) in a head-up view system.
1. The complexity of the logic system architecture is low, and the hardware implementation is convenient; the synchronization of two paths of asynchronous DVI videos can be realized by using less resources;
2. an arbitration mechanism is added to ensure the integrity of each frame of video image data after clock domain crossing synchronization;
3. the whole video synchronization process has good real-time performance, low delay and maximum delay of 2 frames.
Drawings
FIG. 1: logic system architecture schematic
FIG. 2: controller internal state machine schematic
Detailed Description
The invention will now be further described with reference to the following examples and drawings:
the two-way asynchronous DVI video synchronization method based on the FPGA comprises the following steps:
s101, the whole logic system architecture is shown in FIG. 1, and comprises a WRITE _ FIFO memory, a controller and a READ _ FIFO memory.
S102, writing data into a WRITE _ FIFO according to the data valid signal DE of the first path of EVS input DVI video.
S103, the controller completes the read-write control of the EVS video data, and a state machine in the controller is shown in FIG. 2.
IDLE: an initial state;
WRITE _ WAIT: a write wait state;
WRITE: a write state;
READ _ WAIT: reading a waiting state;
READ: the state is read.
And S104, after the power is on, the controller enters a WRITE _ WAIT state from an IDLE state. And waiting for the prog _ empty signal of the WRITE _ FIFO to be 0, and enabling the controller to enter a WRITE state from a WRITE _ WAIT state, or else, entering a READ _ WAIT state. In the WRITE state, the controller READs out EVS video data from the WRITE _ FIFO and WRITEs the EVS video data into the external high-speed memory, and then enters the READ _ WAIT state. WRITE _ addr is incremented by one for each WRITE of a data WRITE address in the WRITE state. In the READ _ WAIT state, the controller will enter the READ state when the prog _ full signal of the READ _ FIFO is 0 and the READ _ start signal is 1, otherwise enter the WRITE _ WAIT state. When the field synchronizing signal VSYNC of the second SVS input DVI video is effective and the write address write _ addr is not equal to 0, the read-on state is indicated, and the read _ start signal is 1. In the READ state, the controller READs the EVS video data from the external high-speed memory, WRITEs the EVS video data into the READ _ FIFO, and enters the WRITE _ WAIT state. READ address READ _ addr is incremented by one every time data is READ in the READ state.
S105, because two paths of independently input DVI videos of the EVS and the SVS are asynchronous, the whole logic system has two clock domains, and the frequency between the two clock domains is different. Assuming that the EVS clock domain frequency is faster than the SVS clock domain frequency, the write address write _ addr inside the controller will catch up with the read address read _ addr at a certain moment. In this case, the data after the address is not read yet and is overwritten by new data, and it is reflected in the video frame that the previous part of a certain frame is the data of the frame but the next part is the data of the next frame. Similarly, when the EVS clock domain frequency is slower than the SVS clock domain frequency, the write address write _ addr inside the controller will be caught up by the read address read _ addr at a certain time. In this case, the data after the address is repeatedly read, and the data is represented in the video frame such that the previous part of a certain frame is the data of the frame but the next part is the data of the previous frame.
And S106, in order to ensure the integrity of each frame of picture data of the EVS video synchronized into the SVS clock domain, adding an arbitration mechanism in the controller. The basic principle is to repeatedly read or delete picture data of one complete frame of the EVS video.
S107, an arbitration mechanism specific implementation method selects two cache regions A, B in an external high-speed memory, and each cache region caches one frame of EVS video data. Assuming that the resolution of the EVS video is 1280 × 1024, the number of frames is 60, the clock frequency is 108M, the spatial depth of the buffer A, B is 1310720, the address of the buffer a is in the interval [0, 1310719], and the address of the buffer B is in the interval [1310720, 2621439 ]. Assuming a maximum clock skew of 1% between the two clock domains, 1080000 more data are read or written from the external high-speed memory per second for the fast clock domain than for the slow clock domain, and 36000 more data are read or written from the external high-speed memory for the fast clock domain over two frames. When the controller is in a READ state, if the READ address READ _ addr is 0 and the write address write _ addr is in a [0, 35999] interval, then the READ address READ _ addr risks to catch up with the write address write _ addr, the READ address READ _ addr is changed to 1310720, and then one frame of EVS picture data is repeatedly READ; when the controller is in the WRITE state, if the WRITE address WRITE _ addr is 1310720 and the read address read _ addr is in the [1310720,1346719] interval, there is a risk that the WRITE address WRITE _ addr catches up with the read address read _ addr, and the WRITE address WRITE _ addr is set to 0, that is, one frame of EVS picture data is deleted in an overwriting manner.
And S108, reading the EVS video data from the READ _ FIFO according to the data valid signal DE of the DVI video input by the second SVS.
And S109, synchronizing the input video data of the EVS clock domain into the SVS clock domain, and completing synchronization of two paths of asynchronous DVI videos of the EVS and the SVS.
Claims (1)
1. A two-way asynchronous DVI video synchronization method based on FPGA is characterized by comprising a WRITE _ FIFO memory, a controller and a READ _ FIFO memory; the controller realizes the read-write control of EVS video data by using a state machine; the internal state machine has five states, namely an initial state IDLE, a WRITE waiting state WRITE _ WAIT, a WRITE state WRITE, a READ waiting state READ _ WAIT and a READ state READ; an arbitration mechanism is added in the controller to ensure the integrity of each frame of image data of the EVS video synchronized to the SVS clock domain;
the synchronization process is as follows:
writing data into a WRITE _ FIFO memory according to a data effective signal DE of a first path of EVS input DVI video;
after power-on, the controller enters a WRITE _ WAIT state from an IDLE state; waiting for the prog _ empty signal of the WRITE _ FIFO to be 0, enabling the controller to enter a WRITE state from a WRITE _ WAIT state, and otherwise, entering a READ _ WAIT state; in the WRITE state, the controller READs the EVS video data from the WRITE _ FIFO and WRITEs the EVS video data into an external high-speed memory, and then enters the READ _ WAIT state; adding one to the WRITE address WRITE _ addr of each WRITE data in the WRITE state; in the READ _ WAIT state, when a prog _ full signal of the READ _ FIFO is 0 and a READ _ start signal is 1, the controller enters the READ state, otherwise, the controller enters the WRITE _ WAIT state; in the READ state, the controller READs the EVS video data from the external high-speed memory, WRITEs the EVS video data into the READ _ FIFO and enters the WRITE _ WAIT state; adding one to each READ address READ _ addr when reading one data in the READ state;
when the field synchronizing signal VSYNC of the DVI video input by the second SVS is effective and the write address write _ addr is not equal to 0, the read _ start signal is 1, and the read _ addr represents the starting read state;
repeatedly reading or deleting the picture data of one complete frame of the EVS video by utilizing an arbitration mechanism in the controller, so that two paths of videos are synchronized:
selecting A, B two buffers in external cache memory, each buffer buffering one frame of EVS video data; with the EVS video resolution of 1280 multiplied by 1024, the frame number of 60, the clock frequency of 108M, the spatial depth of the buffer A, B of 1310720, the address of the buffer A is in the interval of [0, 1310719], and the address of the buffer B is in the interval of [1310720, 2621439 ]; the clock deviation of the two clock domains is 1 percent at most, 1080000 more data are read or written from the external high-speed memory by the fast clock domain than the slow clock domain per second, and 36000 more data are read or written from the external high-speed memory by the fast clock domain than the slow clock domain in two frames; when the controller is in a READ state, if the READ address READ _ addr is 0 and the write address write _ addr is in a [0, 35999] interval, then the READ address READ _ addr risks to catch up with the write address write _ addr, the READ address READ _ addr is changed to 1310720, and then one frame of EVS picture data is repeatedly READ; when the controller is in a WRITE state, if the WRITE address WRITE _ addr is 1310720 and the read address read _ addr is in a [1310720,1346719] interval, at this time, the risk that the WRITE address WRITE _ addr catches up with the read address read _ addr occurs, and the WRITE address WRITE _ addr is made to be 0, namely, one frame of EVS picture data is deleted in a covering manner;
when the second path of SVS input DVI video READs the EVS video data from the READ _ FIFO memory according to the data valid signal DE.
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| CN102833541A (en) * | 2012-08-03 | 2012-12-19 | 东莞中山大学研究院 | SDRAM storage structure used for MPEG-2 video decoding |
| CN104125424A (en) * | 2014-08-06 | 2014-10-29 | 中航华东光电（上海）有限公司 | FPGA (Field Programmable Gate Array) high-speed variable-frame video memory design method |
| US20170208219A1 (en) * | 2016-01-15 | 2017-07-20 | Samsung Electronics Co., Ltd. | Display controller for generating video sync signal using external clock, an application processor including the controller, and an electronic system including the controller |
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