CN102497544B - Device for controlling access to video signals - Google Patents

Device for controlling access to video signals Download PDF

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CN102497544B
CN102497544B CN201110419891.0A CN201110419891A CN102497544B CN 102497544 B CN102497544 B CN 102497544B CN 201110419891 A CN201110419891 A CN 201110419891A CN 102497544 B CN102497544 B CN 102497544B
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write
data
read
control module
signal
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CN102497544A (en
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倪素萍
杜学亮
郭若杉
林啸
蒿杰
张森
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Beijing Jilang Semiconductor Technology Co Ltd
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Institute of Automation of Chinese Academy of Science
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Abstract

The invention discloses a device for controlling access to video signals. The device comprises a write channel and a read channel, wherein the write channel comprises a cache control module, a first-in first-out memory 1 and a bus write control module; and the read channel comprises a bus read control module and a first-in first-out memory 2. The cache control module temporarily stores video data in the first-in first-out memory 1, and then, the bus write control module stores the video data in an external memory through three parallel write modules; the bus read control module reads out the video data in the external memory through three parallel read modules, and temporarily stores the video data in the first-in first-out memory 2. In the device, the clock domain crossing first-in first-out memories with different data width at both sides are used for data caching, and three parallel write controls and three parallel read controls are used for realizing real-time access to the video data, thus, the bus bandwidth can be used effectively, and bus competition can be avoided.

Description

A kind of device that the access of vision signal is controlled
Technical field
The invention belongs to video transmission technologies field, relate to a kind of device that the access of video data is controlled, be used in particular for proposing AXI bus in the SOC (system on a chip) of system bus take ARM company, video data need to be stored in exterior storage body, and exterior storage body is as the situation from equipment of AXI bus.
Background technology
Along with SOC (system on a chip) is in the application development of video field and the extensive use of 64 system bus bit wides, there is a class also to obtain certain development take the AXI bus of 64 bit wides as the SOC (system on a chip) of system bus.AXI (Advanced eXtensible Interface) bus is a part for the bus protocol of ARM company proposition, is a kind of bus on chip towards high-performance, high bandwidth, low delay.For AXI bus, it adopts system clock, and general frequency is higher.And in the vision signal of carrying video data, the bit wide of video data is generally 24, its frequency is generally the frequency of some standard convention, and general frequency is lower.In the SOC (system on a chip) with Video processing, in order to support compared with complicated applications, such as Video Motion Estimation etc., need a lot of frame video images of buffer memory to carry out dynamic analysis, and on sheet, do not have enough spaces to store multiple image, therefore need Video Data Storage in exterior storage body, so that enough large data buffer area to be provided.So just there will be the inconsistent and inconsistent problem of data bit width of vision signal and bus signals frequency.
Summary of the invention
The problem existing in order to solve prior art, the invention provides a kind of device that the access of video data is controlled.
A kind of video data access control device proposed by the invention, is characterized in that, this device comprises write access and read channel, wherein:
Write access is for storing video data into the exterior storage body articulating on system bus by system bus;
Read channel is for reading out by system bus video data from described exterior storage body;
Described write access further comprises: buffer control module S1, and pushup storage 1S2 and bus are write control module S3;
Described read channel further comprises: bus read control module S4 and pushup storage 2S5.
The present invention is by adding cross clock domain, pushup storage that two ends bit wide is different to solve vision signal and bus signals frequency and the inconsistent problem of bit wide between vision signal and AXI bus, and adopt that three concurrent write controls and three are parallel reads to control real time access video data, effectively utilize bus bandwidth, avoid the competition of bus.
Accompanying drawing explanation
Fig. 1 is video data access control device structured flowchart.
Fig. 2 is write address control module control flow chart.
Fig. 3 writes Data Control module controls flow chart.
Fig. 4 writes burst counter update module control flow chart.
Fig. 5 reads address control module control flow chart.
Fig. 6 is read data control module control flow chart.
Fig. 7 reads burst counter update module control flow chart.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention has adopted and has delayed stored video data with cross clock domain, pushup storage that two ends bit wide is different, and then a kind of device that the access of video data is controlled of Video Data Storage being read to exterior storage body or from exterior storage body by AXI bus, this device is realized based on FPGA.
Control device of the present invention is applicable to use the SOC (system on a chip) that the AXI bus of 64 bit wides is system bus, and by video data (24 of video data bit wides) by AXI bus access in exterior storage body.In video access procedure, can face two problems: frequency is inconsistent and data bit width is inconsistent.For AXI bus, it adopts system clock, and general frequency is higher; And for vision signal, it is with the fixed frequency transmission of some agreements, general frequency is lower.Therefore the present invention between vision signal and AXI bus, add the different FIFO of a cross clock domain, two ends bit wide by the Video Data Storage of 24 of bit wides on the AXI bus of 64 bit wides, provided a kind of control method for video access.Here, vision signal can be digital visual interface (Digital VisualInterface, DVI) vision signal or HDMI (High Definition Multimedia Interface) (High DefinitionMultimedia Interface, HDMI) video component of signal, it comprises synchronizing signal and video data.Synchronizing signal has frame synchronizing signal, line synchronizing signal and data useful signal, and in the time that data useful signal sets high, the video data obtaining with HDMI/DVI clock sampling is a pixel of image, is exactly video data of the present invention.Video data information of the present invention has adopted the most frequently used true color, is 24 bit wides.
Fig. 1 is the structured flowchart of video data access control device, and as shown in Figure 1, the device that the access to video data proposed by the invention is controlled comprises: write access and read channel, wherein:
Write access is for storing video data into the exterior storage body articulating on system bus by system bus;
Read channel is for reading out by system bus video data from described exterior storage body.
Described write access further comprises: buffer control module S1, and pushup storage 1S2 and bus are write control module S3, wherein:
Buffer control module S1 is for video data is write to pushup storage 1S2, and the video data line of 24 is connected to [24:0] position of the input signal of pushup storage 1S2; First buffer control module S1 sampled when high and obtains video data at data useful signal take the HDMI/DVI vision signal clock cycle, then the video data obtaining was deposited in pushup storage 1S2.The multipotency of video data line is supported the expansion of 32.
Pushup storage 1S2 is for buffer memory video data.The part being connected with buffer control module S1 has adopted 32 bit wides and vision signal clock, video data is synchronously write to pushup storage 1S2 inside, but video data is 24 true color normally, one 24 represent a pixel, therefore need [31:25] position 0 of pushup storage 1S2 input signal; Write with bus the part that control module S3 is connected and adopted 64 bit data bit wide and system bus clocks, make it to write control module S3 with bus and synchronize.Here, it is for to write control module S3 corresponding with bus that the part that pushup storage 1S2 and buffer control module S1 connect has adopted the object of 32 bit wides, make the video data (having stored 2 24 pixels) of two 32 after pushup storage 1S2, produce the bus data of 64, realize the alignment of data, the pixel splicing while having avoided non-alignment.
Bus is write control module for reading the video data of pushup storage 1S2, then by AXI system bus by Video Data Storage in exterior storage body, bus is write control module and is further comprised: write address control module, write Data Control module and write burst counter update module, bus is write the performed control of control module and is realized based on FPGA circuit, it adopts described three modules to carry out parallel control, main control signal is write burst commencing signal and write burst counter, complete the burst transfer of writing of an AXI bus by the cooperation of the two.Wherein:
Suppose burst transfer M 64 bit data one time, so:
For write address control module, as shown in Figure 2, if write address is set to certain fixed address of exterior storage body when frame synchronizing signal is high, this fixed address can be configured by software its concrete control flow; Otherwise, if write burst commencing signal and be 0 and pushup storage 1S2 to have had N data (N >=M) and write burst counter be 0 o'clock, upgrade write address, after write address is updated to, move the address location of M*8 byte; Write address useful signal when then bus is set writes control module and initiate AXI write request is for effectively, be that AW_VALID signal is for high, as the exterior storage body of this address has responded this write request, exterior storage body arranges write address standby ready signal AW_READY for high; Finally, arrange and write burst commencing signal for high, be the control signal that enables of writing Data Control module.
For writing Data Control module, its concrete control flow as shown in Figure 3, if write burst commencing signal for high, shows that data want the exterior storage body of writing position to allow, and carry out action below, otherwise this module is not done any action; Then judge whether pushup storage 1S2 is empty, if it is not empty, show there are data in pushup storage 1S2, taking out data is put on the data wire of AXI bus, then arrange and write data useful signal W_VALID for high, if exterior storage body can write these data, at this moment AXI bus can be returned and write data ready signal W_READY signal for high, therefore in the time seeing that W_READY is high, repeat said process, in the time writing burst counter and be M-1, when carrying out said process, last data signal line is set for high.
For writing burst counter update module, its concrete control flow as shown in Figure 4, if write data useful signal W_VALID and write data ready signal W_READY and effectively (show that 64 bit data are at that time accepted simultaneously, and can be write in exterior storage body), if when at this moment writing burst counter and being not equal to M-1, write burst counter cumulative 1; If equal M-1, will write burst counter and be set to 0, write burst commencing signal simultaneously and be set to 0, show once to write burst and finish.
Described read channel is used for reading out the video data of exterior storage body, therefore read channel only processing from AXI bus to first-in first-out memory bank FIFO compared with write access, and this process is also based on FPGA, with actual hardware circuit realization.
Described read channel further comprises: bus read control module S4 and pushup storage 2S5.Described bus read control module S4 adopts three modules to carry out the parallel control that data read: read address control module, read data control module and read burst counter update module, main control signal is to read to happen suddenly commencing signal and read burst counter, completes the burst transfer of reading of an AXI bus by the cooperation of the two.
The length of supposing a secondary burst is M 64 bit data, so:
For reading address control module, as shown in Figure 5, if read address when frame synchronizing signal is high and be set to certain fixed address of exterior storage body, this fixed address can be configured by software its concrete control flow, the consistency of software assurance read/write address; Otherwise, be 0 o'clock if pushup storage 2S5 is discontented with and reads burst counter, upgrade and read address, cumulative M*8, namely will read to move after address is updated to the address location of M*8 byte; Address valid signal when then bus read control module initiation AXI read request is set is for effective, be that AR_VALID signal is for high, as the exterior storage body of this address has responded this read request, the setting of exterior storage body is read address standby ready signal AR_READY for high; Finally, the commencing signal of reading to happen suddenly is set for high, is the control signal that enables of read data control module.
For read data control module, its concrete control flow as shown in Figure 6, has allowed if the commencing signal of reading to happen suddenly for high, shows the exterior storage body that data will read position, carry out action below, otherwise this module is not done any action, then judge that whether pushup storage 2S5 is full, if discontented, show the data on the data wire of AXI bus to be left, read data standby ready signal R_READY is set for high, if exterior storage body is ready to data, at this moment AXI bus can be returned to read data useful signal R_VALID signal for high, therefore in the time seeing that R_VALID is high, repeat said process, in the time reading last data of this secondary burst, can see that last data signal line is set to height by exterior storage body, the end that data read completes by reading burst counter update module.
For reading burst counter update module, its concrete control flow as shown in Figure 7.If read data useful signal R_VALID and read data standby ready signal R_READY effectively (show that the data of 64 are at that time ready to simultaneously, and will write pushup storage 2S5), if when at this moment reading burst counter and being not equal to M-1, read burst counter cumulative 1; If while equaling M-1, will read burst counter and be set to 0 (showing once to read burst finishes), the commencing signal of simultaneously reading to happen suddenly is set to 0, closes read data control module.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (9)

1. a video data access control device, is characterized in that, this device comprises write access and read channel, wherein:
Write access is for storing video data into the exterior storage body articulating on system bus by system bus;
Read channel is for reading out by system bus video data from described exterior storage body;
Described write access further comprises: buffer control module (S1), pushup storage 1(S2) and bus write control module (S3), described pushup storage 1(S2) for buffer memory video data, itself and buffer control module (S1) coupling part have adopted 32 bit wides and vision signal clock, write with bus the part that control module (S3) is connected and adopted 64 bit data bit wide and system bus clocks, to realize the alignment of data;
Described read channel further comprises: bus read control module (S4) and pushup storage 2(S5);
Wherein,
Described bus is write control module (S3) and is further comprised three concurrent write modules: write address control module, and write Data Control module and write burst counter update module;
Described bus read control module (S4) further comprises three parallel reads through model: read address control module, read data control module and read burst counter update module.
2. device according to claim 1, is characterized in that, described buffer control module (S1) is for writing video data pushup storage 1(S2); Described buffer control module (S1) is first sampled when high and is obtained video data at data useful signal take the vision signal clock cycle, and deposits the video data obtaining in pushup storage 1(S2) in.
3. device according to claim 1, is characterized in that, described bus is write control module (S3) for reading pushup storage 1(S2) video data, then by system bus by Video Data Storage in exterior storage body.
4. device according to claim 1, is characterized in that, for described write address control module:
If frame synchronizing signal is high, write address is set to certain fixed address of exterior storage body; If frame synchronizing signal is low:
If write that burst commencing signal is 0, pushup storage 1(S2) there are N data, wherein, N>=M, and to write burst counter be 0, moves the address location of M*8 byte after write address being updated to;
Write address useful signal when then described bus is set writes control module and initiate bus write request is for effectively, be that AW_VALID signal is for high, as the exterior storage body of this address has responded this write request, exterior storage body arranges write address standby ready signal AW_READY for high;
Finally, arrange and write burst commencing signal for high, be the control signal that enables of writing Data Control module.
5. device according to claim 1, is characterized in that, for write data control module:
If write burst commencing signal for high, show that data want the exterior storage body of writing position to allow, carry out action below, otherwise write data control module is not done any action;
Then judge pushup storage 1(S2) whether be empty, if it is not empty, show pushup storage 1(S2) in have data, taking out data is put on the data signal line of system bus, then arrange and write data useful signal W_VALID for high, if exterior storage body can write these data, at this moment system bus can return and write data ready signal W_READY signal for high, in the time seeing that W_READY is high, repeat said process;
In the time writing burst counter and be M-1, when carrying out said process, last data signal line is set for high.
6. device according to claim 1, is characterized in that, for the described burst counter update module of writing:
If write data useful signal W_VALID and write data ready signal W_READY simultaneously effectively, if when at this moment writing burst counter and being not equal to M-1, write burst counter cumulative 1; If equal M-1, will write burst counter and be set to 0, write burst commencing signal simultaneously and be set to 0, show once to write burst and finish.
7. device according to claim 1, is characterized in that, for the described address control module of reading:
If frame synchronizing signal is high, reads address and be set to certain fixed address of exterior storage body; If frame synchronizing signal is low:
If pushup storage 2(S5) discontented and to read burst counter be 0, be updated to the address location of reading to move behind address M*8 byte by reading address;
Address valid signal when then described bus read control module initiation bus read request is set is for effective, be that AR_VALID signal is for high, as the exterior storage body of this address has responded this read request, the setting of exterior storage body is read address standby ready signal AR_READY for high;
Finally, the commencing signal of reading to happen suddenly is set for high, described in the commencing signal of reading to happen suddenly be the control signal that enables of read data control module.
8. device according to claim 1, is characterized in that, for described read data control module:
If read to happen suddenly, commencing signal is for high, shows that the exterior storage body that data will read position has allowed, and carry out action below, otherwise described read data control module is not done any action;
Then judge pushup storage 2(S5) whether full, if discontented, show the data on the data signal line of system bus to be left, read data standby ready signal R_READY is set for high, if can sense data from exterior storage body, at this moment system bus can return to read data useful signal R_VALID signal for high, therefore when R_VALID is while being high, repeat said process, when read this time read burst last data time last data signal line be set to height by exterior storage body, the end that data read is completed by the described burst counter update module of reading.
9. device according to claim 1, is characterized in that, for the described burst counter update module of reading:
If read data useful signal R_VALID and read data standby ready signal R_READY effectively, are not equal to M-1 if at this moment read burst counter simultaneously, read burst counter cumulative 1; Equal M-1 if read burst counter, will read burst counter and be set to 0, show once to read burst and finish, the commencing signal of simultaneously reading to happen suddenly is set to 0, closes described read data control module.
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