CN102497544B - Device for controlling access to video signals - Google Patents

Device for controlling access to video signals Download PDF

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CN102497544B
CN102497544B CN201110419891.0A CN201110419891A CN102497544B CN 102497544 B CN102497544 B CN 102497544B CN 201110419891 A CN201110419891 A CN 201110419891A CN 102497544 B CN102497544 B CN 102497544B
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read
write
data
control module
signal
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CN102497544A (en
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倪素萍
杜学亮
郭若杉
林啸
蒿杰
张森
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Beijing Jilang Semiconductor Technology Co Ltd
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Institute of Automation of Chinese Academy of Science
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Abstract

The invention discloses a device for controlling access to video signals. The device comprises a write channel and a read channel, wherein the write channel comprises a cache control module, a first-in first-out memory 1 and a bus write control module; and the read channel comprises a bus read control module and a first-in first-out memory 2. The cache control module temporarily stores video data in the first-in first-out memory 1, and then, the bus write control module stores the video data in an external memory through three parallel write modules; the bus read control module reads out the video data in the external memory through three parallel read modules, and temporarily stores the video data in the first-in first-out memory 2. In the device, the clock domain crossing first-in first-out memories with different data width at both sides are used for data caching, and three parallel write controls and three parallel read controls are used for realizing real-time access to the video data, thus, the bus bandwidth can be used effectively, and bus competition can be avoided.

Description

Device for controlling access of video signal
Technical Field
The invention belongs to the technical field of video transmission, and relates to a device for controlling the access of video data, in particular to a situation that in a system-on-chip taking an AXI bus proposed by an ARM company as a system bus, the video data needs to be stored in an external memory bank which is taken as slave equipment of the AXI bus.
Background
With the application development of the system on chip in the video field and the wide application of 64-bit system bus bit width, a certain development is also provided for the system on chip which takes the 64-bit width AXI bus as the system bus. An axi (advanced eXtensible interface) bus is a part of a bus protocol proposed by ARM corporation, and is an on-chip bus oriented to high performance, high bandwidth and low latency. For an AXI bus, which uses a system clock, the frequency is typically high. In video signals carrying video data, the bit width of the video data is usually 24, and the frequency of the video data is usually a frequency agreed by some standards, and the frequency is generally lower. In a system on chip with video processing, in order to support more complex applications such as video motion estimation, etc., many frames of video images need to be buffered for dynamic analysis, and there is not enough space on chip to store multiple frames of images, so that video data needs to be stored in an external memory bank to provide a large enough data buffer area. This causes the problem of inconsistent frequencies of video signals and bus signals and inconsistent data bit widths.
Disclosure of Invention
To solve the problems of the prior art, the present invention provides an apparatus for controlling access to video data.
The invention provides a video data access control device, which is characterized by comprising a writing channel and a reading channel, wherein:
the writing channel is used for storing the video data into an external memory bank hooked on the system bus through the system bus;
the read channel is used for reading the video data from the external memory bank through a system bus;
the write channel further comprises: a buffer control module S1, a first-in first-out memory 1S2 and a bus write control module S3;
the read channel further comprises: bus read control module S4 and fifo 2S 5.
The invention solves the problem of inconsistent frequency and bit width of the video signal and the bus signal by adding a clock-crossing domain and a first-in first-out memory with different bit widths at two ends between the video signal and the AXI bus, and adopts three parallel write controls and three parallel read controls to access the video data in real time, thereby effectively utilizing the bus bandwidth and avoiding the competition of the bus.
Drawings
Fig. 1 is a block diagram of a video data access control device.
Fig. 2 is a write address control block control flow diagram.
Fig. 3 is a control flow chart of the write data control module.
FIG. 4 is a write burst counter update module control flow diagram.
Fig. 5 is a control flow diagram of the read address control module.
Fig. 6 is a read data control module control flow diagram.
FIG. 7 is a read burst counter update module control flow diagram.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
The invention adopts a device for controlling the access of video data, which uses a first-in first-out memory with different bit widths at two ends across clock domains to cache and store the video data, and then stores the video data into an external memory bank or reads the video data from the external memory bank through an AXI bus, and the device is realized based on FPGA.
The control device is suitable for a system on chip which uses an AXI bus with 64 bit width as a system bus, and accesses video data (video data with 24 bit width) in an external memory bank through the AXI bus. During video access, two problems are faced: frequency inconsistency and data bit width inconsistency. For the AXI bus, a system clock is adopted, and the frequency is generally higher; for video signals, it is transmitted at some agreed fixed frequency, typically lower. Therefore, the invention adds a FIFO with different bit widths across the clock domain and at two ends between the video signal and the AXI bus to store the video data with 24 bits of bit width on the AXI bus with 64 bit width, and provides a control method for video access. Here, the video signal may be a Digital Visual Interface (DVI) video signal or a video component of a High Definition Multimedia Interface (HDMI) signal, which includes a sync signal and video data. The synchronous signals comprise frame synchronous signals, line synchronous signals and effective data signals, and when the effective data signals are set high, video data obtained by sampling through an HDMI/DVI clock is one pixel of an image, namely the video data. The video data information of the present invention uses the most common true color, which is 24 bits wide.
Fig. 1 is a block diagram of a video data access control device, and as shown in fig. 1, the device for controlling access to video data according to the present invention includes: a write channel and a read channel, wherein:
the writing channel is used for storing the video data into an external memory bank hooked on the system bus through the system bus;
the read channel is used for reading the video data from the external memory bank through the system bus.
The write channel further comprises: a buffer control module S1, a first-in-first-out memory 1S2, and a bus write control module S3, wherein:
the buffer control module S1 is used to write video data into the FIFO 1S2, the 24-bit video data line is connected to [24:0] bits of the input signal of the FIFO 1S 2; the buffer control module S1 samples the video data with the HDMI/DVI video signal clock period when the data valid signal is high, and then stores the obtained video data in the fifo memory 1S 2. The video data lines can support up to 32-bit extensions.
The first-in first-out memory 1S2 is used to buffer video data. The part connected with the buffer control module S1 uses 32 bits wide and video signal clock to synchronously write the video data into the fifo memory 1S2, but the video data is usually 24 bits true color, one 24 bit represents one pixel, so that the fifo memory 1S2 needs to input the signal at position 0 [31:25 ]; the portion connected to the bus write control block S3 uses the 64-bit data bit width and the system bus clock to synchronize with the bus write control block S3. Here, the purpose of using 32-bit wide for the connection portion of the fifo memory 1S2 and the buffer control block S1 is to correspond to the bus write control block S3, so that two 32-bit video data (storing 2 24-bit pixels) pass through the fifo memory 1S2 to generate a 64-bit bus data, thereby achieving alignment of data and avoiding pixel splicing when the data is not aligned.
The bus write control module is configured to read out video data from the fifo memory 1S2, and store the video data in an external memory bank via the AXI system bus, and the bus write control module further includes: the bus write control module is controlled by a circuit based on FPGA and adopts the three modules to carry out parallel control, main control signals are a write burst starting signal and a write burst counter, and one-time AXI bus write burst transmission is completed through the cooperation of the write burst starting signal and the write burst counter. Wherein:
assuming that M64-bit data are burst transferred at a time, then:
for the write address control module, the specific control flow is as shown in fig. 2, if the write address is set to a fixed address of the external memory bank when the frame synchronization signal is high, the fixed address can be configured by software; otherwise, if the write burst start signal is 0, N data (N ═ M) already exist in the fifo memory 1S2, and the write burst counter is 0, the write address is updated, and the write address is updated to the address position shifted backward by M × 8 bytes; then setting a write address VALID signal to be VALID when the bus write control module initiates the AXI write request, namely setting the AW _ VALID signal to be high, and if the external memory bank of the address responds to the write request, setting a write address READY signal AW _ READY to be high by the external memory bank; and finally, setting the write burst starting signal to be high, namely, setting the write burst starting signal to be an enabling control signal of the write data control module.
For the write data control module, the specific control flow is as shown in fig. 3, if the write burst start signal is high, indicating that the external memory bank where the data is to be written is allowed, the following action is performed, otherwise, the module does not perform any action; then, whether the fifo 1S2 is empty or not is judged, if not, it is indicated that data is stored in the fifo 1S2, a piece of data is taken out and put on a data line of the AXI bus, then a write data VALID signal W _ VALID is set to high, if the external bank can write the data, the AXI bus returns a write data READY signal W _ READY to high, so when it is seen that W _ READY is high, the above process is repeated, and when the write burst counter is M-1, the last data signal line is set to high while the above process is executed.
For the write burst counter update module, the specific control flow is as shown in fig. 4, if the write data VALID signal W _ VALID and the write data READY signal W _ READY are simultaneously VALID (indicating that a 64-bit data at that time has been accepted and will be written into the external memory bank), at this time, if the write burst counter is not equal to M-1, the write burst counter increments by 1; if equal to M-1, the write burst counter is set to 0, while the write burst start signal is set to 0, indicating the end of a write burst.
The read channel is used for reading out video data in an external memory bank, so that the read channel only processes from an AXI bus to a first-in first-out memory bank FIFO compared with a write channel, and the process is also based on an FPGA and is realized by an actual hardware circuit.
The read channel further comprises: bus read control module S4 and fifo 2S 5. The bus read control module S4 adopts three modules to perform parallel control of data reading: the device comprises a read address control module, a read data control module and a read burst counter updating module, wherein main control signals are a read burst starting signal and a read burst counter, and one-time AXI bus read burst transmission is completed through the cooperation of the read burst starting signal and the read burst counter.
Assuming that the length of a burst is M64-bit data, then:
for the read address control module, the specific control flow is shown in fig. 5, if the read address is set as a fixed address of the external memory bank when the frame synchronization signal is high, the fixed address can be configured by software, and the software ensures the consistency of the read address and the write address; otherwise, if the fifo 2S5 is not full and the read burst counter is 0, the read address is updated, i.e. M × 8 is accumulated, i.e. the read address is updated to the address position shifted by M × 8 bytes later; then setting an address VALID signal when the bus read control module initiates an AXI read request to be VALID, namely setting an AR _ VALID signal to be high, and if an external memory bank of the address responds to the read request, setting a read address READY signal AR _ READY to be high by the external memory bank; and finally, setting the read burst starting signal to be high, namely, setting the read burst starting signal to be an enabling control signal of the read data control module.
For the read data control module, the specific control flow is as shown in fig. 6, if the read burst start signal is high, indicating that the external memory bank of the location where the data is to be read has been allowed, the following action is performed, otherwise, the module does not perform any action; then, it is determined whether the fifo 2S5 is full, if not, it indicates that the data on the data line of the AXI bus can be stored, the read data READY signal R _ READY is set high, if the external memory bank is READY for data, the AXI bus returns a read data VALID signal R _ VALID signal high, so when R _ VALID is seen to be high, the above process is repeated, when the last data of the burst is read, it is seen that the last data signal line is set high by the external memory bank, and the end of data reading is completed by the read burst counter update module.
For the read burst counter update module, the specific control flow is shown in fig. 7. If the read data VALID signal R _ VALID and the read data READY signal R _ READY are both VALID (indicating that a 64-bit data is READY at the time and will be written to FIFO 2S5), then if the read burst counter is not equal to M-1, the read burst counter increments by 1; if the value is equal to M-1, the read burst counter is set to 0 (indicating the end of one read burst), and the read burst start signal is set to 0, so that the read data control module is closed.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A video data access control apparatus, comprising a write channel and a read channel, wherein:
the writing channel is used for storing the video data into an external memory bank hooked on the system bus through the system bus;
the read channel is used for reading the video data from the external memory bank through a system bus;
the write channel further comprises: the buffer memory control module (S1), the first-in first-out memory 1 (S2) and the bus write control module (S3), the first-in first-out memory 1 (S2) is used for buffering video data, the part of the first-in first-out memory 1 (S2) connected with the buffer memory control module (S1) adopts 32 bit width and video signal clock, and the part connected with the bus write control module (S3) adopts 64 bit data bit width and system bus clock, so as to realize the alignment of data;
the read channel further comprises: a bus read control module (S4) and a first-in first-out memory 2 (S5);
wherein,
the bus write control module (S3) further includes three parallel write modules: the write address control module, the write data control module and the write burst counter updating module;
the bus read control module (S4) further includes three parallel read modules: the device comprises a read address control module, a read data control module and a read burst counter updating module.
2. The apparatus of claim 1, wherein the buffer control module (S1) is configured to write the video data into a first-in-first-out memory 1 (S2); the buffer control module (S1) first samples the video data at the video signal clock cycle when the data valid signal is high, and stores the obtained video data in the fifo memory 1 (S2).
3. The apparatus of claim 1, wherein the bus write control module (S3) is configured to read out video data of the first-in first-out memory 1 (S2) and then store the video data into the external memory bank through the system bus.
4. The apparatus of claim 1, wherein for the write address control module:
setting the write address to a fixed address of the external memory bank if the frame synchronization signal is high; if the frame synchronization signal is low, then:
if the write burst start signal is 0, N data already exist in the first-in first-out memory 1 (S2), where N > = M, and the write burst counter is 0, the write address is updated to the address position shifted by M × 8 bytes later;
then setting a write address VALID signal to be VALID when the bus write control module initiates a bus write request, namely setting the AW _ VALID signal to be high, and if the external memory bank of the address responds to the write request, setting a write address READY signal AW _ READY to be high by the external memory bank;
and finally, setting the write burst starting signal to be high, namely, setting the write burst starting signal to be an enabling control signal of the write data control module.
5. The apparatus of claim 1, wherein for the write data control module:
if the write burst start signal is high, indicating that the external memory bank where the data is to be written has been allowed, then the following action is taken, otherwise the write data control module does nothing;
then judging whether the first-in first-out memory 1 (S2) is empty or not, if not, indicating that the first-in first-out memory 1 (S2) has data, taking out a data to put on a data signal line of a system bus, then setting a write data VALID signal W _ VALID to be high, if the external memory bank can write the data, then the system bus returns a write data READY signal W _ READY to be high, and when the W _ READY is seen to be high, repeating the process;
when the write burst counter is M-1, the process described above is performed while the last data signal line is set high.
6. The apparatus of claim 1, wherein for the write burst counter update module:
if the write data VALID signal W _ VALID and the write data READY signal W _ READY are simultaneously VALID, then if the write burst counter is not equal to M-1, the write burst counter increments by 1; if equal to M-1, the write burst counter is set to 0, while the write burst start signal is set to 0, indicating the end of a write burst.
7. The apparatus of claim 1, wherein for the read address control module:
if the frame synchronization signal is high, setting the read address as a certain fixed address of the external memory bank; if the frame synchronization signal is low, then:
if the fifo 2 (S5) is not full and the read burst counter is 0, updating the read address to the read address and moving it back by M × 8 bytes;
then setting an address VALID signal when the bus read control module initiates a bus read request to be VALID, namely setting an AR _ VALID signal to be high, and if an external memory bank of the address responds to the read request, setting a read address READY signal AR _ READY to be high by the external memory bank;
and finally, setting the read burst start signal to be high, wherein the read burst start signal is an enable control signal of the read data control module.
8. The apparatus of claim 1, wherein for the read data control module:
if the read burst start signal is high, indicating that the external memory bank of the position to be read by the data is allowed, then the following action is carried out, otherwise, the read data control module does not carry out any action;
then, it is determined whether the fifo 2 is full (S5), if not, it indicates that the data on the data signal line of the system bus can be stored, the read data READY signal R _ READY is set high, if the data can be read from the external memory bank, the system bus returns a read data VALID signal R _ VALID signal high, so when R _ VALID is high, the above process is repeated, when the last data of the read burst is read, the last data signal line is set high by the external memory bank, and the end of the data reading is completed by the read burst counter update module.
9. The apparatus of claim 1, wherein for the read burst counter update module:
if the read data VALID signal R _ VALID and the read data READY signal R _ READY are simultaneously VALID, then if the read burst counter is not equal to M-1, the read burst counter increments by 1; and if the read burst counter is equal to M-1, setting the read burst counter to be 0 to indicate that one read burst is finished, simultaneously setting a read burst starting signal to be 0, and closing the read data control module.
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103248538B (en) * 2013-05-16 2016-09-07 中国电子科技集团公司第四十一研究所 A kind of based on FPGA and DDR3 realize IP network accumulation burst out damage method
CN106601160B (en) * 2016-12-14 2020-04-14 昆山龙腾光电股份有限公司 Refresh rate conversion device and method and display device
CN108595350B (en) * 2018-01-04 2022-04-05 深圳开阳电子股份有限公司 AXI-based data transmission method and device
CN114253880B (en) * 2020-09-24 2024-08-06 京东方科技集团股份有限公司 Clock frequency adjustment method, device, electronic equipment and readable storage medium
CN112532935A (en) * 2020-11-23 2021-03-19 天津津航计算技术研究所 Device for determining video source position based on SOC
CN112599083B (en) * 2020-12-24 2022-09-06 深圳市洲明科技股份有限公司 Data transmission method, data receiving method, sending card and receiving card of display screen
CN114302089B (en) * 2021-12-06 2024-09-27 中国船舶重工集团公司第七0九研究所 Multi-channel video signal cache control method and system based on FPGA

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6154225A (en) * 1996-10-11 2000-11-28 Silicon Motion, Inc. Virtual refresh™ architecture for a video-graphics controller
US7284074B2 (en) * 2002-10-31 2007-10-16 Force10 Networks, Inc. Pipelined network processing with FIFO queues
CN101055704A (en) * 2007-04-28 2007-10-17 深圳安凯微电子技术有限公司 A LCD data write-in control method and first in and first out memory
CN101236601A (en) * 2008-03-11 2008-08-06 董亮 Image recognition accelerator and MPU chip possessing image recognition accelerator
CN102253909A (en) * 2011-06-30 2011-11-23 济南大学 PCI (Peripheral Component Interconnect) interface and data transmission method thereof under FPGA (Filed-Programmable Gate Array) environment

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040193835A1 (en) * 2003-03-31 2004-09-30 Patrick Devaney Table lookup instruction for processors using tables in local memory
CN100414524C (en) * 2005-09-20 2008-08-27 中国科学院计算技术研究所 Method for controlling data transmission between two different speed buses
US8151008B2 (en) * 2008-07-02 2012-04-03 Cradle Ip, Llc Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling
CN101667451B (en) * 2009-09-11 2012-05-09 西安电子科技大学 Data buffer of high-speed data exchange interface and data buffer control method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6154225A (en) * 1996-10-11 2000-11-28 Silicon Motion, Inc. Virtual refresh™ architecture for a video-graphics controller
US7284074B2 (en) * 2002-10-31 2007-10-16 Force10 Networks, Inc. Pipelined network processing with FIFO queues
CN101055704A (en) * 2007-04-28 2007-10-17 深圳安凯微电子技术有限公司 A LCD data write-in control method and first in and first out memory
CN101236601A (en) * 2008-03-11 2008-08-06 董亮 Image recognition accelerator and MPU chip possessing image recognition accelerator
CN102253909A (en) * 2011-06-30 2011-11-23 济南大学 PCI (Peripheral Component Interconnect) interface and data transmission method thereof under FPGA (Filed-Programmable Gate Array) environment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
陈宏铭等.高效能 低功耗DDR2 控制器的硬件实现.《中国集成电路》.2011
高效能,低功耗DDR2 控制器的硬件实现;陈宏铭 等;《中国集成电路》;20110531(第144期);第58-65页 *

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