CN101055704A - A LCD data write-in control method and first in and first out memory - Google Patents
A LCD data write-in control method and first in and first out memory Download PDFInfo
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- CN101055704A CN101055704A CN 200710074165 CN200710074165A CN101055704A CN 101055704 A CN101055704 A CN 101055704A CN 200710074165 CN200710074165 CN 200710074165 CN 200710074165 A CN200710074165 A CN 200710074165A CN 101055704 A CN101055704 A CN 101055704A
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Abstract
The invention is suitable for a multimedia technic field, provides an LCd data write control method and a first-in first-out memory, the method comprises: receiving a second passage starting signal in a process of writting data of a first passage, wherein the second passage starting signal is used for marking an address where the second passage data is started to input; receiving a first passage finish signal when data input of the first passage is finished, and at the same time writting data of the second passage from the address marked by the second passage starting signal; reading the data of the frist passage and the inputted data of the second passage during a process of inputting the second passage. The invention solves a problem that data reading speed and efficiency are low when realizing an LCD image-in-image function in a current technic.
Description
Technical field
The invention belongs to multimedia technology field, relate in particular to a kind of LCD data write-in control method and pushup storage.
Background technology
Along with the continuous maturation and the development of mobile multimedia technology, (Liquid Crystal Display LCD) has also obtained using more widely as the LCD of main display unit.The LCD interface of present main flow mainly contains microprocessor, and (MICRO PROCESSER UNIT, MPU) (Red GreenBlue, RGB) interface is two kinds for interface and RGB.
The LCD chip for driving of MPU interface, because there is the buffer memory that can deposit a frame image data its inside, therefore not high for the requirement of lcd controller, but LCD chip for driving for rgb interface, because its inside does not have a such buffer memory, and require per second to reach the refresh rate of 60 frames nearly simultaneously, therefore the performance requirement to lcd controller is just very high.Fig. 1 shows the syndeton of lcd controller and chip for driving in the prior art.
Fig. 1 shows the syndeton of lcd controller and LCD chip for driving in the prior art, wherein, lcd controller is used for giving an order with the form of data, and the LCD chip for driving is used to receive the order data of lcd controller and carries out this order, the action of control LCD display panel.
In order to reach the requirement that uninterruptedly refreshes fast, in the design of lcd controller, tend to add a pushup storage circuit (First IN First Out that volume ratio is bigger, FIFO), simultaneously, because the clock of the chip for driving of rgb interface and the phase place and the frequency difference of lcd controller clock are bigger, therefore, this FIFO can be designed to asynchronous.
Fig. 2 shows a kind of structure that typically has the lcd controller of picture-in-picture function, when carrying out the picture-in-picture operation, two kinds of schemes are arranged usually, first kind is in image synthesis unit two channel image to be synthesized a width of cloth picture, send in the asynchronous FIFO then, by the output of interface sequence module, realize picture-in-picture truly.
This scheme is when realizing picture-in-picture, control simply relatively, but necessarily require that the image imported is synthetic to be finished, that is to say, it is synthetic to have an independent image synthesis unit to carry out picture-in-picture in the prime of asynchronous FIFO, has increased area of chip and cost.
Another kind of scheme is a composograph in asynchronous FIFO, writes a channel image earlier, writes another channel image again, reads after all having write again and refreshes, and certain, this is with behavior unit.
This scheme is when realizing picture-in-picture, and delegation's image just can be read behind synthetic the finishing in asynchronous FIFO, has reduced the reading speed and the efficient of data.
Summary of the invention
Embodiment of the invention technical matters to be solved is to provide a kind of LCD data write-in control method and pushup storage, so that LCD when realizing picture-in-picture function, improves the FIFO read-write efficiency under the prerequisite that reduces hardware cost.
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of LCD data write-in control method, and described method comprises:
In the process of the data that write first passage, receive the second channel commencing signal, described second channel commencing signal is used to identify the address that begins to import the second channel data;
When the data end of input of first passage, receive the first passage end signal, write the data of second channel simultaneously from the address of described second channel commencing signal sign;
In the process of input second channel, read the data of first passage and the data of the second channel imported.
The embodiment of the invention also provides a kind of pushup storage, comprises Double Port Random Memory, and described storer also comprises:
The write address generation unit is used in the process that writes the first passage data, receives the second channel commencing signal, described second channel commencing signal is used to identify the address that begins to import the second channel data, simultaneously, produce a pseudo-write address, described pseudo-write address is used to produce fifo empty signal;
The alternative unit is used for when described write address generation unit receives the first passage end signal, the pseudo-write address of selecting the write address generation unit to produce, as with Double Port Random Memory in the synchronous write address of write data;
The FIFO write data unit when being used for selecting in described alternative unit described pseudo-write address, writes the data of second channel from the address of described second channel commencing signal sign; And
The FIFO reading data unit is used for writing the process of second channel, reads the data of first passage and the data of the second channel imported.
The embodiment of the invention is by receiving the second channel commencing signal in the process that receives the first passage data, wherein, the data Input Address of this second channel commencing signal sign second channel, when receiving the first passage end signal, write the data of second channel from the address of this second channel commencing signal sign, and in writing the process of second channel, the data of the second channel of reading the data of first passage and having write, realize simple, solved in the prior art, when realizing the LCD picture-in-picture function, the problem that data reading speed and efficient are lower.
Description of drawings
Fig. 1 is the johning knot composition of lcd controller and LCD chip for driving in the prior art;
Fig. 2 is the structural drawing of lcd controller in the prior art;
Fig. 3 is the structural drawing of the pushup storage that provides of the embodiment of the invention;
Fig. 4 is the process flow diagram of the LCD data write-in control method that provides of the embodiment of the invention;
Fig. 5 is the pushup storage control procedure figure that the embodiment of the invention provides.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention is by receiving the second channel commencing signal in the process that receives the first passage data, wherein, the data Input Address of this second channel commencing signal sign second channel, when receiving the first passage end signal, write the data of second channel from the address of this second channel commencing signal sign, and in writing the process of second channel, read the data of first passage and the data of the second channel that write.
Fig. 3 shows the structure of the pushup storage that the embodiment of the invention provides.
Write in the first passage data procedures in the FIFO write data unit, the write address generation unit receives the second channel commencing signal, and wherein, this second channel commencing signal sign begins to write the address of second channel data.At this moment, the write address that the alternative unit will select the write address generation unit to produce is as the write address of Double Port Random Memory, cooperate with the write data of Double Port Random Memory, receive the data that the FIFO write data unit writes at first passage, concrete engagement process belongs to prior art, repeats no more.
In specific implementation process, this write address is used for writing clock zone generation FIFO completely, the half-full signal that waits of FIFO.And in writing the process of first passage, the FIFO reading data unit can not read the data of the first passage that has write.
After receiving the second channel commencing signal, address from this second channel commencing signal sign, some belongs to second channel, but this moment, the data of second channel also were not written into, as embodiments of the invention, at this moment, the write address generation unit will produce a pseudo-write address, and should the puppet write address be latched as the start address of second channel, write the data that are latched as second channel in the end during this period of time to the first passage data and write the address from receiving the second channel commencing signal, all the other are constantly with increasing progressively with imitating signal.
In specific implementation process, the pseudo-write address that the write address generation unit produces will be sent to scale-of-two commentaries on classics Gray code unit and change into Gray code, be sent to and read clock zone through reading clock domain synchronizer then, reading clock zone reads clock synchronously and writes clock, and the pseudo-write address that will change into Gray code is sent to Gray code and changes binary cell and transfer binary code to, at last, empty sign generation unit is at the pseudo-write address that receives binary code representation with after reading the address, produce fifo empty signal, because the generation reference of fifo empty signal is pseudo-write address, so the data that the FIFO reading data unit can not read the second channel that latchs write this section space, address.Like this, the sector address of this in FIFO space just is protected.
After the data of first passage write end, the write address generation unit received the first passage end signal, and wherein, these first passage end signal sign first passage data write the address of end.At this moment, the pseudo-write address that the alternative unit will select the write address generation unit to produce as the write address of Double Port Random Memory, cooperates with the write data of Double Port Random Memory, receives the data that the FIFO write data unit writes at second channel.
And, after the data of first passage write end, the address the when data of first passage are write write address when finishing and are latched in first passage and finish.Like this, write in the process of data of second channel in the FIFO write data, the write address that the write address generation unit produces will can not increase progressively.All the other constantly as long as have with imitating signal, will increase progressively, and as prior art, this write address is used for that to generate FIFO full writing clock zone, the half-full signal that waits of FIFO.
Certainly, write in the process of second channel data in the FIFO write data unit, the maximal value that in fact effectively writes data address among the FIFO remains the address that the first passage data write end, therefore, during this period of time write address is being latched, guaranteeing in time and the generation FIFO full scale will of safety.
And, writing in the process of data of second channel in the FIFO write data unit, the FIFO reading data unit begins to read the data of first passage and the data of the second channel imported.
After the data of second channel write end, the write address generation unit received the second channel end signal.At this moment, the pseudo-write address of alternative unit controls jumps to the position of the channel end signal identification of first passage, thus open whole address spaces.
Fig. 4 shows the flow process of data write-in control method among the LCD that the embodiment of the invention provides, and Fig. 5 shows the pushup storage control procedure that the embodiment of the invention provides, and is described as follows below in conjunction with Fig. 4 and Fig. 5.
In the process of the data that write first passage, receive the second channel commencing signal, wherein, this second channel commencing signal sign begins to import the address of second channel data.In specific implementation process, when receiving the second channel commencing signal, produce a pseudo-write address, this puppet write address produces fifo empty signal, and the process that specifically produces fifo empty signal is stated at preamble, repeats no more herein.
When the data end of input of first passage, receive the first passage end signal, write the data of second channel simultaneously from the address of second channel commencing signal sign, and, in the process of input second channel, read the data of first passage and the data of the second channel imported.
When the data of second channel write end, receive the channel end signal of second channel, control pseudo-write address and jump to the address that the first passage data write end, thus all open address space.
The embodiment of the invention is by receiving the second channel commencing signal in the process that receives the first passage data, wherein, the data Input Address of this second channel commencing signal sign second channel, when receiving the first passage end signal, write the data of second channel from the address of this second channel commencing signal sign, and in writing the process of second channel, the data of the second channel of reading the data of first passage and having write, realize simple, solved in the prior art, when realizing the LCD picture-in-picture function, the problem that data reading speed and efficient are lower.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1, a kind of LCD data write-in control method is characterized in that, described method comprises:
In the process of the data that write first passage, receive the second channel commencing signal, described second channel commencing signal is used to identify the address that begins to import the second channel data;
When the data end of input of first passage, receive the first passage end signal, write the data of second channel simultaneously from the address of described second channel commencing signal sign;
In the process of input second channel, read the data of first passage and the data of the second channel imported.
2, LCD data write-in control method as claimed in claim 1 is characterized in that, described method further comprises:
When receiving the second channel commencing signal, produce a pseudo-write address, described pseudo-write address is used to produce fifo empty signal.
3, LCD data write-in control method as claimed in claim 1 is characterized in that, described method further comprises:
Receive the channel end signal of second channel, control described pseudo-write address and jump to the address that the first passage data write end.
4, a kind of pushup storage comprises Double Port Random Memory, it is characterized in that, described storer also comprises:
The write address generation unit is used in the process that writes the first passage data, receives the second channel commencing signal, described second channel commencing signal is used to identify the address that begins to import the second channel data, simultaneously, produce a pseudo-write address, described pseudo-write address is used to produce fifo empty signal;
The alternative unit is used for when described write address generation unit receives the first passage end signal, the pseudo-write address of selecting the write address generation unit to produce, as with Double Port Random Memory in the synchronous write address of write data;
The FIFO write data unit when being used for selecting in described alternative unit described pseudo-write address, writes the data of second channel from the address of described second channel commencing signal sign; And
The FIFO reading data unit is used for writing the process of second channel, reads the data of first passage and the data of the second channel imported.
5, pushup storage as claimed in claim 4 is characterized in that, described storer further comprises:
Scale-of-two changes the Gray code unit, is used for the pseudo-write address of write address generation unit generation binary mode is changed into Gray code;
6, pushup storage as claimed in claim 4 is characterized in that, described storer further comprises:
Gray code changes binary cell, is used for described Gray code is transferred to the pseudo-write address of binary code representation;
7, pushup storage as claimed in claim 4 is characterized in that, described storer further comprises:
Empty sign generation unit is used at the pseudo-write address that receives binary code representation and after reading the address, produces fifo empty signal.
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| CNB2007100741653A CN100505029C (en) | 2007-04-28 | 2007-04-28 | A LCD data write-in control method and first in and first out memory |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267459B (en) * | 2008-04-23 | 2011-11-23 | 无锡中星微电子有限公司 | Data output method and data buffer employing asynchronous FIFO register output data |
| CN102497544A (en) * | 2011-12-15 | 2012-06-13 | 中国科学院自动化研究所 | Device for controlling access to video signals |
| CN108363675A (en) * | 2018-02-05 | 2018-08-03 | 成都天诚慧芯科技有限公司 | A kind of accompanying clock synchronous method and digital picture gamma correction hardware implementation method |
| CN111400205A (en) * | 2020-02-29 | 2020-07-10 | 华南理工大学 | First-in first-out address polling cache read-write method, system and device |
| CN112140108A (en) * | 2020-09-07 | 2020-12-29 | 珠海格力电器股份有限公司 | Method, device and equipment for quickly responding to abnormal state and computer readable medium |
| CN112703552A (en) * | 2018-10-10 | 2021-04-23 | 深圳市柔宇科技股份有限公司 | GOA circuit and display device |
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2007
- 2007-04-28 CN CNB2007100741653A patent/CN100505029C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267459B (en) * | 2008-04-23 | 2011-11-23 | 无锡中星微电子有限公司 | Data output method and data buffer employing asynchronous FIFO register output data |
| CN102497544A (en) * | 2011-12-15 | 2012-06-13 | 中国科学院自动化研究所 | Device for controlling access to video signals |
| CN102497544B (en) * | 2011-12-15 | 2014-06-25 | 中国科学院自动化研究所 | Device for controlling access to video signals |
| CN108363675A (en) * | 2018-02-05 | 2018-08-03 | 成都天诚慧芯科技有限公司 | A kind of accompanying clock synchronous method and digital picture gamma correction hardware implementation method |
| CN108363675B (en) * | 2018-02-05 | 2021-03-05 | 成都天诚慧芯科技有限公司 | Accompanying clock synchronization method and digital image gamma correction hardware implementation method |
| CN112703552A (en) * | 2018-10-10 | 2021-04-23 | 深圳市柔宇科技股份有限公司 | GOA circuit and display device |
| CN111400205A (en) * | 2020-02-29 | 2020-07-10 | 华南理工大学 | First-in first-out address polling cache read-write method, system and device |
| CN111400205B (en) * | 2020-02-29 | 2022-05-24 | 华南理工大学 | First-in first-out address polling cache read-write method, system and device |
| CN112140108A (en) * | 2020-09-07 | 2020-12-29 | 珠海格力电器股份有限公司 | Method, device and equipment for quickly responding to abnormal state and computer readable medium |
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| CN100505029C (en) | 2009-06-24 |
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Owner name: ANKAI (GUANGZHOU) MICROELECTRONICS TECHNOLOGY CO., Free format text: FORMER OWNER: SHENZHEN ANKAI MICROELECTRONICS TECHNOLOGY CO., LTD. Effective date: 20100122 |
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Effective date of registration: 20100122 Address after: 3 floor, C1 District, Chuangxin Road, No. 182, science Avenue, Guangzhou Science City, Guangdong Patentee after: Anyka (Guangzhou) Microelectronics Technology Co., Ltd. Address before: A3, building 2, building, Shenzhen digital technology park, Nanshan District hi tech Industrial Park, Shenzhen, Guangdong, China Patentee before: Shenzhen Anyka Microelectronics Technology Co., Ltd. |
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Address after: 510600, Guangzhou Science City, Guangdong science Road, 182 innovation building, C1 District, 3 floor Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 510600, Guangzhou Science City, Guangdong science Road, 182 innovation building, C1 District, 3 floor Patentee before: ANYKA (GUANGZHOU) MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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Address after: 510555 No. 107 Bowen Road, Huangpu District, Guangzhou, Guangdong Patentee after: Guangzhou Ankai Microelectronics Co.,Ltd. Address before: 510600, Guangzhou Science City, Guangdong science Road, 182 innovation building, C1 District, 3 floor Patentee before: Guangzhou Ankai Microelectronics Co.,Ltd. |
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