WO2005059886A1

WO2005059886A1 - Hold type display device and parts thereof

Info

Publication number: WO2005059886A1
Application number: PCT/JP2005/002938
Authority: WO
Inventors: Kenji Mizuno; Nobuyuki Hayama; Akio Kameda; Takashi Sasaki; Shoji Iwasaki
Original assignee: Marubun Corporation
Priority date: 2004-02-24
Filing date: 2005-02-23
Publication date: 2005-06-30
Also published as: JP3839460B2; JPWO2005059886A1

Abstract

[PROBLEMS] To provide drive technique of a general-purpose hold type display panel assuring a large degree of freedom of the black data insert ratio setting and facilitating application to a display panel having various devices structures. [MEANS FOR SOLVING PROBLEMS] The output enable gates of the horizontal scan shift register are divided into M groups: {kM+1}-th gates, {kM+2}-th gates, ...{kM+M}-th gates (wherein k is an integer 0, 1, 2, ..., and M is an integer not smaller than 3) and can be opened/closed all at once in the group unit. The vertical direction control means performs control to output (M-1) image data and one black data from a source driver to a vertical signal line for each (M-1) period of horizontal scan period (H). The horizontal direction control means controls to open/close the output enable gate in each group unit, thereby evading the output competition between the image data write scan signal and the black data write scan signal.

Description

Specification

Hold type display device and parts thereof

Technical field

The present invention relates to a hold-type display device suitable for a hold-type light-emitting display panel such as a liquid crystal display panel or an organic EL display panel, and a component thereof, and more particularly, to a so-called “black insertion technology”. The present invention relates to a hold-type display device that realizes a pseudo-impulse and a component thereof.

^ Scenic technology

In recent years, in the field of large-sized liquid crystal display panels suitable for large-screen televisions and the like, various proposals have been made for the purpose of eliminating so-called “moving image blur”. The cause of “moving image blur” on the liquid crystal display panel is that when the viewpoint moves following the object in the video, the hold-type light emission is integrated into the human eye by the luminance between frames, and it depends on the jump distance between frames. It is known that image deterioration occurs. Therefore, it is considered that moving image blur can be eliminated by correcting the hold type display to the pseudo impulse type light emission using a so-called “black insertion technique”.

[0003] As a conventional black insertion technique, one frame of image data is written to a display panel in the first half of 1Z2 frame time while a gate driver and a source driver are driven by a clock at twice the speed, and the second half is used. It is known to write one frame of black data to a display panel in 1/2 frame time (for example, see Non-Patent Document 1).

[0004] It should be noted that "black data" used herein is a general term for dark to dark data used for filling and erasing image data, and is not limited to black. What?

Non-Patent Document 1: Electronic Journal Separate Volume 2003 FPD Technology Encyclopedia, p. 131, FIG. 4 (a), (b) and Description (Electronic Journal Inc. issued on March 25, 2003) Disclosure of Invention

Problems to be solved by the invention

[0005] In this conventional black insertion technology, two frames of black and image are required within one frame time. Because of the display, the black and image writing time are each half a horizontal period, so the pixel capacity cannot be fully charged during that period, resulting in lower contrast and lower image quality. It has been pointed out that they are being invited.

Here, as a result of earnest study, the present inventors have found that the writing time of black and that of an image are each half a horizontal period each, not only for image data but also for black data. This is because writing is performed sequentially on each of the horizontal pixel rows, and by using the fact that the data content is the same for black data, if writing is performed simultaneously on multiple horizontal pixel rows, multiple pixel rows can be written. The time required to write black data to the memory can be greatly reduced, and the extra time can be used to increase both the black writing time and the image writing time without significantly increasing the clock speed, and to increase the contrast. It was found that the decrease in image quality and image quality could be improved.

[0007] By the way, assuming a shift register type gate driver (horizontal scan line driving circuit) which is currently most frequently employed, sequential writing of image data to a plurality of horizontal pixel columns and a plurality of horizontal pixel columns are performed. In order to alternately execute the simultaneous batch writing of black data to the scan lines, the scan line selection data for writing the image data and the scanning line selection data for writing the black data must be set in a series of stages in the shift register. Must be realized and shifted so that they can be output to the horizontal scanning lines as scanning signals at the required timing without conflict with each other.

[0008] However, most of the shift registers built into the conventional gate driver are configured by connecting several shift register devices in series due to restrictions on a manufacturing process and manufacturing costs. In consideration of the above, in order to avoid output conflict between the scanning signal for writing image data and the scanning signal for writing black data, the scanning line selection data for writing image data and the scanning signal for writing black data are used. If the scan line selection data always moves on a different shift register device, the design freedom of the so-called “black insertion ratio” which is an important element in this kind of pseudo-impulse technology may be significantly restricted. found.

[0009] This point will be described more specifically. State transition diagrams (first state-fourth state) showing the operation of the conventional gate driver are shown in FIGS. In the figure, 9A is a good driver, G1-G256 is an output enable gate, 2-1-2-768 is a horizontal scanning line, and 3 is a left The vertical scanning lines at the end, 91A-93A are shift register devices, and 911A-931A are shift register elements in the device.

[0010] As is apparent from these figures, the gate driver 9A includes three shift register devices 91A, 92A, and 93A. Each shift register device 91A, 92A, 93A contains a device enable gate G1 G256 in addition to the shift register elements 911A, 921A, 931A. The shift register elements 911A, 921A, and 931A are connected in series outside the device, for example, via a conductor pattern on a substrate. The control input terminals of the device enable gates G1 and G256 in each device 91A, 92A, and 93A are commonly connected to each device, and then are led out to the device enable control terminals EN1, EN2, and EN3. CPV is a vertical shift clock signal, and STV is a vertical start signal. In this example, the display panel has 768 horizontal scanning lines, and the shift register elements 911A, 921A, and 931A in each device have 256 stages for storing data.

In the first state shown in FIG. 44, the first stage of the first-stage shift register element 911A includes scanning line selection data for image writing (in the figure, picture STV). 1S 2nd stage shift register element 921A has scanning line selection data for black writing (shown as STV for black in the figure; the same applies hereinafter) in the first and second stages, respectively. Is stored. In this state, the device enable control terminal EN2 of the second-stage shift register device 92A is activated (“H”) in accordance with the output of black data from the source driver (not shown) on the vertical signal line 3. When ")" is set, a scanning signal is output only to the horizontal scanning lines 2-257 and 258, and black data is written to the corresponding two horizontal pixel columns. At this time, since the device enable terminal EN1 of the first-stage shift register device is inactive ("L"), no scan signal is output to the horizontal scanning line 2-1.

In the second state shown in FIG. 45, the first stage of the first-stage shift register element 911A also receives the scanning line selection data for image writing, and the second-stage shift register element 921A In the first and second stages, scanning line selection data for black writing is stored, respectively. In this state, as the image data is output from the source driver (not shown) on the vertical signal line 3, the device enable of the first-stage shift register device 91A is performed. When the control terminal EN1 is activated ("H"), a scanning signal is output only to the horizontal scanning line 2-1 and image data is written to the corresponding one horizontal pixel column. At this time, the device enable terminal EN2 of the second-stage shift register device 92A is set to the non-active ("L") level, and the two horizontal pixel columns corresponding to the horizontal scanning lines 2-257 and 258 are black. No data is written.

In the third state shown in FIG. 46, each of the scanning line selection data is shifted by the positional force S1 stage due to the input of one vertical shift clock (CPV) force S1. That is, the second stage of the first-stage shift register element 911A receives scanning line selection data for image writing, and the second and third stages of the second-stage shift register element 921A perform scanning for black writing. Line selection data is stored. In this state, the device enable control terminal EN1 of the first-stage shift register device 91A is activated (“H”) in accordance with the output of the image data from the source driver (not shown) on the vertical signal line 3. When ")" is set, a scanning signal is output only to the horizontal scanning line 2-2, and image data is written to the corresponding one horizontal pixel column. At this time, the device enable terminal EN2 of the second-stage shift register device 92A becomes inactive ("L"), and the two horizontal pixel columns corresponding to the horizontal scanning lines 2-258 and 259 become black. No data is written.

In the fourth state shown in FIG. 47, since one more vertical shift clock (CPV) is input, the data is shifted by the position force stage of each scanning line selection data. That is, the third stage of the first-stage shift register element 911A receives scanning line selection data for image writing, and the third and fourth stages of the second-stage shift register element 921A perform scanning for black writing. Line selection data is stored. In this state, the device enable control terminal EN2 of the second-stage shift register device 92A is activated ("H") in accordance with the output of black data from the source driver (not shown) on the vertical signal line 3. ), A scan signal is output only to the horizontal scanning lines 2-259 and 260, and image data is written to the corresponding two horizontal pixel columns. At this time, the device enable pin EN1 of the first-stage shift register device 91A is set to the non-active ("L") level, and the black data is stored in one horizontal pixel column corresponding to the horizontal scanning line 2_3. Is not written.

[0015] In the example shown in Figs. 44 and 47, the output rice is output only in units of the shift register device. It is necessary to avoid that the scanning line selection data for writing black data and the scanning line selection data for writing image data are present on the same shift register device. . Therefore, a minimum of 256 stages of squashers S are required between those dots, which limits the black penetration rate to the range of 256/768 (= 33%) — 512/768 (= 66%). It is understood that it is done.

[0016] In general, the value of the black penetration rate required for each display panel is defined by the rising and falling responsiveness between white and black of the display panel, and the rising and falling responsiveness is determined. The characteristics vary considerably depending on the display panel device structure (eg, TN, IPS, MVA, ΔCB, etc.). In the black-intensity technology, the decrease in brightness due to the black intrusion on the screen is a fatal problem in image quality, so the black-in rate is improved in accordance with the difference in the response of these panels. It is necessary to reduce the brightness to the minimum that can obtain the brightness, and to suppress the brightness reduction. With the method described above, the black penetration rate is limited to the range of 33% -66%. If the insertion rate is less than 33% and it is desired to set the scanning power finer, the scanning line per gate driver The number must be reduced and the number of gate drivers must be increased, resulting in increased costs. However, if the number of gate drivers must be changed each time according to the difference in panel responsiveness, there is a problem that it cannot be practically used as a general-purpose display panel drive. .

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a hold-type display by applying a black insertion technique that does not cause a decrease in contrast or image quality. A versatile hold-type display device that can achieve pseudo-impulse of the panel, as well as securing a wide degree of freedom in setting the black insertion ratio, and that can be easily applied to display panels having various device structures. It is to provide the parts.

[0018] Another object of the present invention is to provide a hold-type display device and a component thereof capable of applying a pseudo-impulse technique to a Cs-on-gate type TFT liquid crystal display panel.

Another object of the present invention is to provide a hold-type display device capable of suppressing the occurrence of gradation even when the number of simultaneously writing black data lines is increased, and a component thereof. Is to do. [0020] Still other objects and operational effects of the present invention will be easily understood by those skilled in the art by referring to the description in the following specification.

Means for solving the problem

[0021] The hold-type display device according to the present invention includes a plurality of vertical signal lines, a plurality of horizontal scanning lines, and pixels with switches arranged corresponding to intersections of the vertical signal lines and the horizontal scanning lines. A source driver that outputs display data to each vertical signal line of the hold display panel, and a horizontal scanning line selected from the horizontal scanning lines of the hold display panel. It has a gate driver that outputs a scanning signal and a video timing control unit.

[0022] The gate driver is provided for each of a scanning shift register in which scanning line selection data for scanning signal generation is sequentially shifted in a serial direction on a series of stages, and a parallel output line of the scanning shift register. And an output enable gate for opening and closing a scanning signal to each horizontal scanning line of the display panel.

The output enable gates are {kM + 1} -th, {kM + 2} -th,...

The {kM + M} -th group (where k is an integer of 0, 1, 2, ..., M is an integer of 3 or more) is divided into M groups, each of which is a group. The enable gates can be opened and closed collectively in groups in response to control signals externally provided for each group.

[0024] The image timing control unit includes a vertical direction control unit and a horizontal direction control unit.

[0025] The vertical direction control means is configured to output (M-1) image data and one black data every period corresponding to (M-1) of the horizontal scanning period (H) of the video signal. It controls the output of display data from the source driver to the vertical signal line so that it is output from the source driver to the vertical signal line.

[0026] The horizontal direction control means includes: scanning line selection data for writing image data;

The scan line selection data for (M-1) lines is taken into the first stage of the shift register at a predetermined timing, and shifted as the display data is output from the source driver to the vertical signal line. The shift register is controlled as follows. Also horizontal When the image data is output from the source driver to the vertical signal line, only the scanning signal generated by the scanning line selection data for writing the image data is output to the corresponding horizontal scanning line. When the black data is output from the source driver to the vertical signal line, only the scan signal generated by the scan line selection data for writing (M-1) lines of black data is supported. The output enable gate is controlled to open and close in each group so that it is simultaneously output to the horizontal scanning line.

[0027] Thereby, every time (M_l) pieces of image data are written to (M_l) horizontal pixel rows, black data is simultaneously written to (M-1) horizontal pixel rows different from them. In addition to realizing a pseudo-impulse of the hold type display panel, the black penetration rate can be changed in M (M-1) H units.

According to the above configuration, every time (M−1) pieces of image data are written to (M−1) horizontal pixel rows, (M−1) horizontal pixel rows different from them are written. Simultaneous writing of black data into the image simultaneously realizes a pseudo-impulse of the hold-type display panel, and the black insertion rate can be changed in M (M-1) H units, so the black insertion technology is applied. Display panels with various device structures can achieve a high degree of freedom in setting the black insertion ratio while minimizing the reduction of contrast and image quality while achieving pseudo-no-noise. It can be easily applied to.

[0029] In a preferred embodiment of the present invention, the scan data shift register is formed by connecting a plurality of shift register devices having the same configuration in series, and is derived from each shift register device. The output enable control terminals for each gnole may be connected to each other so that the continuity of the group order of the output enable gates is maintained at a point where the shift register devices are connected in series. According to such a configuration, it is possible to further reduce the cost by promoting the standardization of the shift register device while securing versatility to various display panel devices.

In a preferred embodiment of the present invention, the hold type display panel is a Cs on Gate type TFT liquid crystal display panel, and each of (M−1) horizontal pixel columns to which black data is written simultaneously. May be separated from each other by one or more horizontal pixel columns. According to such a configuration, it is difficult to write to a plurality of continuous scanning lines. In a Cs on Gate type TFT liquid crystal display panel, it is possible to realize pseudo-impulse by the black insertion technology.

In a preferred embodiment of the present invention, the writing order of video data for each of (M−1) horizontal pixel columns may be changed for each frame. According to such a configuration, the number of lines for simultaneously writing black data or black data, which increases the writing time of black data or image data, is increased. If a gradation occurs due to the difference in the hold time, the gradation can be offset by the image data between adjacent frames.

The present invention viewed from another aspect can be understood as a drive control device for a hold-type display panel. That is, this device has a hold having a plurality of vertical signal lines, a plurality of horizontal scan lines, and a pixel with a switch disposed corresponding to each intersection of the vertical signal lines and the horizontal scan lines. Suitable for type display panel.

[0033] This device includes a source driver that outputs display data to each vertical signal line of a hold-type display panel, and scans a horizontal scan line selected from among the horizontal scan lines of the hold-type display panel. It has a gate driver for outputting a signal and a video timing control unit.

[0034] The gate driver is provided for each of a scanning shift register in which scanning line selection data for scanning signal generation is sequentially shifted in a serial direction on a series of stages, and a parallel output line of the scanning shift register. And an output enable gate for opening and closing a scanning signal to each horizontal scanning line of the display panel.

[0035] Those output enable gates are {kM + 1} -th, {kM + 2} -th,...

The {kM + M} -th group (where k is an integer of 0, 1, 2, ···, and M is an integer of 3 or more) is divided into M groups, each of which is a group. The enable gates can be opened and closed collectively in groups in response to control signals externally provided for each group.

[0036] The video 'timing control section includes a vertical direction control means and a horizontal direction control means. [0037] The vertical direction control means performs (M-1) of the horizontal scanning period (H) of the video signal. Equivalent to an individual The output of display data from the source driver to the vertical signal line is controlled so that (M-1) image data and one black data are output from the source driver to the vertical signal line for each period. Control.

[0038] The horizontal direction control means determines whether the scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are at the predetermined timing, respectively, at the first stage of the shift register. And controls the shift register so that the data is shifted in accordance with the output of display data from the source driver to the vertical signal line. Further, when the image data is output from the source driver to the vertical signal line, the horizontal direction control means switches only the scan signal generated by the scan line selection data for writing the image data to the corresponding horizontal scan line. When the black data is output from the source driver to the vertical signal line, only the scan signal generated by the scan line selection data for writing (M-1) black data is output. The output enable gates are controlled to open and close in each group so that they are output simultaneously to the corresponding horizontal scanning lines.

[0039] Accordingly, every time (M-1) pieces of image data are written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from those. By writing, pseudo-impulse of the hold type display panel is realized and the black insertion rate can be changed in M (M-1) H units.

[0040] The present invention viewed from another aspect can be understood even by a display panel with a driver.

The display panel with a driver includes a plurality of vertical signal lines, a plurality of horizontal scanning lines, and pixels with switches arranged corresponding to intersections of the vertical signal lines and the horizontal scanning lines. , A source driver that outputs display data to each vertical signal line of the hold type display panel, and a horizontal scan selected from each horizontal scan line of the hold type display panel It integrates a gate driver that outputs a run signal to the line. It should be noted that the term “integration” here includes both the case where the driver is built into the display panel by a semiconductor process and the case where the driver substrate is bonded to the display panel with an adhesive or the like.

[0042] The gate driver includes a scan shift register in which scan line selection data for scan signal generation is sequentially shifted in a serial direction on a series of stages, and a parallel shift register of the scan shift register. And an output enable gate provided on each of the output lines to open and close a scanning signal to each horizontal scanning line of the display panel.

[0043] The output enable gates are {kM + 1} -th, {kM + 2} -th,...

According to the above configuration, every time (M−1) pieces of image data are written into (M−1) horizontal pixel rows, (M−1) different horizontal pixel rows If the video's timing control unit is appropriately designed so that black data is written simultaneously to the display, and if the pseudo-no-noise of the hold-type display panel is realized, the black penetration rate will be in M (M-1) H units. It can be changed.

The present invention viewed from another aspect can be grasped as a video timing control device for a display panel with a driver.

That is, the video timing control apparatus includes a plurality of vertical signal lines, a plurality of horizontal scanning lines, and switches with switches arranged corresponding to intersections of the vertical signal lines and the horizontal scanning lines. Display panel having a pixel of the same type, a source driver for outputting display data to each vertical signal line of the hold type display panel, and a horizontal line selected from the horizontal scanning lines of the hold type display panel. And a gate driver that outputs a scanning signal to a scanning line. The gate driver sequentially shifts scanning line selection data for generating a scanning signal in a serial direction on a series of stages. A scanning shift register, and an output enable gate provided on each of the parallel output lines of the scanning shift register for opening and closing a scan signal to each horizontal scan line of the display panel. And their output enable gates are {kM + 1} -th, {kM + 2} -th,-'· · {1ζΜ + Μ} -th, (where k is 0, 1, 2, Integers and M are integers of 3 or more) are grouped into M groups, and their output enable gates correspond to control signals externally given to each group, It is compatible with a display panel with a driver that can be opened and closed collectively in units of gnolap.

[0047] The video 'timing control device includes a vertical direction control means and a horizontal direction control means. In.

[0048] The vertical direction control means determines that (M-1) pieces of image data and one piece of black data are provided for each period corresponding to (M-1) pieces of the horizontal scanning period (H) of the video signal. It controls the output of display data from the source driver to the vertical signal line so that it is output from the source driver to the vertical signal line.

[0049] The horizontal direction control means determines whether the scanning line selection data for writing image data and the scanning line selection data for the (M-1) lines for writing black data are at predetermined timings, respectively, at the first stage of the shift register. And the shift register is controlled so that the data is shifted in accordance with the output of display data from the source driver to the vertical signal line, and

When image data is output from a source driver to a vertical signal line, only a scan signal generated by scanning line selection data for writing image data is output to a corresponding horizontal scanning line. When black data is output from the driver to the vertical signal line, only the scan signal generated by the scan line selection data for (M-1) lines of black data is applied to the corresponding horizontal scan line. The output enable gate is controlled to open and close in units of each gnole so that they are output simultaneously.

[0050] Thereby, every time (M-1) pieces of image data are written to (M-1) horizontal pixel rows, black data is simultaneously written to (M-1) horizontal pixel rows different from those. By writing, the pseudo-impulse of the hold type display panel is realized, and the black insertion ratio can be changed in M (M-1) H units.

According to another aspect of the present invention, a video timing control apparatus for a display panel with a driver described above is provided.

(M-1) image data and one black data are output from the source driver to the vertical signal line for each period corresponding to (M-1) of the horizontal scanning period (H) of the video signal Vertical control means for controlling the output of the display data from the source driver to the vertical signal line,

The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively taken into the first stage of the shift register at predetermined timing, and the source driver Output data to the vertical signal line from the Control the shift register so that

When image data is output from the source driver to the vertical signal line, only the scanning signal generated by the scanning line selection data for writing image data is output to the corresponding horizontal scanning line. When the black data is output from the pixel to the vertical signal line, only the scan signal generated by the scan line selection data for writing (M-1) lines of black data is output to the corresponding horizontal scan line. Horizontal direction control means for controlling the opening and closing of the output enable gate for each gnorape so that the signals are output simultaneously.

It can be understood as an FPGA (Field Programmable Gate Array), ASIC (Application Specific IC), or ASSP (Application Specific Standard Products) that functions as a device.

Further, the present invention viewed from another aspect includes a source code for reading into a computer having a compiler function for generating and outputting a netlist indispensable for production of the above-described FPGA, ASIC, or ASSP, Alternatively, it can be understood as a recording medium in which the source code is recorded in a format that can be read by the computer.

The invention's effect

According to the display panel driving device of the present invention, every time (M_l) pieces of image data are written into (M_l) horizontal pixel columns, (M−1) horizontal pixels different from them are written. Simultaneous writing of black data to the columns realizes pseudo-innoise of the hold-type display panel, and the black penetration rate can be changed in M (M-1) H units. While applying the input technology to achieve pseudo-impulse, it is possible to minimize the reduction of contrast and image quality as much as possible. It can be easily applied to a display panel having a device structure.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below are merely a part of the present invention, and it goes without saying that the gist of the present invention is specified only by the description of the claims.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the device of the present invention. same As shown in the figure, the display panel driving device includes a TFT type liquid crystal panel 1 as a display panel, a source driver 8, a gate driver 9, and a video timing control unit 10. The source driver 8 and the gate driver 9 may be formed in the display panel 1 by a semiconductor process, or may be a substrate in which the drivers 8 and 9 are mounted on the display panel 1 with an adhesive or screws. good.

The liquid crystal panel 1 includes a pixel array in which pixels are arranged vertically and horizontally. Each pixel constituting the pixel array is provided with a thin film transistor (TFT) as a switching element. In the TFT array, the gate terminals of the TFTs belonging to each pixel column in the horizontal direction are connected to the scanning line 2, and similarly, the drain terminals of the TFTs belonging to each pixel column extending in the vertical direction are connected to the signal line 3. Have been.

FIG. 2 and FIG. 3 are explanatory diagrams showing the connection relationship between each TFT and the scanning line 2 and the signal line 3. As is well known to those skilled in the art, this type of TFT type liquid crystal panel includes a Cs on Common type and a Cs on Gate type. It has been known. Figure 2 shows the equivalent circuit diagram of the CS ON common method. In the figure, 2 is a horizontal scanning line, 3 is a signal line, 4 is a TFT, 5 is a liquid crystal capacitor, 6 is a storage capacitor, and 7 is a common electrode.

As is clear from the figure, in the CS-on-common type liquid crystal panel, one end of the liquid crystal capacitor 5 and one end of the storage capacitor 6 are connected in common, and then are connected via the TFT 4 as a switching element. Connected to each signal line 3. The other end of the liquid crystal capacitor 5 and the other end of the storage capacitor 6 are connected to a common electrode 7. Thus, in the CS “on” common type liquid crystal display panel, the liquid crystal capacitance 5 and the storage capacitance 6 are connected in parallel between the signal line 3 and the common electrode 7. Therefore, the pixel columns existing on the scanning lines N and N + 1 in contact with each other can be simultaneously driven by activating those scanning lines.

On the other hand, FIG. 3 shows an equivalent circuit diagram of the CS “on” gate system. In the drawing, the same components as those in FIG. 2 described above are denoted by the same reference numerals, and description thereof is omitted. As is clear from the figure, in the case of the CS “on” gate method, the other end of the storage capacitor 6 is not the common electrode 7, but the scan line (N− 1 1), that is, connected to the gate of TFT4. Therefore, adjacent scan lines (N, If the pixels belonging to (N + l) are to be driven simultaneously, the other end of the storage capacitor 6 belonging to the scanning line N + 1 cannot be maintained at “L”, and sufficient charge cannot be stored in the storage capacitor. No image is displayed. As a result, there arises a disadvantage that pixels belonging to two adjacent scanning lines N and N + 1 cannot be driven simultaneously. This point has been found by the present inventors through earnest research.

Returning to FIG. 1, the source driver 8 is well known to those skilled in the art without being shown, for example, a shift register that takes in and shifts a horizontal start signal (STH), A first register group for serial-parallel conversion that sequentially takes in each image data of one horizontal scanning line of an image from a video source (for example, a DVD player, a computer, a TV tuner, etc.) by a parallel output of the shift register and In response to the latch pulse (LP) at the end of each horizontal cycle, the second register group and the second register group capture the image data captured in the first register group in parallel as they are. D / A conversion that converts each of a series of captured image data into a grayscale voltage having the polarity specified by the polarity indication signal (POL) and outputs it to each of the vertical signal lines 3, 3, Instrument group Can be achieved

On the other hand, the gate driver 9 is a main part of the present invention, and has a characteristic circuit configuration. The details of the gate driver will be described later with reference to FIGS. 21 to 24.

Next, the configuration of the video timing control unit 10 will be described. As shown in FIG. 1, the video timing control unit 10 includes a scaler 11, a timing controller 12, and a black insertion circuit 13.

As is well known to those skilled in the art, the function of the scaler 11 is to match the format on the video source side with the format on the display panel side. Examples of the matching format include a screen size, a running format, and the like. A signal line group 1 la indicated by a thick arrow drawn from the scaler 11 includes various signals output from the scaler 11. These signals include, for example, RGB data (Data), a dot clock signal (DCLK), a horizontal synchronization signal (HSYNC), a vertical synchronization signal (VSYNC), and a data enable signal (DE). it can. Next, the configuration of the timing controller 12 will be described. The timing controller 12 generates a data sequence and a signal group suitable for the source driver 8 and a signal group suitable for the gate driver 9 based on various signals arriving from the scaler 11 via the signal lines 11a. . Note that, as the timing controller 12, a conventional one can be used as it is.

More specifically, the timing controller 12 synchronizes with the dot clock (DCLK) based on the horizontal synchronizing signal (HSYNC), the vertical synchronizing signal (VSYNC), and the data enable signal (DE). Then, a horizontal control signal for the source driver is generated. The horizontal control signal includes a horizontal start signal (STH), a dot clock signal (DCLK), a latch pulse (LP), a polarity designation signal (P〇L), and the like. The timing controller 12 synchronizes with the dot clock signal (DCLK) based on the horizontal synchronization signal (HSYNC), vertical synchronization signal (VSYNC), and data enable signal (DE) sent from the scaler 11. While generating, a vertical control signal for the gate driver is generated. The vertical control signal includes a vertical start signal (STV), a gate driver shift clock signal (CPV), and an output enable signal (OE) which is a main part of the present invention. The details of the vertical start signal (STV), gate driver shift clock signal (CPV), and output enable signal (OE) generated in this manner will be described later in connection with the operation description. The bold arrow 12a includes the horizontal and vertical control signals described above.

Next, the details of the black insertion circuit 13 will be described. In the following description, in order to simplify the description, the circuits in the case where the number of the output enable control signals OE is three are arranged in rows. It is also assumed that the frequency of the second dot clock (CLKN) is set to 3Ζ2 times the frequency of the first dot clock (DCLK).

The black input circuit 13 corresponds to a main part of the present invention, and inserts black into a screen displayed by data provided from an image source to simulate a hold-type display panel device. Impulse resolution solves the problem of afterimages when displaying moving images.

FIG. 4 is a block diagram showing details of the black insertion circuit. As shown in the figure, the black input circuit 13 includes a phase locked loop circuit (PLL) 131, a data generation circuit 132, , A horizontal direction control circuit 133, a vertical direction control circuit 134, and a timing adjustment circuit 135.

The phase-locked loop circuit (PLL) 131 is configured to output a first dot clock signal (DCLK) and a second dot clock signal (DCLK) based on the dot clock signal (DCLKIN) output from the timing controller 12. CLKN). Here, the frequency of the first system dot clock signal (DCLK) is set to be 1 times the input side dot clock signal (DCLKIN), and the frequency of the second system dot clock signal (CLKN) is set to the input side dot clock. MZ (M_1) times the clock signal (DCLKIN). The first system dot clock signal (DCLK) thus obtained is supplied to a data generation circuit 132 and a horizontal direction control circuit 133 provided at the subsequent stage. Similarly, the second system dot clock signal (CLKN) is supplied to each of the data generation circuit 132, horizontal direction control circuit 133, vertical direction control circuit 134, and timing adjustment circuit 135 provided at the subsequent stage. Is done.

Next, the data generation circuit 132 will be described. A block diagram showing details of the data generation circuit is shown in FIG. As shown in the figure, the data generation circuit 132 includes a FIFO (First In First Out processing) 1321, a selector 1322, a flip-flop 1323, and a black data generation circuit 1324.

[0071] The FIF01321 synchronizes the video signal (DATA) with the first system dot clock signal (DCLK) while the FIFO write enable signal (FIF) _WE) is active, and stores the internal memory (not shown) of the FIFO. ). Also, while the FIFO read enable signal (FIF__RE) is active, the video signal (DATA) is read from the memory inside the FIFO in synchronization with the second system dot clock signal (CLKN).

The black data generation circuit 1324 generates black or dark to dark color video data required for the filling process of the present invention. The selector 1322 is selectively controlled by the FIFO read enable signal delayed by the second system dot clock power S1 clock by the flip-flop 1323, and the video signal (DATA) signal read from the FIFO 321 and the black data generation time are controlled. One of the black data (BLACK) output from the path 1324 is selected and output as a video signal (DATA_bit).

Next, returning to FIG. 4, the horizontal direction control circuit 133 will be described. Horizontal control times A block diagram showing the details of the road is shown in FIG. As shown in the figure, the horizontal direction control circuit 133 includes a FIFO write enable signal generation circuit 1331, a horizontal start signal generation circuit 1332, a FIFO read enable signal generation circuit 1333, and a horizontal counter. 1334, a latch pulse signal generation circuit 1335, and a polarity designation signal generation circuit 1336.

As shown in FIG. 7, the FIFO write enable signal generation circuit 1331 includes an enable generation circuit 1331a and a counter 1331b. The counter 1331b is counted up by the dot clock signal (DCLK) and reset at the leading edge of the horizontal start signal (STH). On the other hand, the enable generation circuit 1331a includes a flip-flop (not shown) which is set to “H” at the leading edge of the horizontal start signal (STH) and reset when the count value of the counter 133 lb reaches a certain value. In. The output power of this flip-flop is output as a FIFO write enable signal (FIF〇_WE).

Next, returning to FIG. 6, the horizontal direction start signal generation circuit 1332 will be described. FIG. 8 is a block diagram showing details of the horizontal direction start signal generation circuit. As shown in the figure, the STH generation circuit 1332 includes an STH edge extraction circuit 1332a, a state circuit 1332b, a counter 1332c, an STH generation circuit (decoder) 1332d, an OR gate 1 332e, and an AND gate 1332f. — Includes h and OR gate 1332i.

The STH edge extraction circuit 1332a detects an odd-numbered rising edge of the horizontal start signal (STH) and generates and outputs a 1 CLK width pulse. The counter 1332c is controlled to count up by the dot clock signal (CLKN), and is reset by an edge detection signal output from the STH edge detection circuit 1332a. The count value (PIX_COUNT) of the counter 1332c is supplied to the STH generation circuit (decoder) 1332d. The STH generation circuit (decoder) 1332d generates and outputs a horizontal start signal (STH_bit) which is a pulse of 1 CLK width every time the count value (PIX_CIXUNT) given from the counter 1332c reaches a specific value. Further, the horizontal start signal (STH_bit) is supplied to the reset terminal of the counter 1332c and the state circuit 1332b.

Next, the state circuit 1332b will be described. The state circuit 1332b includes an edge detection signal supplied from the STH edge detection circuit 1332a and an STH generation circuit (decoder) 1332d. Based on the supplied horizontal start signal (STH-bit), three types of state signals SI, S2, SO and a blanking signal (BLANKING) are generated and output. Note that these state signals SI, S2, SO, and BLANKING become "H" when active. In this example, the state signal S1 corresponds to the first data output period, S2 corresponds to the second data output period, and SO corresponds to the black data output period. In addition, BL ANKING represents a vertical retrace interval.

[0078] The state signals SI, S2, SO and the blanking signal (BLANKING) are generated as follows. First, it is assumed that the periods corresponding to the state signals SI, S2, and SO do not overlap each other. The signals SI, S2, and SO repeatedly appear in the order of S0, SI, and S2 each time the horizontal start signal (STH_bit) arrives from the STH generation circuit 1332d. When an edge detection signal arrives from the STH edge detection circuit 1332a, setting to the SO state is always performed.

[0079] The state signal SO thus obtained is gated by the horizontal start signal (STH-bit) in the AND gate 1332h, and then output to the outside as a horizontal image start signal (STH-C1). . The state signal S1 is gated by a horizontal start signal (STH-bit) in an AND gate 1332f, and then output to the outside as a horizontal image start signal (STH-C2). Similarly, the state signal S2 is gated by the horizontal start signal (STH-bit) at the AND gate 133 2g and then output to the outside as the horizontal black start signal (STH-BLACK). . The state signal SO is output as it is as a black state signal (STATE-BLACK). Further, the horizontal start signal (STH-bit) and the state signal SO are logically ANDed by an AND gate 1332h, and then the logical sum of the horizontal image start signal (STH_C2) by the 〇R gate 13321 Is output to the outside as a horizontal image start signal (STH_COLOR).

Next, the blanking signal (BLANKING) will be described. As explained earlier, the blanking period is the vertical retrace period, and the blanking signal (BLANKING) is at the same timing when the signal (STH) and signal (STH_bit) are switched from the S2 state to the SO state. 'Η' is output if no signal arrives, and then a signal (STH) arrives The signal is output as a signal (COLOR_BLANK) as it is.

[0081] Each signal output from the STH generation circuit in this way has the following meaning.

First, the signal (STH-C1) corresponds to a start signal of image data to be written for the first time. The signal (STH_C2) corresponds to a start signal of image data to be written for the second time. The signal (STH_BLANKING) corresponds to a start signal of black data. The signal (STATE_BLACK) corresponds to a signal indicating a black data output period. The signal (COL OR_BLANK) corresponds to a signal indicating a blanking period. The signal (STH_COL @ R) corresponds to a start signal for image data. The signal (STH_bit) corresponds to a start signal for the source driver 8. FIG. 43 shows a time chart showing the operation of each signal of these STH generation circuits.

Next, returning to FIG. 6, the FIFO read enable generation circuit 1333 will be described. This circuit 1333 has a circuit configuration similar to that of the FIFO write enable generation circuit 1331 described above, and the only difference is the input / output relationship. That is, in the FIFO write enable generation circuit 1331 shown in FIG. 7, the input of the enable generation circuit 1331a is replaced with a horizontal picture start signal (STH-COLOR), and the counting clock of the counter 1331b is replaced with a dot clock signal (CLKN). By replacing the reset input of the counter 1331b with the horizontal image start signal (STH-COLOR), the FIFO read enable generation circuit 1333 can be configured as it is.

Next, returning to FIG. 6, the horizontal counter 1334 will be described. As shown in FIG. 9, the horizontal counter 1334 is a counter that counts the dot clock signal (CLKN) and is reset by a horizontal start signal (STH-bit). That is, the horizontal counter counts and outputs the number of dots in the horizontal direction, and operates in a 2HZ3 cycle. Here, H is the original horizontal scanning cycle on the video source side.

Next, returning to FIG. 6, the latch pulse generation circuit 1335 will be described. As shown in FIG. 10, this latch panelless generation circuit 1335 includes a first comparator 1335a, a second comparator 1335b, and an AND gate 1335c. The first comparator 1335a changes its output from "L" to "H" when the value of the force data of the horizontal counter becomes larger than a predetermined LP rising value. Similarly, a second comparator 1335b provides a counter from the horizontal counter. When the value of the event data becomes larger than a predetermined LP falling value, the output changes from "H" to "L". As a result, a latch pulse (LP) of a specific width having a predetermined rising timing and falling timing is output to the output side of the AND gate 1335c.

Next, returning to FIG. 6, the polarity instruction signal generation circuit 1336 will be described. Details of the polarity indication signal generation circuit 1336 are shown in FIG. As shown in the figure, this circuit includes a polarity initial state register 1336a, a polarity image register 1336b, a polarity black register 1336c, and a polarity selection circuit (selector) 1336d.

[0086] The polarity initial state register 1336a stores an initial state signal (FIRST_STATE) based on the horizontal image start signal (STH_C1) output from the horizontal direction start signal generation circuit 1332 and the image blanking signal (COLOR_BLANK). ) Is generated. That is, the polarity initial state register 1336a is a register for setting an initial value of the polarity instruction signal (P〇L), and its output signal (FIRST-STATE) is inverted at the beginning of each frame. That is, the polarity initial state register 1336a stores the first image start after the image blanking signal (COLOR-BLANK) changes from "H" to "L" (or "L" to "H"). The output is inverted only at the rising edge of the signal (STH-C1). This is because the charging polarity of each pixel is alternately inverted for each frame.

[0087] The polarity designation picture register 1336b includes an initial state signal (FIRST-STATE) obtained from the polarity initial state register 1336a, a horizontal picture start signal (STH-C1), and a horizontal picture start signal (STH-C2). And an image blanking signal (COLOR-BLANK), and generates an image polarity designation signal (POL-C). In other words, the polarity designation image register 1336b stores the rising edge of the first horizontal image start signal (STH_C1) after the image blanking signal (C〇LOR_BLANK) power S changes from “H” to “L”. The initial state signal (FIRST_STATE) is read only by the edge signal, and the content of the image polarity designation signal (POL_C) is inverted each time the horizontal image start signal (STH_C2) arrives.

[0088] The polarity designation black register 1336c includes an initial state signal (FIRST STATE) output from the polarity initial state register 1336a and a horizontal black start signal (STH BLACK). And a black direction designation signal (POL-B) based on the vertical black start signal (STV-BLACK). That is, the polarity designation black register 1336c reads the state of the initial state signal (FIRST-STATE) at the rising edge of the horizontal direction black start signal (STH-BLACK). Then, each time the horizontal black start signal (STH_BLK) arrives, its output is inverted.

[0089] The polarity designation select circuit (selector) 1336d is composed of the image polarity signal (P〇L_C) output from the polarity designation image register 1336b and the black polarity designation signal (POL_B) output from the polarity designation black register 1336c. Select one of these, and output this to the outside as a polarity designation signal (PbitL_bit). This selection switching is controlled by a black state signal (STATE_BLACK) indicating that black writing is being performed. That is, when the black state signal (STATE_BLACK) is “L”, the image polarity designation signal (P〇L_C) is selected, and when it is “H”, the black polarity designation signal (POL_B) is selected.

Next, returning to FIG. 4, the vertical direction control circuit 134 will be described. The vertical control circuit 134 generates five signals (CP signals) based on a dot clock signal (CLKN) obtained from the PLL 131 and a horizontal start signal (STH-bit) obtained from the horizontal control circuit 133. Generate and output V_bit, STV_bit, OEl_bit, OE2_bit, 〇E3—bit).

FIG. 12 is a block diagram showing details of the vertical direction control circuit. As shown in the figure, the vertical control circuit 134 includes an edge detection circuit 1341, a dot counter 1342, a vertical shift clock generation circuit 1343, a vertical start signal generation circuit 1344, and an output circuit. Enable generation circuit 1345.

[0092] The edge detection circuit 1341 includes three types of edge detection units, as shown in detail in FIG. The first edge detection unit includes a first D-type flip-flop 1341a, a second D-type flip-flop 1341b, and an AND gate 1341c. The second edge detection unit includes a first D-type flip-flop 1341d, a second D-type flip-flop 1341e, and an AND gate 134 #. The third edge detection unit is provided with a first D-type flip-flop 1341g, a second D-type flip-flop 1341h, and two AND gates 1341i and 1341j.

[0093] The first edge detector detects the rising edge of the horizontal start signal (STH bit). Detects and outputs a horizontal direction start signal rising edge detection signal (STH-H-DETECT) which is a pulse signal of 1CLK width. The second edge detector detects the rise of the vertical shift clock signal (CPV-bit) and generates and outputs a vertical shift clock rise detection signal (CPV_H_DETECT), which is a pulse signal of 1 CLK width. Power. The third edge detector detects both the rising and falling edges of the vertical shift internal clock, and outputs the vertical shift internal clock fall detection signal (INT_CPV_L_DETECT) and the vertical shift internal clock rise detection signal. (INT_CPV_H_DETECT).

Next, returning to FIG. 12, the dot counter 1342 will be described. As shown in FIG. 14, the dot counter 1342 counts the dot clock signal (CLKN) and is reset by the rising edge detection signal (STH_H_DETECT) of the horizontal start signal, and the count value is equal to the horizontal period count signal (H_PERI〇). D_C〇UNT). That is, this dot counter 1342 is a counter that moves in 2H / 3 cycles, and the counting operation is performed up to the number of dots in the horizontal direction (including the blanking period).

Next, returning to FIG. 12, the vertical shift clock generation circuit 1343 will be described. Details of the vertical shift clock generation circuit 1343 are shown in FIG. As shown in the figure, the circuit 1343 includes a first comparator 1343a, a second comparator 1343b, an AND gate 1343c, a counter 1343d, a data 1343e, and an AND gate 1343f. Is included.

[0096] When the value of the horizontal period count signal (H-PERIOD-COUNT) reaches a predetermined CPV rising value, the output of the first comparator 1343a changes from "L" to "H". When the value of the horizontal period count signal (H_PERIOD_COUNT) reaches a predetermined CPV falling value, the output of the second comparator 1343b changes from “H” to “L”. Therefore, the output side of the AND gate 1343c has a width corresponding to the difference between the CPV rising value and the CPV falling value in response to the value of the horizontal period count signal reaching the CPV rising value ^. Generates and outputs the internal clock signal for vertical shift (INT_CPV), which is a pulse. In other words, a clock pulse having a predetermined pulse width repeatedly appears at a cycle of 2H / 3 in the vertical shift internal clock signal. [0097] The counter 1343d is a so-called ternary counter, and sequentially and repeatedly outputs count values "0", "1", and "2". In other words, the counter 1343d has its count operation enabled by the falling edge detection signal (INT-CPV-L-DETECT) of the vertical shift internal clock, and the dot clock signal (CLKN) only during the enable state. Count up. As a result, "0", "1", and "2" are repeatedly output to the output side of the counter 1343d in 2H / 3 cycles.

[0098] The decoder 1343e decodes only one of the three values output from the counter 1343d, and outputs "H" to its output side. As a result, on the output side of the AND gate 1343f, the vertical shift clock signal (CPV_bit), which is a signal obtained by masking one of the three pulses among the pulses appearing in the vertical shift internal clock signal, is output. Generated and output.

Next, returning to FIG. 12, the vertical shift start signal generation circuit 1344 will be described. FIG. 16 is a block diagram showing details of the vertical shift start signal generation circuit. As shown in the figure, the circuit 1344 includes a first comparator 1344a, a second comparator 1344b, an AND gate 1344c, a line counter 1344d, an image data 1344e, and a black decoder I 344f. AND gate 1344g, AND gate 1344h, and OR gate 1344i.

[0100] The first comparator 1344a changes its output from "L" to "H" when the value of the horizontal period count signal (H-- PERIOD-- COUNT) reaches a predetermined falling value of the vertical start signal. Changes to When the value of the horizontal period count signal (H—PERIOD—COUNT) reaches a value corresponding to the falling value of the vertical start signal, the output of the second comparator 1344b changes from “H” to “L”. . Therefore, the output side of the AND gate 1344c has a predetermined pulse width determined by the value of the STV rising value and the STV falling force S in response to the rising of the horizontal period count signal (H_PERI〇D_C〇UNT). A pulse signal is generated and output.

[0101] The line counter 1344d is a counter that counts the number of horizontal lines. The count enable is controlled by the clock rise detection signal (CPV_H_DETECT) for the vertical shift, and only when the count operation power is enabled. Counts the dot clock signal (CLK N). In other words, this line counter 1344d It counts up at the rising edge of the clock rising detection signal (CPV-H-DETECT) and is reset at the maximum number of horizontal lines. As a result, numerical data corresponding to the number of lines of the image being scanned is output to the output side of the line counter 1344d. This numerical data is supplied in parallel to the image decoder 1344e and the black decoder 1344f.

[0102] The image decoder 1344e outputs "H" when the count value of the line counter 1344d is a count value corresponding to a specific line. Similarly, the black decoder 1344f also outputs "H" when the count value of the line counter 1344d corresponds to a specific line. The decoded output of the image decoder 1 344e is supplied to an AND gate 1344g, and the decoded output of the black decoder 1344f is supplied to an AND gate 1344h. Therefore, the pulse signal output every horizontal cycle from the AND gate 1344c is gate-controlled by the AND gates 1344g and 1344h. As a result, the output side of the OR gate 13441 has a vertical start signal (STV_bit) to be given to the gate driver. Is generated, and at the same time, a vertical black start signal (STV-BLK) is generated and output from the output side of the AND gate 1344h.

Next, returning to FIG. 12, the output enable generation circuit 1345 will be described. FIG. 17 is a block diagram showing details of the output enable generation circuit. As shown in the figure, this circuit 1345 includes an l_tt comparator 1345a, a second_tt comparator 1345b, an AND gate 1345c, a counter 1345d, and a selector 1345e.

[0104] The first comparator 1345a changes its output from "L" to "H" when the count value of the horizontal period count signal (H-PERIOD-COUNT) reaches a predetermined OE rising value. Change. Similarly, when the count value of the horizontal period count signal (H—PERIOD—COUNT) reaches a predetermined ΔE falling value, the second comparator 1345b changes its output from “H” to “L”. Change. As a result, at the output side of the AND gate 1345c, the value of the horizontal period count signal (H_PERI〇D_COUNT) reaches the 〇E rising value and is defined by the difference between the 〇E rising value and the 〇E falling value. The internal output enable signal (INT_〇E), which is a pulse signal having a pulse width, is output. This internal output enable signal (INT_〇E) is supplied to the selector 1345e.

[0105] On the other hand, the counter 1345d is configured to detect the rising edge of the internal clock pulse

Count enabled by (INT CPV H DETECT) and enabled The dot clock signal (CLKN) is counted only when. More specifically, the counter 1345d is configured as a 9-value counter that repeatedly outputs “0”-“8” as the count value.

The selector 1345e has an internal output enable signal (INT_〇E) as an input signal and three output enable signals (〇El_bit, 〇E2_bit, 〇E3_bit) as output signals. The selector 1345e has a built-in selector function for assigning the internal output enable signal (INT_OE) to one of the nine combinations of these three output lines. It is controlled by nine types of count values “0” and “8” obtained from the counter 1345d.

For example, in the case of the first embodiment, the relationship between the count value of the counter 1345d and the output enable signals (OEl_bit, OE2_bit, OE3_bit) is as follows.

[1] When the count value is "0"

OEl_bit = "H", OE2_bit = INT_OE, OE3_bit = INT_OE

[2] When the count value is "1"

OEl_bit = INT_OE, OE2_bit = "H", OE3_bit = "H"

[3] When the count value is 2

OEl_bit = "H", OE2_bit = INT_OE, OE3_bit = "H"

[4] When the count value is "3"

OEl_bit = INT_OE, OE2_bit = INT_OE, OE3_bit = "H"

[5] Count value 4

OEl_bit = "H", OE2_bit = "H", OE3_bit = INT_OE

[6] When the count value is 5

OEl_bit = INT_〇E, OE2_bit = "H", OE3_bit = "H"

[7] When the count value is 6 ”

OEl_bit = INT_〇E, OE2_bit = "H", OE3_bit = INT_OE

[8] Count value 7

OEl_bit = "H", OE2_bit = INT_OE, OE3_bit = "H"

[9] In case of count value S "8" OEl_bit = "H", OE2_bit = "H", OE3_bit = INT_OE

Next, returning to FIG. 4, the timing adjustment circuit 135 will be described. The basic functions of the timing adjustment circuit 135 are as follows: data mixed with black (DATA_bit) output from the data generation circuit 132, various signals (POL_bit, LP_bit, STH_bit) output from the horizontal control circuit 133, By adjusting the phases of various signals (SPV_bit, STV_bit, 〇El_bit, OE2_bit, OE3_bit) output from the vertical direction control circuit 134 by clock synchronization using a group of D-type flip-flops, the Group (D ATA_0, POL_〇, LP_0, STH_〇) and a group of signals to the gate driver 9 (C PV_〇, STV_〇, 〇E1_0, OE2_〇, OE3_0) . The signal group thus obtained is sent out to the source driver 8 and the gate driver 9, and contributes to the black insertion operation for pseudo-impulse according to the present invention.

Next, the internal configuration of the gate driver 9 which is a main part of the present invention will be described in detail with reference to FIGS.

As shown in FIGS. 21 to 24, the gate driver 9 includes three semiconductor devices 91, 92, 93. Each of the semiconductor devices 91, 92, and 93 has a built-in shift register element 911, 921, and 931 having an IJ256 stage. These shift register elements 911, 921, and 931 are connected in series with each other via a pattern on a substrate connecting the devices, thereby forming a shift register having 768 stages in series. Each shift register element 911, 921, 931 has 256 c. Raler output lines are provided. Output enable gates Gl, G2-G256 are provided for each of the 256 normal output lines of each shift register element 911, 921, 931.

[0110] The gates Gl, G2, and G256 are divided into three gnorapes, which are a first group, a second group, and a third group. More specifically, when k is an integer of 0, 1, 2,..., The (3k + l) th gates Gl, G4, G7, G10 ′,... Belong to the first group. Similarly, the (3k + 2) th gates G2, G5, G8, Gl 1 · · · belong to the second group. In addition, the (3k + 3) th gate G3, G6, G9, G12 '"belongs to the third group. A series of gates Gl, G4, G7, GIO" belonging to the first group are controlled. The input is connected to the inside of the device 91, and is led out to the external terminal OE1. Similarly, the control input terminals of the gates G2, G5, G8, and Gil '''belonging to the second group are connected to the external terminal OE2 after being commonly connected in the device. Similarly, the control inputs of the gates G3, G6, G9, and G12 '''belonging to the third group are also commonly connected in the device, and are then led out to the external terminal OE3.

On the other hand, each output line of a series of gates Gl, G2—G256 in each of the devices 91, 92, and 93 is led out from each of the devices 91, 92, and 93 to the scanning lines 2—1, 2 -2, '····· 2_768 connected. Therefore, according to the gate driver 9 including these three devices 91, 92, and 93, the first common line, the second group common line, and the third common line that are derived in the device are appropriately connected. By activating these common connection lines at appropriate timing, the black data or image data of each stage of the shift register elements 911, 921, and 931 can be selectively led out to the outside in units of gnorape. It is possible to do this.

Note that the shift register devices 91, 92, and 93 constituting the gate driver shown in FIGS. 21 to 24 have the same circuit configuration from the viewpoint of reducing manufacturing costs. That is, each of shift register elements 911, 921, and 931 has 256 stages, and output enable gates G1 to G256 included in each are divided into three groups. Moreover, the (3k + l) (where k is an integer of 0, 1, 2,...) Th output enable gate (Gl, G4, G7 '.') Belongs to the first group, and the (3k + 2) th output enable gate The group order is determined so that the group of (2) belongs to the second group, and the (3k + 3) -th group belongs to the third group.

[0113] In order to realize the operation required for the present invention, it is necessary that this gnorape sequence be continuous over the entire series of shift register elements 911, 921, 931. However, since the last gate G256 of the first-stage shift register element 911 belongs to the first group, and the first gate G1 of the second-stage shift register element 921 belongs to the first group, if the devices 91, 92, When the common terminals derived from 93 are connected to each other in the first group, the continuity of the gnorape is lost at the connection between the first-stage shift register element 911 and the second-stage shift register element 921. I will. Therefore, in this example, the first shift The first group common line derived from the register device 91 is the second group common line derived from the second-stage shift register device 92 and the third group common line derived from the third-stage shift register device 93. Are connected to a common line. The second group common line derived from the first-stage shift register device 91 is the first group common line derived from the second-stage shift register device 92 and the third-stage shift register device. It is connected to the third group common line derived from 93. Furthermore, the third group common line derived from the first stage shift register device 91 is the second group common line derived from the second stage shift register device 92 and the third stage shift register device. It is connected to the first group common line derived from chair 93. By doing so, the repetition of the group order of the output enable gates is maintained over the entire three shift register elements 911, 921, 931.

In the present invention, as will be described in detail later, the connection relationship of the first, second, and third group common lines derived from each of the devices 91, 92, 93, and the vertical start signal (STV —0), the appearance timing of black writing data and image writing data, the timing of appearance of black data or image data from the source driver 8, and the clock included in the vertical shift clock signal (CPV— PV) Devise the appearance timing of the pulse and the enable timing of the output enable signals (OEl-〇, 〇E2-O, OE3-〇) applied to each of the first, second, and third group common lines. By adding them, on a series of shift register elements 911, 921, 931, data for black writing (scanning line selection) and image writing (scanning line selection) are separated by an arbitrary distance beyond the boundary between devices. Both data and By shifting them occasionally and sending them to the scanning lines without competing with each other, it is possible to perform black writing to each pixel row while suppressing a reduction in image writing time, and to realize a pseudo-innocable which can be practically used. ^ This is to realize a less-less method.

[0115] That is, as shown in FIG. 21, in the first state, temporarily, in the first state, the first stage of the shift register element 911 has the image writing data force, and the 251 and 252 stages have the black writing data. Are assumed to exist.

[0116] However, the image write data and the black write data are distinguished for the sake of convenience, and in practice, both are gate drive signals as vertical start signals (STV #). Input to the server. Further, in this first state, it is assumed that black data is transmitted from the source driver 8 to the signal line 3. At this time, when the output enable signal OE1〇 is inactive and 〇E2—O and OE3〇 are activated as shown by the thick line in the figure, the gate G1 is closed and the gates G251 and G252 are opened. As a result, only two black writing data are sent out to the scanning lines 2-251 and 2-252, and as a result, only the scanning lines 2-251 and 2-252 are selected as indicated by the black circles in the figure. Then, black is written simultaneously to two adjacent horizontal pixel columns.

As shown in FIG. 22, in the second state, image data is sent out to the signal line 3 from the source driver. At this time, ΟΕ1_〇 is active, and 〇E2_0 and 〇E3_O are all inactive. Further, at the time of transition from the first state to the second state, no shift pulse appears in the clock signal for vertical shift (CPV_〇). In the second state, the gate G1 is open, and the gates G251 and G252 are closed. Therefore, the image write data stored in the first stage of the shift register element 911 is output to the scanning line 2-1 as a scanning signal, whereas the data for the image writing data is output to the 251 and 252 stages of the shift register element 911. The stored image writing data is not output to the scanning lines 2-251 and 2-252. Therefore, in the second state, image data is written only to the horizontal pixel column corresponding to the scanning line 2-1 as indicated by a white circle in the drawing.

As shown in FIG. 23, in the third state, image data is output to signal line 3. The output enable signals {E1-O and OE3-} are non-active, and OE2-- is active. Further, at the time of transition from the second state to the third state, one shift pulse appears in the clock signal for vertical shift (CPV-0). Therefore, the image write data existing in the first stage of the shift register element 911 is shifted to the second stage, and at the same time, the two black write data existing in the 251st stage and the 252th stage are The stage has been shifted to stages 252 and 253. At this time, the gate G2 is open, and the gates G252 and G253 are closed. Therefore, in the third state, the image writing data stored in the second stage is sent out to the scan line 2-2, whereas the black writing data stored in the 252th stage and the 253th stage is transmitted. Data is not output to scan lines 2-252 and 2-253. As a result, this In the third state, as shown by white circles in the figure, image data is written only to horizontal pixel columns and pixel rows corresponding to the scanning line 2-2.

[0119] As shown in FIG. 24, in the fourth state, black data is sent out to the signal line 3. Output enable signals 〇E1_0 and 〇E2_0 are active, and OE3_〇 is inactive. In the transition from the third state to the fourth state, one shift clock appears in the vertical shift clock signal. Therefore, the image write data that existed in the second stage of the shift register element 911 up to that point goes to the third stage, and the two black write data that existed in the 252th stage and the 253rd stage have the 253rd and 253rd stages. It has been shifted to 254 stages. Gate G3 is closed, and gates G253 and G254 are open. Therefore, in the fourth state, the image write data existing in the third stage is not output to the scanning line 2_3. The black writing data existing in the 253rd stage and the 254th stage are sent to the scanning lines 2-253 and 2-254. Therefore, in the fourth state, as shown by the black circles in the figure, black data is written in only two horizontal pixel columns corresponding to the scanning lines 2-253 and 2-254.

As described above with reference to FIGS. 21 to 24, in the present invention, the gate driver 9 having a specific circuit configuration is used, and the gate driver 9 is used for the vertical start signal (STV_〇), By appropriately controlling with three output enable signals (により E1 適宜 O, OE2〇〇, OE3〇〇) and a clock signal for vertical shift (CPV—O), the shift register element of the same device 91 is controlled. While the image writing data and the black writing data are mixed in the 911, it is possible to selectively output them to the corresponding scanning line, and by using this, the existence of the image writing data Existence of black stage data and black writing data While setting the distance between the black stage and the black stage ratio arbitrarily, image data writing for each line and simultaneous black writing for multiple lines are performed alternately Sa , It is possible to realize a pseudo-impulse-control by black writing for the purpose.

[0121] That is, as described in the conventional example above, if black writing is to be performed on the screen while alternately repeating simultaneous writing of a plurality of lines and image writing a plurality of times for each line, The distance between the image writing line and the black writing line is the maximum line of one device For example, the number must be at least 256 lines apart. This has the very practical disadvantage of being able to meet the black insertion rate requirement only in the 33% -66% range. As is well known to those skilled in the art, the black insertion ratio at the time of black writing varies depending on the device characteristics of the display panel, and it is not practical to limit this to a range of 33% to 66%. It is a big obstacle. On the other hand, according to the present invention, only the three output enable signals (〇1_〇, OE2_0, 〇E3_0) shown in FIGS. It is possible to change it arbitrarily, and it is possible to significantly improve the degree of freedom of the black penetration rate and the luminance as compared with the case of using a gate driver that cannot perform active Z non-active control in the conventional device unit. It can respond flexibly to the suppression of the decline.

Next, a specific operation of the above-described display panel driving device will be described in detail with reference to FIGS. 25 and 39. In the display panels shown in these figures, for the sake of convenience of description, the vertical scanning period is set to 24 lines, of which four lines, each consisting of 21 lines and 24 lines, are set as the retrace period.

FIGS. 25 to 27 show time charts (No. 1 to No. 3) showing the operation of the source driver and the gate driver in the first embodiment. In the first embodiment, the format of the liquid crystal display panel is Cs on Common, three signals (CommonE1-O, OE2-〇, OE3-〇) as the output enable signal, and the source A clock frequency of 3/2 times is adopted.

In FIG. 25-FIG. 27, the waveform (DATA) described at the top corresponds to 48-bit video data input to the black insertion circuit 13 shown in FIG. On the other hand, in these figures, the waveform (DATA_〇) described in the second row corresponds to the black-inserted display data (DATA_〇) output from the black input circuit 13 shown in FIG. Equivalent to. As is clear from comparison of these two waveforms, one black data and two pieces of image data are output in 2H / 3 cycles during a period of 2H of data from the image source. Thus, the display data (DATA_〇) for which the black input has been output from the black input circuit 13 is sent to the source driver 8 shown in FIG.

[0125] In the source driver 8, display data is shifted by a dot clock. The data is sequentially fetched into a first register group (not shown) by a horizontal start signal (STH-O), and data for one horizontal line is held. Then, based on a latch pulse (LP-O), data for one horizontal line is obtained. The data is taken into a second register group (not shown). At the same time, the display data read in the second register group is converted into a gray scale voltage by a D / A converter (not shown), and then output from the source driver 8 to each signal line 3. Is done. The source driver output described in the fourth row from the top in the figure indicates the output on the scanning line 3.

On the other hand, the gate driver 9 performs a predetermined control operation based on the five signals (CPV_ 5, STV_0, ΟΕ1_〇, OE2_0, 〇E3_0) as described above. I will. That is, in this example, a signal for vertical shift is output to the signal (CPV_〇) in accordance with the timing at which data is output from the source driver. However, among the timings at which data is output from the source driver, at the timing at which image data is output next to the timing at which black data is output, a missing pulse is observed. As described later in detail, this is a device for writing image data and black data to continuous lines without fail. In this example, an image writing pulse and a black writing pulse appear in the signal (STV-〇) at a predetermined time interval. In this example, the pulse width of the image writing pulse is set to approximately 2H / 3, and the pulse width of the black data writing pulse is set to approximately 4H / 3.

The operation shown in this time chart can be divided into nine states defined by three output enable signals (OE1-〇, 1E2-0, OE3-0). The relationship between each state and the combination of the signals OE1—〇1 OE3—〇 is as follows.

[First state]

ΟΕ1_〇 (non-active), OE2_〇 (active), 〇E3_0 (active)

[2nd state]

ΟΕ1_〇 (active), 〇E2_〇 (non-active), 〇E3_0 (non-active)

[3rd state]

ΟΕ1_〇 (non-active), OE2_〇 (active), 〇E3_0 (non-active)

[4th state]

OE1 アクティブ (active), 〇E2 〇 (active), 〇E3 0 (non-active) [5th state]

ΟΕ1_〇 (non-active), OE2_〇 (non-active), 〇E3_〇 (active)

[6th state]

ΟΕ1_〇 (active), 〇E2_〇 (non-active), 〇E3_0 (non-active)

[7th state]

ΟΕ1_〇 (active), 〇E2_〇 (non-active), 〇E3_0 (active)

[8th state]

ΟΕ1_〇 (inactive), OE2_〇 (active), 〇E3_0 (inactive)

[9th state]

ΟΕ1_〇 (non-active), OE2_〇 (non-active), 〇E3_〇 (active) Among the active states described above, colored is black active and uncolored is active. It is. When 〇E1_0 is active, the (3k + 1) th line can be output. 〇E2— When O is active, the (3k + 2) th line can be output. When OE3—〇 is active, the (3k + 3) th line can be output. Also, in the first state where the vertical start signal (STV-O) is input as appropriate and the black data is output from the source driver, the image write data is in the stage corresponding to the first line, It is assumed that write data is held in the stages corresponding to the eleventh and twelfth lines, respectively. Further, when shifting from the second state, the third state, the fifth state, the sixth state, the eighth state, and the ninth state to the next state, a vertical shift clock is input. .

As described above, intermittently dropping the pulse of the vertical shift clock is a device for writing image data and black data to continuous lines as described above. Assuming that there is no missing pulse, an image is written on the second line, black is written on the 13th and 14th lines, and then a pulse is input, so that data for scanning line selection is obtained. Shifts to the stage corresponding to the fourth line, and writing of image data to the third line is lost. In order to prevent the loss of writing of image data as shown in this example, at the timing of outputting the image data following the timing of outputting the black data, the pulse of the clock for vertical shift is used. Let it be missing. [0129] Assuming the above, in the first state in which black data is output from the source driver, only the eleventh and twelfth lines are selected, and the horizontal pixel columns corresponding to those two lines are selected. On the other hand, black data is written. In the second state in which the image data “1” is output from the source driver, only the first line is selected, and the image data is written to the horizontal pixel column corresponding to the first line. In the third state where the second image data “2” is output from the source driver, only the second line is selected, and the image data “2” is written to the horizontal pixel column corresponding to the second line. Is performed. In the fourth state in which black data is output from the source driver, only the thirteenth and fourteenth lines are selected, and black data is written to the horizontal pixel columns corresponding to those two lines. In the fifth state where the third image data “3” is output from the source driver, only the third line is selected, and the third image data “3” is output to the horizontal pixel row corresponding to the third line. 3 ”is written. In the sixth state in which the fourth image data “4” is output from the source driver, only the fourth line is selected, and the fourth image is output to the horizontal pixel row corresponding to the fourth line. Data “4” is written. In the seventh state in which black data is output from the source driver, only the fifteenth and sixteenth lines are selected, and black data is written into the horizontal pixel columns corresponding to those two lines. In the eighth state in which the fifth image data “5” is output from the source driver, only the fifth line is selected, and the fifth pixel data “5” is output to the horizontal pixel column corresponding to the fifth line. Is written. In the ninth state where the sixth image data “6” is output from the source driver, only the sixth line is selected, and the sixth image data is output to the horizontal pixel row corresponding to the sixth line. "6" is written.

When a predetermined timing comes during the repetition of the first state to the ninth state, a start pulse for writing black data appears in the signal (STV_〇). In this example, the pulse width of the start pulse for writing black data is set to about 4HZ3. This is to ensure that the data for black writing is read into two consecutive stages of the shift register in response to the two pulses that appear in the signal (CPV_〇) (see Figure 26).

[0131] As described above, simultaneous writing of black data on two consecutive lines and simultaneous writing of black data on two consecutive lines are performed. In order to continue the operation of alternately writing image data for each line without conflict, the total number of display lines (20 in this example) and the number of lines in the retrace period (4 in this example) The sum (24 in this example) must be set to be a multiple of 6. This is because the first to ninth states described above are completed every 6H.

Next, a time chart (No. 1 to No. 3) showing the operation of the source driver and the gate driver in the second embodiment is shown in FIG. 28 and FIG. The difference between the second embodiment and the first embodiment is that the input timing of the black writing start pulse is different. That is, in the first embodiment shown in FIG. 26, the signal (CPV_C) is synchronized with the timing at which the 14th data is output from the source driver and the timing at which the subsequent black data is output. Two consecutive noises appear in 〇). Also, in order that black writing data can be sent to the shift register at the rising of these two pulses, a pulse having a pulse width corresponding to an appearance period of the two clock pulses is used as a black writing start signal (STV). — Appears in o).

On the other hand, in the case of the second embodiment, as shown in FIG. 30, especially, the appearance timing of the start pulse for black writing is delayed by 6H. More specifically, in the case of the second embodiment, two pulses are applied to the signal (CPV-O) in accordance with the output timing of the twentieth image data and the subsequent black data from the source driver. Appears in Further, a start pulse for writing black data having a width of about 4H / 3 appears in the signal (STV-〇) so as to be read by these two consecutive noises. As a result, the difference between the timing at which black is written to a certain line and the timing at which an image is written is reduced as compared with the case of the first embodiment, thereby reducing the black insertion rate. In this way, by delaying the appearance timing of the black writing pulse every 6H, the black penetration rate for the image can be freely changed.

Next, FIG. 31 and FIG. 33 show time charts (No. 1 to No. 3) showing the operation of the source driver and the gate driver in the third embodiment. The difference between the third embodiment and the first and second embodiments described above is that the output enable signal is increased from three to four. That is, in the third embodiment, four output enable signals including signals ({E1_0, OE2_0, OE3}, OE4 O) are provided. this Accordingly, the 16 states consisting of the first to the 16th are repeatedly set by the combination of the output enable signals. That is, when the signal OE11 is active, the (4k + l) th line can be output. When the signal OE2-〇 is active, the (4k + 2) th line can be output. When the signal _E3_0 is active, the (4k + 3) th line can be output. When signal OE4_〇 is active, the (4k + 4) th line is active.

[0135] Regarding the relationship between the data (DATA) from the video source and the output data (DATA_0) from the black input circuit, one black data and three pieces of image data are within the 3H period. Input to the source driver. As a result, one black data and three image data are output from the source driver to each signal line within a period of 3H.

[0136] Further, the vertical start signal (STV_〇) is appropriately input, and in the first state in which the black data is output from the source driver, the image writing data is transferred to the stage corresponding to the first line. It is assumed that the black writing pulse is held in the stages corresponding to the tenth, eleventh, and twelfth lines, respectively. Further, from the second state, third state, fourth state, sixth state, seventh state, eighth state, tenth state, eleventh state, twelfth state, fourteenth state, fifteenth state, and sixteenth state When shifting to the next state, the clock for vertical shift shall be input.

[0137] In the first state, only the tenth, eleventh, and twelfth lines are selected, and black data is written to three horizontal pixel columns corresponding to those lines. In the subsequent second state, only the first line is selected, and the first image data "1" is written to the horizontal pixel column corresponding to the first line. In the subsequent third state, only the second line is selected, and image data is written to a horizontal pixel column corresponding to the second line. In the subsequent fourth state, only the third line is selected, and the third image data "3" is written only in the horizontal pixel row corresponding to the third line. In the subsequent fifth state, only the thirteenth line, the fourteenth line, and the fifteenth line are selected, and black data is written in a horizontal pixel row corresponding to those lines. In the subsequent sixth state, only the fourth line is selected, and the fourth pixel data “4” is written to the horizontal pixel row corresponding to the same line. In the subsequent seventh state, only the fifth line is selected, and the horizontal pixel corresponding to the same line is selected. The fifth image data "5" is written to the column. In the subsequent eighth state, only the sixth line is selected, and the sixth image data “6” is written in the horizontal pixel row corresponding to the sixth line. In the subsequent ninth state, only the 16th, 17th, and 18th lines are selected, and black data is written in the horizontal pixel columns corresponding to those lines. Subsequently, in the tenth state, only the seventh line is selected, and the seventh image data “7” is written to the horizontal pixel row corresponding to the selected line. In the subsequent eleventh state, only the eighth line is selected, and the eighth image data “8” is written to the horizontal pixel column corresponding to the eighth line. In the twelfth state, only the ninth line is selected, and the ninth image data “9” is written to the horizontal pixel row corresponding to the ninth line. In the following thirteenth state, only the nineteenth and twentieth lines are selected (the twenty-first line is not displayed during the blanking period), and black data is written to the horizontal pixel column corresponding to the same line. Done. In the fourteenth state, only the tenth line is selected, and the tenth image data “10” is written in the horizontal pixel row corresponding to the tenth line. In the subsequent fifteenth state, only the eleventh line is selected, and the eleventh image data “11” is written in the horizontal pixel row corresponding to the eleventh line. In the sixteenth state, the twelfth line is selected, and the twelfth image data “12” is written in the horizontal pixel column corresponding to the twelfth line. Thereafter, similarly, the 1st to 16th states are repeatedly executed.

According to the third embodiment, by increasing the output enable signal by one system, the write time per line becomes 3H / 4, which is smaller than the case of the first and second embodiments. And the writing time of the image data and the black data increases. By increasing the writing time, it is possible to suppress a decrease in the image data writing time due to insertion of black data. Also, in this example, since three lines of black are written at the same time, the width of the pulse for black writing appearing in the signal (STV_〇) is smaller than in the first and second embodiments. And wider. In this example, the width of the black writing pulse is set to about 2H. This is because black writing data is read into three consecutive stages of the shift register in response to the three panels appearing on the signal (CPV_〇) (see Figure 26).

When comparing the first and second embodiments with the third embodiment, as described above, the output enable There is a difference in the number of signal signals (OE). Here, a general relational expression between the number of output enable signals and the writing time of black or picture is obtained. Assuming that the number of OE systems is M, the writing time is {(M-1) H} / M (assuming that the image and black writing times are the same). The cycle of each state generated by the combination of 〇E can be expressed as 1 ^ (1 ^ _1) 1 ^. Therefore, the black penetration rate can be arbitrarily changed in increments of M (M-1) H, and compared to the conventional example using a gate driver that can be changed only in shift register device units. The degree of freedom for change can be increased.

[0140] As described above, in order to maintain the repetition cycle of simultaneous black writing of a plurality of lines and image writing of each line of the plurality of lines according to the present invention, the number of display scanning lines must be reduced. The sum with the number of lines included in the flyback period is preferably a multiple of M (M-1).

Next, FIGS. 34 to 36 show time charts (No. 1 to No. 3) showing the operation of the source driver and the gate driver in the fourth embodiment. The difference between the fourth embodiment and the first to third embodiments described above is that a Cs on Gate type TFT liquid crystal panel is used as the display panel.

[0142] As described above with reference to FIG. 3, in the Cs-on-gate type TFT liquid crystal panel, the other end of the storage capacitor 6 is connected to the gate of the immediately preceding scanning line. Therefore, the inventors have found that writing black data to two pixel rows corresponding to adjacent scanning lines at the same time would hinder the writing of the black data. Therefore, in the fourth embodiment, black data, which should be written to two consecutive pixel rows, is written to two pixel rows separated by two lines controlled by the same OE. Even with a Cs on Gate type TFT liquid crystal panel, it is possible to write black simultaneously on two adjacent lines.

In other words, in FIG. 34, in the first state, only the eleventh line and the fourteenth line are selected, and black data is written to the horizontal pixel columns corresponding to those two lines. In the second state, only the first line is selected, and the first image data “1” is written to the horizontal pixel column corresponding to the first line. In the third state, only the second line is selected, and the second image data “2” is output to the horizontal pixel row corresponding to the second line. Is written. In the fourth state, only the thirteenth line and the sixteenth line are selected, and black data is written to two horizontal pixel columns corresponding to those lines. In the fifth state, only the third line is selected, and the third image data “3” is written to the horizontal pixel row corresponding to the third line. In the sixth state, only the fourth line is selected, and image data is written to a horizontal pixel column corresponding to the fourth line. In the seventh state, only the fifteenth line and the eighteenth line are selected, and black data is written to two horizontal pixel columns corresponding to the two lines. In the eighth state, only the fifth line is selected, and the fifth image data “5” is written to the horizontal pixel row corresponding to the fifth line. In the ninth state, only the sixth line is selected, and the sixth image data “6” is written to the horizontal pixel column corresponding to the sixth line.

In the fourth embodiment, while using three output enable signals ({1_}, OE2_0, OE3_0), their control is slightly different from that of the first embodiment. The difference is that only one OE is active in any state, as is clear from the first and ninth states. Further, in the fourth embodiment, the method of inserting the write start pulse is also different from that of the first embodiment. That is, as shown in Fig. 35, this difference is due to the fact that, when two lines are selected at the same time, a pulse of almost 2H / 3 width is not generated, but a pulse with a large length including the two lines between them is generated. By making the panel appear intermittently, it is possible to select every other two lines at the same time. On the other hand, with regard to the black insertion ratio, while writing black simultaneously on two lines separated by two lines in this way, it is possible to realize an arbitrary black insertion ratio every six lines.

Next, FIG. 37 and FIG. 39 show time charts (Nos. 1 to 3) showing the operation of the source driver and the gate driver in the fifth embodiment. The feature of the fifth embodiment is that, compared to the fourth embodiment, the speed of the source clock is increased, thereby shortening the black writing time and, correspondingly, increasing the image writing time. It is. That is, according to the present invention, (M-1) image data and one black data are added to the source driver every period corresponding to (M-1) horizontal scanning periods (H) of the video signal. Output to the vertical signal line, and the output period of the image data and the output period of the black data are the same. There is no need to be. It is also possible to shorten the black data writing period and extend the image writing period by using a clock with a frequency of M / (M-1) times or more. In this example, since twice the source clock is used, the writing time for black is H / 2 and the writing time for images is 3H / 4.

In the above embodiment, instead of sending black data to the source driver, the output to the signal line that resets the shift register in the source driver at once is fixed (for example, black data is not sent to the source driver). ), One (M-1) image data and one (M-1) image data in each period corresponding to (M-1) of the horizontal scanning period (H) of the video signal The output of display data from the source driver to the vertical signal line can be controlled such that the black data is output from the source driver to the vertical signal line.

Next, FIG. 40 and FIG. 42 show time charts (No. 1 to No. 3) showing the output of the source driver and the operation of the gate driver in the sixth embodiment of the present invention. Note that the display panels shown in these figures have three signals (〇E1—O, 〇E2—O, OE3—〇) as output enable signals and a source clock frequency of 3 for convenience of explanation. The vertical scanning period is set to 18 lines, and the 17th line and the 18th line are set to the retrace period. The numbers in the source driver output column shown in the figure indicate the numbers of the scanning lines on which the image data is written.

As is apparent from FIGS. 25 to 27 of the first embodiment described above, in the first embodiment, the black data is the first and second lines, the third and fourth lines, ... and two scanning lines are simultaneously selected and writing is performed, whereas image data is written for each scanning line. Therefore, focusing on two scanning lines (for example, the first line and the second line) on which black is written at the same time, the display time of the image of one scanning line is 2H / 3 longer than the other. Also, in the fourth embodiment, as can be seen from FIGS. 34 to 36, black data is simultaneously written to the first and fourth lines, and the third and sixth lines, and two scanning lines. In contrast, image data is written for each scanning line. Therefore, focusing on two scanning lines (for example, the first line and the fourth line) where black is written simultaneously, the display time of the image of one scanning line is 8HZ3 longer than the other. The difference between these display times depends on the characteristics of the liquid crystal panel, the number of scanning lines and the number of vertical scanning lines that are selected simultaneously when writing black data, and the like. May be recognized. The present embodiment aims to eliminate the difference between these display times. In the sixth embodiment, the black writing method is the same as the fourth embodiment described above, but the image writing method is changed.

Next, a method for writing these images will be described more specifically. In FIG. 40 to FIG. 42, in period A, the write data pulse input to the gate driver and shifted before period A is held in the stage corresponding to the second line. During this period, since only the output enable signal 〇E2_0 is enabled, an image is written to the second line.

[0150] In the period B, the write data held in the stage corresponding to the second line in the period A is shifted by 1 CLK, new write data is input, and the first line and the third line are input. The respective stages are held. During this period, since only the output enable signal 〇E1_0 is enabled, an image is written only to the first line.

[0151] In the period C, the write data is shifted by 1 CLK from the period B, and is held in the stages corresponding to the second line and the fourth line, respectively. Since only the output enable signal 画像 E1-O is enabled, an image is written only on the fourth line.

[0152] In the period D, the write data is shifted by 1 CLK from the period C and held in the stages corresponding to the third and fifth lines, respectively. Since only the output enable signal 画像 E3-O is enabled, an image is written only on the third line.

[0153] In the period E, the write data is shifted by 1 CLK from the period D and held in the stages corresponding to the fourth and sixth lines, respectively. Since only the output enable signal 画像 E3-O is enabled, an image is written only on the sixth line.

[0154] In the period F, the write data is shifted by 1 CLK from the period E, and held in the stages corresponding to the fifth line and the seventh line, respectively. Since only the output enable signal 画像 E2_0 is enabled, an image is written only on the fifth line.

[0155] In the period G, the write data is shifted by 1 CLK from the period F, and held in the shift registers corresponding to the sixth and eighth lines, respectively. As for the output enable signal, since only OE20 is enabled, an image is written only on the eighth line. [0156] Thereafter, the same operation as the above BG is repeated, and the image is written. In addition, the image data is also rearranged in the order of the number in the source driver output column so that the writing order conforms to these. In this case, the amount of data to be held is required to be larger than that in the fourth embodiment, and accordingly, the capacity of the image memory needs to be increased.

[0157] On the other hand, as in the fourth embodiment, two scan lines such as the first line and the fourth line, the third line and the sixth line, the fifth line and the eighth line, etc. Selected and written. Here, paying attention to the first and fourth lines, the image is written for each scanning line such that the first line is selected and written, and then the fourth line is selected and written. On the other hand, in black, two scanning lines are written simultaneously, so that the image display time T2 of the fourth line is 2H longer than the image display time T1 of the first line as shown in FIGS. It is shortened by / 3. Similarly, for the other scanning lines, a time difference of 2HZ3 occurs between two scanning lines selected at the same time. In order to eliminate these time differences, in the next frame, the order of the images input to the source driver and the input timing of the writing pulse are changed, and the writing order of these two scanning lines is changed.

In FIG. 40 to FIG. 42, in period I, the write data that has been input to the gate driver and shifted before period I is held in the stage corresponding to the second line. During this period, only the output enable signal OE2-0 is enabled, so the image is written to the second line.

[0159] In the period J, the write data held in the second line in the period I is shifted by 2 CLK and held in the shift registers corresponding to the fourth line. During this period, since only the output enable signals OE1-0 are enabled, the image is written only on the fourth line.

[0160] In the period K, the write data is shifted by 1 CLK from the period C, and a new start signal is input and held in the stages corresponding to the first line and the fifth line, respectively. Since only the output enable signal {1_} is enabled, the image is written only to the first line.

[0161] As described above, by changing the input timing of the write data, in the previous frame, the fourth line was selected and written after the first line (period B period C) In this frame, the first line is selected and written after the fourth line (period J and period K). Since the writing order of the black data is not changed from the previous frame, as shown in Figure 40-42, the image display time T2 'of the fourth line is 2Η / It gets longer by 3. Similarly, for the other scanning lines, a time difference of 2Η / 3 occurs in the two scanning lines selected at the same time.

According to this method, the image display time (ΤΙ + ΤΙ ′) of the first line and the image display time (T2 + T2 ′) of the fourth line between the frames become equal, and the display time difference between them is canceled. In addition, the difference in display time is similarly canceled for other scanning lines.

As described above, in the sixth embodiment, more memory is required than in the above-described embodiment, but it is possible to eliminate a luminance difference due to a difference in display time due to simultaneous writing of black data. You. In panels with different numbers of output enable signals, the same effect can be obtained by changing the phase of the output enable signal and the input timing of the write pulse, and changing the image writing order every few frames. Can be obtained.

Next, the polarity control of the present invention will be described. As is well known to those skilled in the art, when a DC voltage is continuously applied to the liquid crystal material, the liquid crystal material deteriorates. In order to prevent this deterioration, it is necessary to periodically invert the polarity of the signal voltage applied to the liquid crystal material with respect to the common electrode voltage.

[0165] The inversion operation referred to here is a force performed on adjacent frames, adjacent scanning lines, and adjacent pixels. For a scanning line, the polarity of the signal line is determined by a polarity instruction signal. Therefore, depending on the method of applying the polarity instruction signal, the opposite polarity is not always applied to adjacent scanning lines. For example, as is well known, there is a method of applying the opposite polarity every two scanning lines.

In the present invention, the polarity of black data output from the source driver is inverted each time black data is output. For black, a plurality of scanning lines are simultaneously selected and writing is performed, so that the polarity of the voltage applied to the pixels of the simultaneously selected scanning lines is the same in the signal line direction. The polarity of the image data is such that the polarity indication signal (for the scanning lines that have the same polarity when black is selected at the same time, so that the polarity of each scanning line is the same when writing an image). Enter POL—O). In other words, the number of scanning lines on which the polarity inversion of black is performed is the same as the number of scanning lines on which the polarity of the image is reversed.

Hereinafter, a specific polarity control method according to the present invention will be described with reference to FIGS. 25 to 27 of the first embodiment and FIGS. 34 and 36 of the fourth embodiment. The polarity of the voltage with respect to the common voltage output from each signal line is determined by the polarity indication signal (P〇L_〇) input to the source driver. For example, when the polarity indication signal (P〇L_〇) is “H”, the polarity force of the voltage output from the signal line is ^ positive / negative / positive / negative for each signal line. Sometimes the opposite voltage polarity is negative, positive, negative, positive for each signal line and output. "+" And "one" shown in Fig. 25-Fig. 27 and Fig. 34 and Fig. 36 indicate "H" and "L" of the polarity indication signal (POL_〇) applied to these source drivers, respectively. Shall be represented.

In the first embodiment, as is apparent from FIGS. 25 to 27, black is simultaneously formed for every two scanning lines, such as the first line and the second line, and the third line and the fourth line. Since the data is written, the polarities of the scanning lines written at the same time are the same. Therefore, the polarity indication signal (POL-O) is "10" when writing black on the first and second lines, "one" when writing black on the third and fourth lines, and "1" when writing black on the third and fourth lines. When writing black on the 6th line, set to "+" and invert the polarity every time black data is written. As a result, when writing black data, the polarity is inverted every two scanning lines. In the next frame, the polarity indication signal (POL-〇) is set to "1" when writing black on the first and second lines, and "1" when writing black on the third and fourth lines. When writing black on the 5th and 6th lines, set to "1" and invert the polarity in the adjacent frame.

[0169] The polarity of the image is such that the first line and the second line are set so that the polarity of each scanning line is the same when writing an image to the scanning lines that have the same polarity when black is selected at the same time. Is "10", 3rd and 4th lines are "1", 5th and 6th lines are "+", and the polarity is inverted every two scanning lines. Perform polarity reversal.

In the fourth embodiment, unlike the first embodiment, after black is written on the second line as shown in FIGS. 34 and 36, the first and fourth lines, and the third and sixth lines are written. Black is written simultaneously for every two scanning lines, such as the line, the fifth line, and the eighth line..., And the polarity of these simultaneously written scanning lines is the same. Therefore, the polarity indication signal (P〇LO) is "10" when writing black on the first line, "" when writing black on the first and fourth lines, "+" when writing black on the third and sixth lines, and fifth line When writing black on the 8th line, write "", and invert the polarity every time black data is written. As a result, when writing black data, the polarity is inverted every two scanning lines. However, when the black data is written to the second line, the polarity of the gate driver is inverted after one scanning line because only one scanning line has been input to the gate driver.

[0171] In the next frame, the polarity indication signal (P (L_〇) is set to “1” when writing black on the second line, and when writing black on the first and fourth lines. Set "+", "1" when writing black on the third and sixth lines, and "+" when writing black on the fifth and eighth lines, and invert the polarity in adjacent frames.

[0172] The polarity of the image is set to "10" so that the polarity of each scanning line is the same when writing an image to the scanning lines that have the same polarity when black is selected at the same time. Polarity indication signal (POL-O) such that ", 1st and 4th lines are" ", 3rd and 6th lines are" 10 ", and 5th and 8th lines are" ". Enter As described above, the polarity of black is inverted every two scanning lines, so the polarity of the image is also inverted every two lines (however, the second line is one). Polarity inversion is also performed in the frame.

[0173] Furthermore, when the output enable signal is increased from the fourth embodiment to four lines, black is written to the second line, and then the first line, the third line, the fifth line, and the fourth line Black is written simultaneously for every three scanning lines, such as the sixth and eighth lines, the seventh line, the ninth line, and the eleventh line, and the polarity of these simultaneously written scanning lines is the same. Become. As a result, the polarity of the image is also inverted for each scanning line because the polarity of black data writing is inverted for each scanning line.

In this example, when the polarity of black is “+”, the polarity of the image is also “+” and the polarity of black and the image in the same frame is the same, but the polarity of black is “+”. Sometimes, the polarity of black and the image may be different in the same frame so that the polarity of the image is "1".

As is clear from the above description of the embodiment, according to the present invention, it is possible to achieve a pseudo impulse by applying a black insertion technique while minimizing a decrease in contrast and a deterioration in image quality. Wide range of freedom in setting the black penetration rate, and various device structures Application to a hold-type display panel can be facilitated. The results of experiments conducted by the present inventors show that a 15-inch XGA (1024 X 768) TN liquid crystal module was used to introduce pseudo-impulse by the black insertion technology using the output enable for each gnolap of the present invention. It was confirmed that the blur was significantly improved. It will be easily understood by those skilled in the art that similar effects will be obtained in other liquid crystal modes (IPS, MVA, OCB).

In the video timing control unit 10 shown in FIG. 1, the scaler 11, the timing controller 12, and the black input circuit 13 are configured as separate semiconductor devices. Is merely an example. Another example (part 1) of the video timing control unit 10 is shown in FIG. In this example, the scaler 11 is configured as an independent device, but the black insertion circuit 13 is included in a device configuring the timing controller 12. Another example (part 2) of the video timing control unit 10 is shown in FIG. In this example, the black insertion circuit 13 is configured as an independent device. The power timing controller 12 is built in a device configuring the scaler 11. Another example (part 3) of the video timing control unit 10 is shown in FIG. In this example, the black insertion circuit 13 is included in a device constituting a scaler together with the timing controller 12.

[0177] Various forms of commercial use of the device of the present invention can be adopted. For example, if it is sold as a packaged IC, (1) if only the black insertion circuit 13 is integrated into one chip, (2) if the black insertion circuit 13 and the timing controller 12 are integrated into one chip, In the case where the insertion circuit 13, the timing controller 12, and the scaler 11 are one-chip connected, various product forms such as are considered.

[0178] Furthermore, if a packaged IC is manufactured on the customer side, an IP core (eg, a black lead-in circuit, a timing controller, a scaler, etc.) which is a main part of the present invention is provided to the customer as source code. I do. Here, the source code is a description of those circuits in a hardware description language (VH DL, Verilog, C, etc.). For example, there is a method in which a black insertion circuit and a timing controller are provided to the customer as source code, and the customer independently develops a scaler part and converts it to source code, and drops both into one chip. You can also adopt it can. In this case, the customer performs “logic synthesis” processing on a computer having a compiler function based on the source code of the black insertion circuit and the timing controller and the source code of the scaler section designed by the customer. Then, based on the obtained information (generally called a “net list”), “placement and wiring” processing is performed to produce a target chip. Here, `` logic synthesis '' is to convert the source code described in the hardware description language into a logical expression, logically compress it, and expand it into a group of circuit elements called AND, 〇R, and latch. Specifically, it means compiling those source codes using a library specific to the semiconductor manufacturer. The term “placement and wiring” refers to determining where to place circuit element information obtained by logic synthesis on an actual chip and how to set wiring routes. Industrial applicability

According to the present invention, each time (M−1) pieces of image data are written to (M−1) horizontal pixel rows, the (M−1) pieces of horizontal pixel rows are different from the (M−1) pieces of horizontal pixel rows. Simultaneous writing of black data realizes pseudo-impulse generation of the hold-type display panel, and the black insertion rate can be changed in M (M-1) H units. By applying this technology, it is possible to minimize the contrast and image quality while achieving a pseudo-innoise, and also ensure a wide degree of freedom in setting the black penetration rate, and realize various device structures. It can be easily applied to a display panel having the same.

Brief Description of Drawings

FIG. 1 is a block diagram showing the overall configuration of the device of the present invention.

FIG. 2 is an equivalent circuit diagram of a Cs on Common type liquid crystal display panel.

FIG. 3 is an equivalent circuit diagram of a Cs on gate type liquid crystal display panel.

FIG. 4 is a block diagram showing details of a black insertion circuit.

FIG. 5 is a block diagram showing details of a data generation circuit.

FIG. 6 is a block diagram showing details of a horizontal direction control circuit.

FIG. 7 is a block diagram showing details of a FIF I-WE generation circuit.

FIG. 8 is a block diagram showing details of an STH generation circuit. FIG. 9 is a block diagram showing details of a horizontal counter.

FIG. 10 is a block diagram showing details of an LP-bit generation circuit.

FIG. Ll is a block diagram showing details of a POL-bit generation circuit.

FIG. 12 is a block diagram showing details of a vertical control circuit.

FIG. 13 is a block diagram showing details of an edge detection circuit.

FIG. 14 is a block diagram showing details of a dot counter.

FIG. 15 is a block diagram showing details of a CPV_bit generation circuit.

FIG. 16 is a block diagram showing details of an STV_bit generation circuit.

FIG. 17 is a block diagram showing details of an OE generation circuit.

FIG. 18 is a block diagram (part 1) showing another example of a video ′ timing processing block.

FIG. 19 is a block diagram (part 2) showing another example of a video ′ timing processing block.

FIG. 20 is a block diagram (part 3) showing another example of the video ′ timing processing block.

FIG. 21 is a state transition diagram (first state) showing the operation of the gate driver of the present invention.

FIG. 22 is a state transition diagram (second state) showing the operation of the gate driver of the present invention.

FIG. 23 is a state transition diagram (third state) showing the operation of the gate driver of the present invention.

FIG. 24 is a state transition diagram (fourth state) showing the operation of the gate driver of the present invention.

FIG. 25 is a time chart (part 1) showing the operation of the source driver and the gate driver in the first embodiment.

FIG. 26 is a time chart (part 2) showing the operation of the source driver and the gate driver in the first embodiment.

FIG. 27 is a time chart (part 3) showing the operation of the source driver and the gate driver in the first embodiment.

FIG. 28 is a time chart (part 1) showing the operation of the source driver and the gate driver in the second embodiment.

FIG. 29 is a time chart (No. 2) showing the operation of the source driver and the gate driver in the second embodiment.

FIG. 30 is a time chart (part 3) showing the operation of the source driver and the gate driver in the second embodiment. FIG. 31 is a time chart (part 1) showing the operation of the source driver and the gate driver in the third embodiment.

FIG. 32 is a time chart (part 2) showing the operation of the source driver and the gate driver in the third embodiment.

FIG. 33 is a time chart (part 3) showing the operation of the source driver and the gate driver in the third embodiment.

FIG. 34 is a time chart (part 1) showing the operation of the source driver and the gate driver in the fourth embodiment.

FIG. 35 is a time chart (part 2) showing the operation of the source driver and the gate driver in the fourth embodiment.

FIG. 36 is a time chart (part 3) showing the operation of the source driver and the gate driver in the fourth embodiment.

FIG. 37 is a time chart (1) showing the operation of the source driver and the gate driver in the fifth embodiment.

FIG. 38 is a time chart (part 2) showing the operation of the source driver and the gate driver in the fifth embodiment.

FIG. 39 is a time chart (part 3) showing the operation of the source driver and the gate driver in the fifth embodiment.

FIG. 40 is a chart (part 1) showing the operation of the source driver and the gate driver in the sixth embodiment.

FIG. 41 is a flowchart (part 2) showing the operation of the source driver and the gate driver in the sixth embodiment.

FIG. 42 is a chart (part 3) showing operations of the source driver and the gate driver in the sixth embodiment.

FIG. 43 is a time chart showing the operation of each signal of the STH generation circuit.

FIG. 44 is a state transition diagram (first state) showing the operation of the conventional gate driver.

FIG. 45 is a state transition diagram (second state) showing the operation of the conventional gate driver.

FIG. 46 is a state transition diagram (third state) showing the operation of the conventional gate driver. FIG. 47 is a state transition diagram (fourth state) showing the operation of the conventional gate driver. Explanation of reference numerals

1 LCD panel

2 scan lines

3 Signal line

4 TFT

5 LCD capacity

7 Common electrode

8 Source dry tank

9 Gate driver

10 Image timing control section

11 Scaler

12 Timing controller

13 Black insertion circuit

131 PLL

132 Data generation circuit

133 horizontal control circuit

134 Vertical control circuit

135 Timing adjustment circuit

91 Shift Register Device

92 Shift register noise

93 shift register device

911 shift register element

921 shift register element

931 shift register element

Claims

The scope of the claims

[1] A hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines, A source driver for outputting display data to each vertical signal line of the hold type display panel,

A gate driver for outputting a scan signal to a horizontal scanning line selected from the horizontal scanning lines of the hold type display panel;

Video 'timing control unit,

The gate driver is

A scanning shift register in which scanning line selection data for generating a scanning signal is sequentially shifted in a serial direction on a series of stages;

An output enable gate provided on each of the parallel output lines of the scanning shift register for opening and closing a scanning signal to each horizontal scanning line of the display panel; and

The output enable gates are {kM + 1}, {kM + 2},... {KM + M}, (where k is 0, 1, 2, (Integer, M is an integer of 3 or more.) Can be opened and closed all at once.

The video's timing control unit

(M-1) image data and one black data are output from the source driver to the vertical signal line in each period equivalent to (M-1) of the horizontal scanning period (H) of the video signal Vertical control means for controlling the output of the display data from the source driver to the vertical signal line,

Scan line selection data for writing image data and scanning line selection data for (M-1) lines for writing black data are taken into the first stage of the shift register at predetermined timing, respectively, and the source driver And the shift register is controlled so that the display data is shifted in accordance with the output of the display data to the vertical signal line, and

When the image data is output from the source driver to the vertical signal line, the image data is written. When only the scanning signal generated by the scanning line selection data for the pixel is output to the corresponding horizontal scanning line, and when the source driver outputs the black data to the vertical signal line, (M-1 ) The horizontal direction that controls the opening and closing of the output enable gate in each gnorape unit so that only the scanning signal generated by the scanning line selection data for writing the black data for the line is output simultaneously to the corresponding horizontal scanning line. Control means;

As a result, each time (M_l) pieces of image data are written to (M_l) horizontal pixel rows, the black data is simultaneously written to (M-1) horizontal pixel rows different from the (M_l) pieces of horizontal pixel rows. A hold-type display device that realizes a pseudo-impulse display panel and enables a black penetration ratio to be changed in M (M-1) H units.

[2] The running shift register is formed by connecting a plurality of shift register devices having the same configuration in series, and the output enable control terminal for each group derived from each shift register device is connected to the shift register device. 2. The hold-type display device according to claim 1, wherein the output enable gates are connected to each other so that the continuity of the group order of the output enable gates is maintained at the serial connection points.

[3] Hold-type display panel This is a Cs-on-gate type TFT liquid crystal display panel, and each of the (M-1) horizontal pixel rows to which black data is written is separated by one or more horizontal pixel rows. The hold according to claim 1 or 2, wherein

[4] The hold-type display device according to any one of claims 13 to 13, wherein a writing order of image data to each of the (M-1) horizontal pixel rows is changed for each frame.

[5] Suitable for a hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and pixels with switches arranged corresponding to respective intersections of the vertical signal lines and the horizontal scanning lines. A drive control device,

A source driver for outputting display data to each vertical signal line of the hold type display panel,

Video 'timing control unit, The gate driver is

An output enable gate provided on each of the parallel output lines of the scan shift register, for opening and closing a scan signal to each horizontal scan line of the display panel; and

The output enable gates are {kM + 1} th, {kM + 2} th,... {KM + M} th, where k is an integer of 0, 1, 2, , M is an integer of 3 or more), each of which is divided into M groups, and their output enable gates are grouped in units of groups corresponding to control signals externally given to each group. It is possible to open and close all at once,

The video's timing control unit

The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are fetched into the first stage of the shift register at predetermined timing, respectively, and are read from the source driver. The shift register is controlled so as to be shifted in accordance with the output of the display data to the vertical signal line, and

When image data is output from the source driver to the vertical signal line, only the scanning signal generated by the scanning line selection data for writing image data is output to the corresponding horizontal scanning line. When the black data is output from the pixel to the vertical signal line, only the scan signal generated by the scan line selection data for writing (M-1) lines of black data is output to the corresponding horizontal scan line. Horizontal direction control means for controlling the opening and closing of the output enable gate in units of each gnole so as to be output simultaneously.

As a result, each time (M_l) pieces of image data are written to (M_l) horizontal pixel rows, the black data is simultaneously written to (M-1) horizontal pixel rows different from the (M_l) pieces of horizontal pixel rows. The display panel is made to be a pseudo-impulse, and the black penetration rate is reduced by M (M- 1) A drive control device for a hold-type display panel, which can be changed in H units.

[6] A hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines, A source driver for outputting display data to each vertical signal line of the hold type display panel,

A gate driver for outputting a scan signal to a horizontal scanning line selected from the horizontal scanning lines of the hold type display panel,

The gate driver is

A scan shift register in which scan line selection data for scan signal generation is sequentially shifted in a serial direction on a series of stages;

An output enable gate provided on each of the parallel output lines of the scan shift register, for opening and closing a scanning signal to each horizontal scanning line of the display panel, and

The output enable gates are {kM + 1} -th, {kM + 2} -th,... {KM + M} -th, (where k is an integer of 0, 1, 2 , M is an integer of 3 or more), each of which is divided into M groups, and their output enable gates are grouped in units of groups corresponding to control signals externally given to each group. A display panel with a driver, which can be opened and closed collectively.

[7] A hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and pixels with switches arranged corresponding to respective intersections of the vertical signal lines and the horizontal scanning lines, A source driver for outputting display data to each vertical signal line of the hold type display panel,

The gate driver is

Each of the parallel output lines of the running shift register is provided with An output enable gate that opens and closes a scanning signal to a flat scanning line, and

The output enable gates are {kM + 1} -th, {kM + 2} -th,... {KM + M} -th, (where k is an integer of 0, 1, 2, , M is an integer of 3 or more), each of which is divided into M groups, and their output enable gates are grouped in units of groups corresponding to control signals externally given to each group. An image timing control device that fits a display panel with a driver that can be opened and closed at once.

The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively taken into the first stage of the shift register at predetermined timing, and the source driver And the shift register is controlled so that the display data is shifted in accordance with the output of the display data to the vertical signal line, and

When image data is output from the source driver to the vertical signal line, only the scanning signal generated by the scanning line selection data for writing image data is output to the corresponding horizontal scanning line. When black data is output to the vertical signal line from the scan line, only the scan signal generated by the scan line selection data for writing (M-1) lines of black data is output to the corresponding horizontal scan line at the same time. Horizontal control means for controlling the opening and closing of the output enable gate for each gnorape so as to be output.

As a result, each time (M_l) pieces of image data are written to (M_l) horizontal pixel rows, the black data is simultaneously written to (M-1) horizontal pixel rows different from the (M_l) pieces of horizontal pixel rows. An image timing processing device for a display panel with a driver, wherein the display panel has a pseudo-impulse and the black penetration ratio can be changed in M (M-1) H units.

[8] A hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines, A source driver for outputting display data to each vertical signal line of the hold type display panel,

A gate driver that outputs a scanning signal to a horizontal scanning line selected from among the horizontal scanning lines of the hold-type display panel,

The gate driver is

The output enable gates are {kM + 1}, {kM + 2},... {KM + M}, (where k is 0, 1, 2, (Integer, M is an integer of 3 or more.) Each group is divided into M groups, and their output enable gates are grouped according to the control signal given to each group from outside. To configure a video timing controller that fits the display panel with driver, which can be opened and closed at once.

Scan line selection data for writing image data and scanning line selection data for (M-1) lines for writing black data are fetched into the first stage of the shift register at predetermined timing, respectively, and are also read from the source driver. The shift register is controlled so as to be shifted in accordance with the output of the display data to the vertical signal line, and

When image data is output from a source driver to a vertical signal line, only a scan signal generated by scanning line selection data for writing image data is output to a corresponding horizontal scanning line. When black data is output from the driver to the vertical signal line, only the scan signal generated by the scan line selection data for writing (M-1) lines of black data is output to the corresponding horizontal scan line. So that they are output at the same time. Horizontal control means for opening and closing the enable gate;

FPGA (Field Programmable Gate Array), ASIC (Application Specific IC), or ASSP (Application Specific Standard Products) functioning as

[9] A source code for causing a computer having a compiler function for generating and outputting a netlist necessary for producing the FPGA, ASIC or ASSP according to claim 8 or a source code to be read into the computer A recording medium recorded in a possible format.