JP2005010579A - Method for driving hold type display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for driving a hold type display panel in which "moving picture blurring" of a display panel having hold characteristics can be reduced as far as possible, and an image hold period and a black hold period can properly be set, and which can be manufactured using an existent source driver which is not adaptive to a high-speed clock. <P>SOLUTION: In the driving method of the hold type display panel, one picture is previously divided into a plurality of areas in the vertical direction and the respective divided areas are allocated to a series of image frames in specified order; when the individual image frames are written to the display panel, black data are inserted into only lines included in the divided areas allocated to the image frames and then each time a series of a plurality of image frames corresponding to the number of picture divisions are displayed, black insertion into the whole one picture of the display panel is completed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a drive method for a hold-type display panel suitable for a display panel that performs hold-type light emission, such as a liquid crystal display panel or an organic EL display panel, and more particularly to a hold-type that realizes pseudo impulse by black insertion. The present invention relates to a display panel driving method.
[0002]
[Prior art]
In recent years, various proposals have been made in the field of large-sized liquid crystal display panels suitable for large screen televisions and the like for the purpose of eliminating so-called “moving image blur”. The cause of the “moving image blur” on the LCD panel is that when the viewpoint moves following the target in the video, the hold-type light emission is integrated with the luminance between the frames for the human eye, and the image corresponds to the inter-frame jump distance. It is known that deterioration occurs. Therefore, it is considered that blurring of moving images can be eliminated by correcting the hold type display to a pseudo impulse type display using the black insertion technique.
[0003]
The conventional black insertion techniques are as follows: (1) Black is inserted in units of frames every time the vertical blanking period arrives (first conventional example), (2) The gate driver and source driver are driven with a normal speed clock. However, by providing a black insertion period at the rear of the image hold period (one frame period) of each horizontal line, one frame of black is inserted every two frame times (second conventional example), (3 ) While driving the gate driver and source driver with the clock at twice the speed, one frame of image data is written to the display panel in the first half frame time, and one frame of black data in the second half frame time. Is written on the display panel (third conventional example), etc. (see Non-Patent Document 1, for example).
[0004]
[Non-Patent Document 1]
E-journal separate volume 2003 FPD Technology Encyclopedia Page 131, Fig. 4 (a), (b) and its explanation
[0005]
[Problems to be solved by the invention]
However, in the first conventional example, since black data for one frame must be written to the display panel at a time during the blanking period, it is necessary to develop a source driver that operates with a high-speed clock, which increases costs. There is a problem of being connected.
[0006]
In the second conventional example, since a method of inserting one frame of black data every two frame times is employed, the source driver can be driven by a normal speed clock, but two or more There is a problem that the gate line selection control becomes complicated because the image writing timing and the black writing timing may conflict between the gate lines.
[0007]
In the third conventional example, the use of the double-speed source and gate clocks prevents the image writing timing and the black writing timing from competing between two or more gate lines. If the ratio of the image hold time and the black hold time is made different in accordance with the rise or fall characteristics of the image, it is necessary to use a high-speed clock of the source and gate more than double speed at the time of image writing or black writing. However, it is difficult to cope with existing source drivers, and it is necessary to develop a new source driver corresponding to a high-speed source clock. If the image hold time and the black hold time are not equalized within one frame time, a gradation (darkness unevenness from the upper part to the lower part of the screen) occurs due to the difference between the writing times, and the display quality deteriorates. Therefore, if it is assumed that the use of the existing source driver and the display quality are not sacrificed, it is necessary to use the same speed (double speed) gate clock at the time of image writing and black writing. Regardless of the response speed of the device, the ratio between the image hold period and the black hold period is fixed to ½, and there is a problem in that the degree of freedom in designing the image hold period and the black hold period is lacking.
[0008]
The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to reduce “moving image blur” as much as possible in a display panel having this kind of hold characteristic, An object of the present invention is to provide a method for driving a hold-type display panel, which can appropriately set the hold period and the black hold period and can be manufactured using an existing source driver that cannot support a high-speed clock.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, in the method for driving a hold-type display panel according to the present invention, one screen of the display panel is divided into a plurality of areas in the vertical direction in advance, and each of the divided areas generated by the division is Are assigned to each of a series of image frames in a predetermined order, and when writing each image frame to the display panel, black data is inserted only into the lines included in the assigned area, thereby corresponding to the number of screen divisions. Each time a series of a plurality of image frames are displayed, black insertion for the entire screen of the display panel is completed.
[0010]
Here, the “predetermined order” is, for example, when one screen is divided into four in the vertical direction, and first, second, third, and fourth numbers are assigned to the respective divided regions in order from the top. Each divided area is an image, for example, the first divided area is a first image frame, the second divided area is a second image frame, the third divided area is a third image frame, and the fourth divided area is a fourth image frame. Not only in the case of assigning in order of frame appearance, the first divided area is called the second image frame, the second divided area is called the fourth image frame, the third divided area is called the first image frame, and the fourth divided area is called the third image frame. As described above, this means that the case where the divided areas are assigned in an order other than the order in which the image frames appear is included. Further, if this “predetermined order” is changed at random, the flickering of the screen can be further reduced.
[0011]
According to such a configuration, every time a series of a plurality of image frames corresponding to the number of screen divisions is displayed, black insertion into the entire screen of the display panel is completed, and thus flickering in the human eye is felt. It is only necessary to appropriately set the number of screen divisions within the range where this is not possible.
[0012]
In addition, the operation of writing individual image frames to the display panel is performed while stepping the lines in synchronization with the first gate clock from the top line of the screen to just before the top line of the allocated divided area. A step of writing to the display panel, and writing black data to the display panel while stepping the line in synchronization with the second gate clock from the first line to the last line of the assigned divided area; The process of returning to the top line of the assigned divided area while stepping the line in the reverse direction in synchronization with the clock, and the first gate clock from the start line of the assigned divided area to the end line of the screen If it is realized by the process of writing image data to the display panel while stepping the lines synchronously, a continuous gate line is driven. Because There is maintained, using existing gate driver using the shift register of the bidirectional shift type, it is possible to realize the driving of the display panel. In addition, by making the clock speeds different between the first clock and the second clock, the image data for one screen and the writing of the black data to the assigned divided area can be completed in one frame time. it can. At this time, the black hold period is 1 frame time × (1 / N) when the allocated divided area is 1 / N in one screen, and the remaining {1- (1 / N)} frame time is an image. Hold period.
[0013]
At this time, if the basic dot clock frequency during normal operation of the display panel is CP1 and the number of screen divisions is N, the frequency of the first dot clock is {N / (N-1)} × CP1, If the frequency of the second dot clock is 2 × CP1 (double speed), it is possible to suppress an excessive increase in the source clock speed when writing image data, and to drive the display panel using an existing source driver. It can be certain.
[0014]
In the preferred embodiment, the screen division number N is 3, 4, or 5. That is, if the screen division number N is 3, the frequency of the first dot clock is (3/2) × CP1 = 1.5 times faster, and if N is 5, the frequency of the first dot clock is ( 5/4) × CP1 = 1.25 × speed. If the dot clock speed is the same as the source clock speed, the source clock at the time of writing the image data is only about 1.5 times, so it is possible to drive the display panel using the existing source driver as it is. Become.
[0015]
On the other hand, when writing black data, if the source driver control signal other than the source clock is maintained at double speed and only the source clock is driven at single speed, the existing source driver that cannot support double-speed writing operation is used as it is. can do. At this time, a double-speed gate clock is supplied to the gate driver. The normal clock speed of the gate driver is several tens of KHz, and even if the speed is doubled, it operates without any problem. Thus, black data is written to the display panel via the source driver in at least one horizontal scanning time (2-line gate scanning time) from the start of black data writing. Thereafter, black data is written and updated on the display panel via the source driver every two line gate scanning time. Since black data exists as continuous lines, black data is not missed by the source driver.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
In the following, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
[0017]
FIG. 1 shows a configuration diagram of an entire moving image display system to which the present invention is applied. As shown in the figure, this moving image display system includes a moving image source 1, a controller 2, a liquid crystal display panel 3, a gate driver 4, a source driver 5, a gate power supply 6, a gradation power supply 7, An image memory 8 for holding image data is provided.
[0018]
Image data (Data) sent from a moving image source 1 such as a computer, a DVD player, or a TV is once input to the controller 2 and then transferred to the source driver 5.
[0019]
The controller 2 also performs various control signals based on the vertical synchronization signal (Vsyn), horizontal synchronization signal (Hsyn), basic dot clock (CP1), and data enable signal (DENB) sent from the moving image source 1. (DSP, DCK, OP, GSP, GCK) are generated. Here, DSP is a data start pulse, GSP is a gate start pulse, DCK is a source clock, GCK is a gate clock, OP is a data output latch pulse, and their roles will be described later as necessary. As shown in FIG. 3, the signal generation circuit 27 generates a black period instruction signal (inverted black) and a black period latter half instruction signal (inverted black second half) based on these signals (CP1, Hsyn, Vsyn, DENB). Generate.
[0020]
In addition, the gradation power supply 7 generates a reference voltage (gradation voltage: Vn) when D / A converting digital data into a corresponding voltage. The gate power supply 6 generates output voltages (VGH) and (VGL) of the gate driver 4.
[0021]
In this example, a liquid crystal display panel 3 having a resolution of W-XGA (1280 × RGB × 768) is used. Further, the frame frequency is 60 Hz (non-interlace) and the basic dot clock speed given to the controller 2 is 42.5 MHz when the liquid crystal display panel 3 is operated. The description will be made assuming that the screen division number N is four.
[0022]
In this example, the gate driver 4 includes three shift registers 41, 42, and 43 connected in series with each other, as shown in FIG. Each of these shift registers 41, 42, 43 has 256 stages each having a 1-bit configuration. The 1-bit data stored in each stage can be shifted in either the left direction (L) or the right direction (R). A gate clock pulse for shift driving is supplied to a terminal (CPV), and a logic signal for designating a shift direction is supplied to a terminal (L / R). The gate start pulse (GSP) to be shifted is input to the terminal (STV1) of the shift register 41, and the output terminal (STV2) is cascaded to STV1 of the shift register 42 in the next stage. Similarly, the STV2 output of shift register 42 is cascaded to 43 STV1 inputs. The resistor R1 connected to the STV1 terminal of the shift register 41 and the resistor R2 connected to the STV2 terminal of the shift register 43 are provided to prevent malfunction when the shift direction is reversed.
[0023]
A gate start pulse GSP is supplied to a terminal (STV1) of the shift register 41 located at the head of the three shift registers 41, 42, and 43 connected in series. When the gate start pulse GSP is taken into the shift register 41, 1-bit data constituting the line selection signal is generated in the first stage of the shift register 41. Thereafter, the 1-bit data is synchronized with a gate shift clock supplied to a terminal (CPV), the first stage to the 256th stage of the shift register 41, the first stage to the 256th stage of the shift register 42, and the shift register. 43 are sequentially shifted sequentially from the first stage to the 256th stage.
[0024]
Each of the three shift registers 41, 42, 43 connected in series has 256 gate outputs. As is well known to those skilled in the art, each of these gate outputs corresponds to a horizontal scan line of the display panel. These 256 gate outputs correspond to the first stage to the 256th stage of each shift register 41, 42, 43. Therefore, when 1-bit data is sequentially shifted in each shift register 41, 42, 43, only the gate output corresponding to the stage where the 1-bit data exists is activated, and the corresponding horizontal scanning line is selected. Is done.
[0025]
In the example of FIG. 2, a gate clock (GCK) including one of two systems of gate clocks having different frequencies is supplied to the terminals (CPV) of the shift registers 41, 42, and 43 in a time division manner. One of the two gate clock pulses is referred to as a first gate clock, and the other as a second gate clock. Assuming that GCP is a gate clock (hereinafter referred to as a basic gate clock) that is normally used when operating at a specified frame frequency (60 Hz in this example) of the display panel, the first gate clock (4/3 × GCP) Is a clock having a frequency (4/3 times) of the basic gate clock GCP (4/3 times speed), and the second gate clock (2 × GCP) is twice the frequency (2 times speed) of the basic gate clock GCP. A clock having
[0026]
Referring to FIG. 3, the dot clock (DCP) input to timing controller 23 has different clock speeds during the black data writing period and the image data writing period to the liquid crystal display panel. The dot clock speed is switched by the selector 25. During black writing, the double-speed dot clock CP3 (= 2 × CP1) is used, and during image writing, the high-speed dot clock CP2 (4 / 3CP1) is used. The 4/3 speed dot clock CP2 and the double speed dot clock CP3 are generated by the PLL circuit 26 based on the basic dot clock CP1. The timing controller 23 sends data, control signals, and shift clocks to the source driver and gate driver corresponding to the speed of the dot clock (DCP).
[0027]
The shift direction of each of the shift registers 41, 42, 43 is controlled by a black period second half instruction signal (Black second half) drawn as an “L” active pulse waveform in the second half of the black period display signal (Black) in the figure. Each shift register 41, 42, 43 is shifted in the backward direction (L direction) only in the second half of the black period, and is shifted in the forward direction (R direction) in other periods. In addition, the shift speed of each of the shift registers 41, 42, 43 is doubled in synchronization with the second gate clock (2 × GCP) during the black period. Similarly to the gate signal, corresponding to the dot clock (DCP) of the timing controller 23, the source driver data, control signals (DSP, OP), and source clock (DCK) are also twice the normal speed during black writing. At the time of writing, the speed is 4/3 times the normal speed, and black data and image data are written to the liquid crystal display panel in synchronization with the gate signal.
[0028]
Note that the first gate clock (4/3 × GCP), the second gate clock (2 × GCP), and the black period latter half instruction signal (Black latter half) are supplied from the controller 2 depicted in FIG. .
[0029]
Returning to FIG. 1, the source driver 5 displays based on the gradation voltage (Vn) given from the gradation power supply 7, the control signals (DSP, DCK, OP) and source data (Data) given from the controller 2. Control for writing source data to the horizontal scanning line selected by the gate driver 4 of the panel 3 is realized. This source data write control is performed using a data start pulse (DSP), a source clock (DCK), and a data output latch pulse (OP) included in a control signal supplied from the controller 2.
[0030]
Although the internal circuit configuration of the source driver 5 is well-known to those skilled in the art, it is not shown in the figure. However, in general, a data start pulse (DSP) is captured in synchronization with the source clock (DCK), and this is taken into A shift register that shifts in synchronization with (DCK), a number of latch circuits that sequentially capture image data in synchronization with each of the parallel outputs of the shift register, and each output data of these latch circuits is output latch pulse (OP ) And a data output circuit that converts the output data of the holding memory into a corresponding analog voltage and writes it to the display panel.
[0031]
Theoretically, if the speed of the source clock (DCK) is increased, the data writing speed can be increased arbitrarily. However, in reality, the source clock (DCK) is limited due to restrictions on data setup and hold time. There is an upper limit on speed for each product.
[0032]
In standard use, the frequency of the data start pulse (DSP) and the frequency of the gate clock (GCK) are the same. That is, new data is written to each horizontal scanning line by switching the horizontal scanning line every time data for one horizontal scanning line is transferred to the source driver 5. However, the data transfer rate to the source driver 5 and the gate clock frequency of the gate driver 4 can be set to be independent while maintaining a synchronous relationship. As will be described later, in this embodiment, while the gate driver 4 is driven at double speed, the data transfer to the source driver 5 is maintained at the single speed at the source clock (DCK), thereby writing black data. The operating speed of the source driver 5 in FIG. In this case, the same black data is written in two horizontal scanning lines that are continuous in one horizontal period, but the black data is not missed by the source driver.
[0033]
Next, a block diagram showing a circuit configuration for generating black insertion image data is shown in FIG. This circuit configuration is included in the controller 2 depicted in FIG. However, the dual port memory 21 of FIG. 3 is connected to the outside of the controller because of the storage capacity. The image memory 8 in FIG. 1 corresponds to the dual port memory 21.
[0034]
As shown in the figure, this circuit is composed mainly of a dual port memory 21, a selector 22, a timing controller 23, a NAND gate 24, and a selector 25.
[0035]
The dual port memory 21 has a storage capacity necessary for returning to the first pixel for black writing after at least black writing, and image data is stored in each address of the storage area. The dual port memory 21 includes a write address pointer P (W) and a read address pointer P (R). The write address pointer P (W) is incremented in synchronization with the clock supplied to the terminal (W). The read address pointer P (R) is incremented in synchronization with the clock supplied to the terminal (R). The 48-bit data that is the input data Din1 from the image source 1 is stored at the address specified by the write address pointer P (W). The 48-bit data stored at the address specified by the read address pointer P (R) is output as output data Dout1.
[0036]
The reference dot clock CP1 is supplied to the terminal (W) of the dual port memory 21 of FIG. Here, the frequency of the reference dot clock CP1 is 42.5 (= 85/2) MHz. Therefore, the write address pointer P (W) in the dual port memory 21 is stepped in synchronization with the reference dot clock CP1 having 42.5 MHz. Therefore, the input data Din1 which is each pixel data (8 bits × RGB × 2 ports = 48 bits) constituting the image data (Data) sent from the image source 1 is synchronized with the reference dot clock CP1 of 42.5 MHz. Then, data is sequentially written to each address in the dual port memory 21 designated by the write address pointer P (W).
[0037]
The high-speed dot clock CP <b> 2 is supplied to the terminal (R) of the dual port memory 21 through the NAND gate 24. Here, the NAND gate 24 is controlled to be opened and closed by a black period instruction signal (inverted black) drawn as an “L” active pulse waveform in the drawing. The frequency of the high-speed dot clock CP2 is 56.66 (= 4/3 × CP1) MHz. Therefore, the read address pointer P (R) in the dual port memory 21 is advanced only in the period excluding the black period in synchronization with the high speed dot clock CP2 having 56.66 MHz. Therefore, from the dual port memory 21, pixel data (8 bits × RGB × 2 ports = 48 bits) stored at the address specified by the read address pointer P (R) is output data Dout1 only during the period excluding the black period. Output sequentially.
[0038]
Either the output data Dout1 of the dual port memory 21 or the separately prepared black data Db is alternatively supplied to the data input terminal of the timing controller 23 via the selector 22. The dot clock input terminal of the timing controller 23 is connected to a high-speed dot clock CP2 (= 4/3 × CP1 = 56.66 MHz) and a double-speed dot clock CP3 (= 2 × CP1 = 85 MHz) via a selector 25. One of these is alternatively supplied. Here, the output of the selector 25 including the high-speed dot clock CP2 and the double-speed dot clock CP3 in a time division manner is referred to as a dot clock DCP.
[0039]
Here, switching of the selector 22 and the selector 25 is controlled by an “L” active black period instruction signal (inverted black). Therefore, during an image data writing period, which will be described later, the output data Dout1 is supplied to the data input terminal of the timing controller 23, and the high-speed dot clock CP2 is supplied to the dot clock input terminal. On the other hand, in the black data writing period, the black data Db is supplied to the data input terminal of the timing controller 23, and the double speed dot clock CP3 is supplied to the dot clock input terminal. The timing controller 23 sends a signal group toward the source driver 5 and a signal group toward the gate driver 4 corresponding to the speed of the dot clock DCP.
[0040]
The signal group toward the gate driver 4 includes a gate start pulse (GSP), a gate clock (GCK), a black second half instruction signal (Black second half), and the like. The frequency of the gate clock (GCK) sent to the gate driver 4 is different between the black insertion period and the image data writing period, as will be described later. Specifically, the frequency of the gate clock (GCK) sent to the gate driver 4 is set to double speed (2 × GCP) in the black insertion period, whereas it is 4/3 speed in the image writing period. (4/3 × GCP). GCP is set to a gate clock speed during normal operation, that is, when the basic dot clock CP1 is 42.5 MHz.
[0041]
The signal group toward the source driver 5 includes control signals such as the data start pulse (DSP) and the output latch pulse (OP) described above in addition to the image data (Data) and the source clock (DCK). It is. As will be described later, the image data sent to the source driver 5, the transmission speed of the control signal, and the frequency of the source clock (DCK) are different between the black period and the image data writing period.
[0042]
A normal source clock used for writing new data for each horizontal scanning line is defined as a basic source clock (DCK1). In this embodiment, the basic source clock DCK1 has the same frequency as the basic dot clock CP1. Then, the frequency of the source clock DCK output from the timing controller 23 is set to double speed (2 × DCK1) in the black data writing period, whereas it is 4/3 times speed (4 / 3 × DCK1). Of course, in accordance with the source clock speed, the transmission speed of the source data is also set to double speed and 4/3 speed. As a result of experience, in recent liquid crystal display panel products, if the source clock speed is about twice the recommended basic source clock (DCK1), black data can be obtained if a high-speed source driver is used. There will be no hindrance to writing.
[0043]
However, depending on the liquid crystal display panel product, a source driver that cannot withstand even the black data writing drive at the double speed is assumed. For such products, the frequency of the source clock DCK output from the timing controller 23 is set to 1 × speed while maintaining the basic source clock (DCK1) during the black period, and the gate driver is driven at 2 × speed. In the image writing period, the speed is 4/3 times (4/3 × DCK1). In accordance with the source clock speed, the transmission speed of data sent from the timing controller 23 to the source driver 5 is also set to 1 × speed and 4/3 speed. Then, in the display panel, one data is written for every two continuous horizontal scanning lines, but since the data written at the time of black insertion is continuous black, the black data is supplied to the source driver. There is no loss of uptake. In most liquid crystal display panels, even if the speed of the source clock DCK is increased to about 4/3 times, there is no problem in writing data to the source driver. Therefore, writing of image data at 4/3 times speed is performed without any problem.
[0044]
Next, the operation of the moving image display system of the present invention will be described in detail mainly with reference to FIGS.
[0045]
In this example, as shown in FIG. 4E, one screen of the display panel is divided in advance into four areas in the vertical direction. The term “division” as used herein is an ideal meaning and is not physically divided. Now, suppose that each divided region is named first divided region, second divided region, third divided region, and fourth divided region in order from top to bottom. Further, “division” is realized by storing the head line addresses (L1, L193, L385, L577) of these four division areas in a predetermined memory as shown in FIG. 4D. can do. As shown in FIG. 4E, these four divided areas are assigned in a predetermined order to four image frames that arrive in succession. In this example, the first divided area is the first frame, the second divided area is the second frame, the third divided area is the third frame, the fourth divided area is the fourth frame, and so on. The division order of each divided region is assigned so as to correspond to the appearance order of each image frame.
[0046]
It should be noted that the graph of FIG. 4E is somewhat misunderstood, so an annotation is added. The horizontal axis of this graph is the time axis, and the vertical axis is the number of horizontal scanning lines. Accordingly, in the horizontally long rectangular figure drawn on the graph, the vertical direction corresponds to the screen length, but the horizontal direction does not correspond to the screen length. At first glance, it is apt to be misunderstood that not only the vertical direction of the screen but also the horizontal direction is divided into four parts, and black is written in one of the regions divided into four parts vertically and horizontally. It should be noted that in the upper part, the entire width in the left-right direction is divided into four parts in the vertical direction, and black is written in one of the divided areas thus obtained.
[State before display operation starts]
[0047]
The image data (input data Din1) of each frame coming from the image source 1 is repeatedly overwritten on a series of addresses in the dual port memory 21 in synchronization with the reference dot clock (CP1). At this time, the value of the read address pointer P (R) in the dual port memory 21 is held at a value corresponding to immediately before the top line of the screen.
[Status after display operation starts]
(1) Image data writing period control operation (front side)
[0048]
When the display operation on the liquid crystal display panel 3 is started, the head line address of the divided area where black is to be written in the first image frame (first frame) is read from the memory and set as the target address.
[0049]
At this time, the black period instruction signal (inverted black) is maintained at “H” and the black second half instruction signal (inverted black second half) is also maintained at “H”, and the NAND gate 24 is set to “open”. The read address pointer P (R) is incremented in synchronization with a high-speed dot clock (CP2 = 4/3 × CP1) having a frequency of 56.66 MHz. At the same time, collation between the memory address corresponding to the first line of the black writing scheduled area and the value of the read address pointer P (R) is started.
[0050]
The selector 22 is set on the output data Dout1 side, and the selector 25 is set on the high-speed clock (CP2 = 4/3 × CP1) side. Therefore, in this state, the storage contents of the addresses sequentially specified by the read address pointer P (R) are sequentially output from the dual port memory 21 as output data Dout1 from the dual port memory 21, and the selector 22 and the timing After passing through the controller 23 in order, it is sent to the source driver 5 together with a data start pulse (DSP) and a source clock (DCK = 4/3 × DCK1).
[0051]
At this time, since the black period latter half instruction signal (inverted black second half) is “H”, as shown in FIG. 2, the shift direction of each shift register 41, 42, 43 is set to the right direction (R), and the shift is performed. The gate start pulse (GSP) taken into the register 41 is shifted in the forward direction. A gate start pulse (GSP) and a gate clock (GCK) are sent from the timing controller 23 to the gate driver 4. The frequency of GSP and GCK is 4/3 times that in normal operation.
[0052]
Thereby, each horizontal scanning line of the liquid crystal display panel 3 is successively moved at (4/3) times speed until the value of the read address pointer P (R) reaches immediately before the head line address of the target black writing area. While switching, a process of writing image data to the corresponding horizontal scanning line is executed.
(2) Control operation in the first half of the black data writing period
[0053]
When the content of the read address pointer P (R) coincides with the address immediately before the start address of the target black writing area, the content of the black period instruction signal (inverted black) is changed from “H” to “L”. Then, the advance of the read address pointer P (R) in the dual port memory 21 is stopped, the output data Dout1 in the selector 22 is switched to the black data Db, and the high-speed dot clock (CP2 = 4/3 × CP1) in the selector 25. Switching to the double speed dot clock (CP3 = 2 × CP1) is performed. At this time, since the black period latter half instruction signal (inverted Black second half) is still maintained at “H”, the shift direction of each shift register 41, 42, 43 is set to the right direction (R) or the forward direction.
[0054]
In this state, the reading of the output data Dout1 from the dual port memory 21 is stopped. Instead, after the black data Db sequentially passes through the selector 22 and the timing controller 23, the data start pulse (DSP) or 1 × speed It is sent to the source driver 5 together with the data clock (DCK = 1 × DCK1). At this time, if there is a margin in the writing speed of the source driver 5, a double speed data clock (DCK = 2 × DCK1) may be used.
[0055]
A gate start pulse (GSP), a double speed gate clock (GCK = 2 × GCP), and a Black second half signal are sent from the controller 2 to the gate driver 4.
[0056]
As a result, while the horizontal scanning lines of the liquid crystal display panel 3 are sequentially switched from top to bottom at double speed until the final line address of the black writing area is reached, two lines of black data are output for the corresponding lines. Is written once (when using a 1 × speed source clock) or once per line (when using a 2 × speed source clock).
(3) Control operation in the second half of the black data writing period
[0057]
When the writing of black data is completed up to the final line address of the black writing area, the content of the black period instruction signal (inverted black) remains “L” and only the black period latter half instruction signal (inverted black second half) is “H”. In response to this, the shift direction of each shift register 41, 42, 43 is switched from the right direction (R) to the forward direction to the left direction (L) to the reverse direction.
[0058]
Even in this state, the reading of the output data Dout1 from the dual port memory 21 is stopped. Instead, the black data Db passes through the selector 22 and the timing controller 23 in order, and then the 1 × or 2 × speed source clock. (DCK = 1 × DCK1, or 2 × DCK1) is sent to the source driver 5. Further, a double-speed gate clock (GCK = 2 × GCP) is sent from the timing controller 23 to the gate driver 4.
[0059]
As a result, while the horizontal scanning lines of the liquid crystal display panel 3 are sequentially switched from the bottom to the top at the double speed until the head line address of the black writing area is reached, two lines of black data are output for the corresponding lines. Is written once (when using a 1 × speed data clock) or once per line (when using a 2 × speed data clock).
[0060]
In this way, when returning from the last line address to the first line address, black data may not be written but only address stepping may be performed.
(4) Image data writing period control operation (rear side)
[0061]
If the line address is returned to the head line address of the black writing area, the black period instruction signal (inverted black) is changed from “L” to “H”, and at the same time, the black second half instruction signal (inverted black second half) is also changed. “L” is changed to “H”. Then, the NAND gate 24 is opened, and the read address pointer P (R) in the dual port memory 21 is synchronized with a high-speed dot clock (CP2 = 4/3 × CP1) having a frequency of 56.66 MHz. Stepped on. At the same time, the comparison between the memory address corresponding to the last line of the screen and the value of the read address pointer P (R) is started.
[0062]
The selector 22 is set on the output data Dout1 side, and the selector 25 is set on the high-speed dot clock (CP2 = 4/3 × CP1) side. Therefore, in this state, the storage contents of the addresses sequentially specified by the read address pointer P (R) are sequentially output from the dual port memory 21 as output data Dout1 from the dual port memory 21, and the selector 22 and the timing After passing through the controller 23 in order, it is sent to the source driver 5 together with a data start pulse (DSP) and a source clock (DCK = 4/3 × DCK1).
[0063]
At this time, since the black period latter half instruction signal (inverted Black second half) is “H”, the shift direction of each shift register 41, 42, 43 is set to the right (R) as shown in FIG. The gate pulse (1-bit data) that has been shifted backward in the gate driver is shifted in the forward direction. A gate clock (GCK = 4/3 × GCP) is sent from the timing controller 23 to the gate driver 4.
[0064]
Thus, the horizontal scanning lines of the liquid crystal display panel 3 are switched one after another at (4/3) times speed until the value of the read address pointer P (R) reaches the target screen final line address. The process of writing image data to the horizontal scanning line is continued until a match between the memory address corresponding to the last line of the screen and the value of the read address pointer P (R) is confirmed.
[0065]
Thereafter, as a result of repeating the control operations (2) to (4), as shown in FIG. 4 and FIG. 5, it is included in the divided areas assigned to the respective image frames (1 to 4 frames). By inserting black only in the horizontal scanning line, every time a series of a plurality of image frames (1 to 4 frames) corresponding to the number of screen divisions is displayed, the black insertion for the entire screen of the display panel is completed. It will be.
[0066]
In the example shown in FIGS. 4 and 5, one screen of the display panel is divided into four areas in the vertical direction in advance, and each of the areas generated by the division is a series of image frames (1 to 4 frames). Frames) are assigned in a predetermined order. The operation of writing individual image frames (1 to 4 frames) to each horizontal scanning line of the display panel includes a first process to a third process.
[0067]
In the first step, the first gate clock (4/3 × GCP) is reached from just before the top line (L1) of the screen (L0) to just before the top line (L1, L193, L385, L577) of the allocated area. ) (Steps 0 to P1, P5 to P6, P10 to P11, and P15 to P16 in FIG. 5) are executed while stepping the line in synchronization with the line.
[0068]
In the second step, the second gate clock (2 × GCP) is synchronized from the first line (L1, L193, L385, L577) to the last line (L192, L384, L576, L768) of the allocated divided area. The process of writing black data to the display panel while stepping the line (corresponding to P1 to P2, P6 to P7, P11 to P12, P16 to P17 in FIG. 5), and the second gate clock (2 × GCP) A process (P2, P3, P7 to P8, P12 to P13 in FIG. 5) of returning to the first line (L1, L193, L385, L577) of the allocated area while stepping the line in the reverse direction synchronously Corresponding to P17 to P18).
[0069]
In the third step, the line is walked in synchronization with the first gate clock (4/3 × GCP) from the first line (L1, L193, L385, L577) of the allocated divided area to the last line (L768) of the screen. The process of writing image data on the display panel while proceeding (corresponding to P3 to P4, P8 to P9, P13 to P14, and P18 to P19 in FIG. 5) is performed.
[0070]
According to this embodiment, since the continuity of the selected lines is maintained, the display panel can be driven using the existing gate driver using the bidirectional shift type shift register, Moreover, the image hold period and the black hold period can be set appropriately depending on the number of screen divisions.
[0071]
At this time, when the gate clock frequency for horizontal scanning line stepping during normal operation of the display panel is GCP and the number of screen divisions is N, the frequency of the first gate clock is {N / (N-1)}. If it is set to × GCP and the frequency of the second gate clock is 2 × GCP (double speed), an excessive increase in the gate and source clock speed at the time of writing source data is suppressed, especially at the time of writing black data. When a 1 × speed source clock (DCK1) is used, the display panel can be driven more reliably using an existing source driver.
[0072]
In the preferred embodiment, the screen division number N is 3, 4, or 5. That is, if the screen division number N is 3, the frequency of the first dot clock is (3/2) × CP1 = 1.5 times faster, and if N is 5, the frequency of the first dot clock is ( 5/4) × CP1 = 1.25 times speed, and the source clock for writing image data is only about 1.5 times, so that the display panel can be driven using the existing source driver as it is. Become.
[0073]
【The invention's effect】
As is apparent from the above description, according to the method of the present invention, “moving image blur” can be reduced as much as possible in a display panel having this kind of hold characteristic, and the image hold period and the black hold period are appropriately set. It can also be set using an existing source driver that does not support high-speed clocks.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an entire moving image display system.
FIG. 2 is an explanatory diagram of a circuit configuration for realizing gate line selection control according to the present invention.
FIG. 3 is a block diagram showing a circuit configuration for generating black insertion image data.
4 is an operation explanatory diagram of the circuit of FIG. 2. FIG.
FIG. 5 is an explanatory diagram illustrating a relationship between black insertion of a screen and drive timing of a gate driver.
[Explanation of symbols]
1 Video source
2 Controller (ASIC)
3 LCD panel
4 Gate driver
5 Source driver
6 Gate power supply
7 gradation power supply
8 Image memory
21 Dual port memory
22 Selector
23 Timing controller
24 NAND gate
25 Selector
26 PLL circuit
27 Signal generation circuit
41-43 shift register

Claims (4)

One screen of the display panel is divided into a plurality of areas in the vertical direction in advance, each of the divided areas generated by the division is assigned to each of a series of image frames in a predetermined order, and each image frame is displayed on the display panel. Each time a series of a plurality of image frames corresponding to the number of screen divisions is displayed, black data is inserted only into the lines included in the divided area assigned to the image frame. A method for driving a hold-type display panel, characterized in that black insertion for one entire screen is completed. The operation of writing individual image frames to the display panel
Writing image data to the display panel while advancing the line in synchronization with the first gate clock from just before the top line of the screen to just before the top line of the allocated divided area;
Write black data to the display panel while stepping the line in synchronization with the second gate clock from the first line to the end line of the assigned divided area, and then the line is synchronized with the second gate clock. Returning to the top line of the assigned divided area while stepping in the opposite direction;
Writing image data to the display panel while advancing the line in synchronization with the first gate clock from the first line of the allocated divided area to the last line of the screen, and the first gate clock 2. The method of driving a hold type display panel according to claim 1, wherein the frequency is different from that of the second gate clock. When the basic gate clock during normal operation of the display panel is GCP and the number of screen divisions is N, the frequency of the first gate clock is {N / (N−1)} × GCP, and the second gate clock 3. The method for driving a hold type display panel according to claim 2, wherein the frequency of the hold type display panel is 2 * GCP. 4. The method of driving a hold type display panel according to claim 3, wherein the division number N of the screen is 3, 4, or 5.

Images