JPH0854601A - Active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device capable of displaying even video signals mutually different in the number of pixels. CONSTITUTION:In the active matrix type liquid crystal display device provided with an active matrix liquid crystal display panel 1, a data driver 2 driving the data lines of the liquid crystal display panel 1 and a gate driver 3 driving the scan lines of the liquid crystal display panel 1, when the video signal of the number of pixels different from the number of pixels of the liquid crystal display panel 1 in the horizontal or vertical direction is inputted, and a part where no video is displayed occurs on the display surface of the liquid crystal display panel 1, a prescribed voltage is supplied to the pixel in the part where no video of the liquid crystal display panel 1 is displayed in the non-video signal period of the video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal, and particularly when displaying display data smaller than the screen of a liquid crystal panel that can be displayed, one data of a video signal is displayed for one pixel of the liquid crystal panel. The present invention also relates to a liquid crystal display device that drives all liquid crystal pixels.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing a basic configuration of an active matrix type liquid crystal display device, and FIG. 12 is a diagram showing a configuration example of an active matrix type liquid crystal panel.
3 is a block diagram showing the configuration of the data driver, and FIG. 14 is a block diagram showing the configuration of the gate driver.

The active matrix type liquid crystal display device is
It has an active matrix type liquid crystal panel 1, a data driver 2, and a gate driver 3. As shown in FIG. 12, the active matrix type liquid crystal panel 1 includes liquid crystal cells C11, ..., Cxy arranged in a matrix, data lines extending from the data driver 2, scan lines extending from the gate driver 3, and each liquid crystal. A thin film transistor T arranged to connect a cell and a corresponding data line and having a corresponding gate connected to a scan line
FT11, ..., TFTxy. Scan pulses are sequentially applied to the scan lines, and the thin film transistors in each row are sequentially turned on in response to the scan pulses. The data driver 2 outputs a voltage corresponding to display data to the data line in response to the thin film transistor in each row being turned on. Therefore, the voltage corresponding to the display data is applied to the liquid crystal cell in that row according to the scan pulse. When a scan pulse is applied to the next row, the thin film transistors in that row are turned off, and the thin film transistors in that row remain off until the scan pulse is applied to all rows and the scan pulse is applied again. Therefore, the voltage applied to the liquid crystal is maintained until that time. In this way, when the voltage corresponding to the display data is applied to the liquid crystals of all the rows, the display of one screen is completed. This one-screen display cycle is called a normal frame. Further, it may be referred to as one vertical display period in the sense that all the rows in the vertical direction are displayed.

A video signal similar to that supplied to a CRT (Cathode Ray Tube) is supplied to the active matrix type liquid crystal display device. In order to enable the above display when such a video signal is supplied, the data driver 2 has the shift register 2 as shown in FIG.
1, a level shifter 22, a sample and hold circuit 23, and an output buffer 24. A clock signal GCLK corresponding to one display dot is input to the shift register 21, and a horizontal synchronizing signal HSY is input.
NC is input and horizontal pulses generated corresponding to the horizontal synchronizing signal are sequentially shifted according to the clock signal GCLK. A video signal is supplied to the data driver 2 and is latched in the sample-and-hold circuit 23 by a horizontal pulse that is sequentially shifted. In this way the sample
The AND / hold circuit 23 holds data for one horizontal line. The data for one horizontal line is taken into the output buffer 24, and the corresponding voltage is simultaneously output to the data line for one horizontal display pixel number.

As shown in FIG. 14, the gate driver 3 has a shift register 31, a level shifter 32, and an output buffer 33. The vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC are input to the shift register 31, and the scanning pulse generated according to the vertical synchronizing signal is sequentially shifted according to the horizontal synchronizing signal. The sequentially shifted scanning pulse output from the shift register 31 is the level shifter 32.
Is input to the output buffer 33 via. The output buffer 33 outputs a scan pulse that is sequentially shifted to a scan line according to the output enable signal OE.

At present, CRTs are widely used as display devices for computers and the like, but the use of active matrix type liquid crystal display devices is increasing as compact and low power consumption display devices. Current standard video signal 640x4
Although 00 dots are displayed, higher definition display is desired, and CRTs and active matrix type liquid crystal display devices capable of high definition display have been developed. At present, a standard number of display pixels has not been determined as a display device for high definition, and a plurality of types of display devices having different display pixels have been developed. Normally, since the display device is selected corresponding to the computer, the number of pixels of the video signal output from the computer and the number of pixels of the display device have a one-to-one correspondence. However, even if the computer is changed, it is desired that the display device can be used commonly and universally, and it is desirable that the display device can display all modes of the video signal.

When the ratio of the number of display pixels in the vertical and horizontal directions is an integral multiple, the video signal is thinned out when the number of pixels of the video signal is large, or the same data is applied to a plurality of pixels when the number of display pixels is large. This can be easily handled by displaying or displaying the average value of a plurality of pixels. However, when the ratio of the number of display pixels in the vertical and horizontal directions is not an integral multiple, display cannot be performed by such a method.

Therefore, for example, when the number of pixels of the video signal is large, only some pixels of the video signal are displayed. In this case, the same applies to the CRT and the liquid crystal display device. Therefore,
In this case, part of the image will not be displayed,
Can be displayed. On the other hand, when the number of pixels of the video signal is smaller than the number of pixels of the display device, the display can be performed by supplying the video signal as it is in the case of a CRT. In the CRT, the portion to which the video signal is not supplied is displayed in black, so the portion other than the display of the video signal is black. As described above, it is desirable that the portion of the screen on which the image is not displayed is displayed in black from the viewpoint of easy viewing. However, white may be displayed instead of black, especially in the case of a display mode in which black and white are reversed.
White display is preferable. Alternatively, an intermediate gray level may be displayed.

[0009]

However, it is difficult to display black or white portions of the screen where the image is not displayed on the liquid crystal display device, and some means is required. In order to avoid deterioration due to image sticking on the liquid crystal panel, 1
It is necessary to alternately apply positive / negative and reverse polarity voltages for each display cycle (frame cycle) of the screen. Even when black display or white display is performed, the voltage of positive / negative reverse polarity at a level corresponding to black display or white display. Must be applied alternately. Hereinafter, in order to facilitate the description, black display will be described as an example, but the same applies to the case of displaying white display or gray level. Due to the structure of the liquid crystal display device, the numbers of pixels in the horizontal and vertical directions are determined at the time of manufacturing.
The number of shift stages of the shift registers 21 and 31 described in Section 4 is also determined. Therefore, it is not possible to alternately apply the voltages of the positive and negative polarities to the portion for displaying black only by inputting the video signal. Therefore, in the case where the number of pixels of the video signal is smaller than the number of pixels of the liquid crystal display device, in order to perform black display on a portion other than the portion where the image is displayed, in the pixel of the portion where the image of the liquid crystal display panel is not displayed, It is necessary to be able to alternately apply voltages of opposite polarities for black display.

When the number of pixels of the video signal is smaller than the number of pixels of the liquid crystal display device, various positions can be considered for displaying the image on the screen of the liquid crystal display device. For example, this is a case where the video and the upper left position of the display screen are matched. In another case, for example, as shown in FIG. 15, a video portion is arranged in the center of the display screen. Since it is considered that this is the easiest to see from the viewpoint of the viewing angle, the following description will be made assuming that the image is displayed at the position as shown in FIG.

In any case, in order for the liquid crystal display device to be able to display video signals having different numbers of pixels, the part where the screen image is not displayed when the number of pixels of the video signal is smaller than the number of pixels of the liquid crystal display device. It is also necessary to display a predetermined level of data, and an object of the present invention is to realize an active matrix type liquid crystal display device capable of doing so.

[0012]

In order to achieve the above object, an active matrix type liquid crystal display device of the present invention comprises:
In an active matrix liquid crystal display device including an active matrix liquid crystal panel, a data driver that drives a data line of the liquid crystal panel, and a gate driver that drives a scan line of the liquid crystal panel, the number of pixels in the horizontal or vertical direction of the liquid crystal panel When a video signal with a different number of pixels is input and a part of the liquid crystal panel where the video is not displayed occurs, the pixels in the part of the liquid crystal panel where the video is not displayed have a predetermined voltage during the non-video signal period of the video signal. Is supplied.

Further, in the active matrix type liquid crystal display device according to the second aspect of the present invention, the data driver includes a shift register which shifts according to the dot clock signal of the video signal, and the number of dot clocks in the horizontal scanning period of the video signal. Is smaller than the number of horizontal pixels of the liquid crystal panel,
In the non-driving period of the horizontal scanning period, a clock signal having a frequency higher than that of the dot clock signal is supplied to the shift register of the data driver.

Further, in the active matrix type liquid crystal display device according to the third aspect of the present invention, the gate driver includes a shift register which shifts in accordance with the horizontal synchronizing signal of the video signal, and the horizontal synchronizing in the vertical scanning period of the video signal. When the number of signals is smaller than the number of pixels in the vertical direction of the liquid crystal panel, a scanning signal having a frequency higher than that of the horizontal synchronizing signal is supplied to the shift register of the gate driver during the vertical blanking period of the video signal.

[0015]

1 is a diagram for explaining the principle of the present invention. FIG.
As shown in FIG. 7, in the active matrix type liquid crystal display device of the present invention, a video signal having a number of pixels different from the number of pixels in the horizontal or vertical direction of the liquid crystal panel is input, and a portion where no image is displayed occurs on the display surface of the liquid crystal panel. In some cases, the non-video signal period of the video signal is used to supply the voltage necessary for black display or white display on the non-video portion of the liquid crystal panel, and further for display suitable for other non-video portions. Do it.
As a result, it becomes possible to perform display suitable for the non-image portion even in the portion where the image is not displayed, and to realize an active matrix type liquid crystal display device which can be generally used for the image signal of various modes.

When there are many pixels that need to be supplied with voltage during the non-video signal period, driving at a normal operating speed cannot supply the voltage to all of the pixels required during the non-video signal period. , Increase the operation speed. Specifically, as shown in (1) of FIG. 1, when the number of dot clocks in the horizontal scanning period of the video signal is smaller than the number of pixels in the horizontal direction of the liquid crystal panel, in the non-driving period of the horizontal scanning period, The clock signal supplied to the shift register of the data driver has a higher frequency than the dot clock signal. When the number of horizontal synchronizing signals in the vertical scanning period of the video signal is smaller than the number of pixels in the vertical direction of the liquid crystal panel, as shown in (2) of FIG. The scanning signal supplied to the shift register of the driver has a frequency higher than that of the horizontal synchronizing signal.

[0017]

FIG. 2 is a block diagram showing the configuration of the first embodiment of the present invention. It should be noted that, in the drawings, the same functional portions as those in the drawings described above are denoted by the same reference numerals, and a part of the description will be omitted. In FIG. 2, reference numeral 1 is a liquid crystal panel having pixels of x in the horizontal direction and y in the vertical direction, 2 is a data driver for driving the data lines of the liquid crystal panel 1, and 3 is a scan line of the liquid crystal panel 1. Is a data driver for applying a scan pulse to the data driver, 4 is a data driver clock generation circuit for generating a clock signal to be supplied to the data driver 2, and 5 is a gate driver clock generation for generating a scan clock signal to be supplied to the gate driver 3. Circuit, 6
Is a clock control circuit for performing control such as not changing the output of the data driver 2. The data driver 2 and the gate driver 3 have the same configurations as those shown in FIGS. 13 and 14. The data driver clock generation circuit 4 includes a first clock generation circuit 41 that generates a first clock signal used as a shift clock signal for video data, and a second clock signal that generates a second clock signal having a frequency higher than the first clock signal. It has a clock generation circuit 42 and a 2-1 selector 43 which selects and outputs either the first clock signal or the second clock signal according to the first switching signal. The gate driver clock generation circuit 5 generates a third clock signal corresponding to a horizontal scanning signal.
A clock generation circuit 51, a fourth clock generation circuit 52 that generates a fourth clock signal having a frequency higher than that of the third clock signal, and selects either the third clock signal or the fourth clock signal according to the second switching signal. And output 2-
It has one selector 53.

FIG. 3 shows the data driver clock generation circuit 4, the gate driver clock generation circuit 5 shown in FIG.
FIG. 4 is a diagram showing the clock control circuit in more detail, FIG. 4 is a diagram showing horizontal operation timings of the first embodiment, and FIG. 5 is a diagram showing vertical operation timings of the first embodiment. FIG. 6 is a diagram showing the operation timing of the clock control circuit 5.

The PLL circuit 49 is an integral multiple of the horizontal sync signal / HS of the video signal to the dot clock signal, specifically, 2
It is a circuit that generates a signal with a doubled frequency, and the PLL circuit 4
Since the high-speed clock signal output from 9 is used as the second clock signal, it can be said that the PLL circuit 49 corresponds to the second clock generation circuit 42. The frequency dividing circuit 44 is P
This is a circuit that divides the high-speed clock signal output from the LL circuit 49, specifically, divides it by two to generate a clock signal having the same frequency as the dot clock signal. The clock signal output from this circuit Can be said to correspond to the first clock generation circuit 41, since is the first clock signal. Counter 45, first and second decoder 4
Reference numerals 6, 47 and JK flip-flop (FF) 48 are portions that generate the first switching signal. When the counter 45 counts the second clock signal output from the PLL circuit 49 and the first decoder 46 detects that the count value is equal to the period during which the display data of the video signal is output, the JK-FF 48 outputs 2- The 1 selector 43 is switched to output the second clock signal output from the PLL circuit 49. The counter 45 is reset, similarly counts the second clock signal, and when the second decoder 47 detects that the count value matches the non-video signal period, J
The K-FF 48 switches the 2-1 selector 43 to output the first clock signal output from the frequency dividing circuit 44.
Therefore, as shown in FIG. 4, the first switching signal is "high (H)" during the output period of the display signal of the video signal, and "low (L)" during the other periods. The first switching signal is "H"
During the period (1), the first clock signal is supplied to the data driver 2, and the same operation as in normal video display is performed. While the first switching signal is "L", the data driver 2
The clock signal is supplied, and the shift pulse is shifted faster than usual. During the period when the first switching signal is "L", the voltage applied to the pixels of the non-image portion, that is, the voltage of the positive / negative reverse polarity corresponding to the black display is alternately applied to the data driver 2 when the black display is performed. Is supplied to.

In the vertical direction, the horizontal synchronizing signal / HS is used as it is as the third clock signal. The frequency multiplication circuit 54 uses the horizontal synchronization signal / HS to output the fourth frequency of an integer multiple.
It can be said that the frequency dividing circuit 54 is a circuit for generating a clock signal and corresponds to the fourth clock generating circuit 52. The counter 55, the third and fourth decoders 56 and 57, and the JK flip-flop (FF) 58 are parts that generate the first switching signal. When the counter 55 counts the horizontal synchronizing signal / HS and the third decoder 56 detects that the count value becomes equal to the value of the vertical row of the video signal, the JK-FF 58 doubles the 2-1 selector 53. Circuit 5
It is switched so as to output the fourth clock signal output by the signal No. 4. The counter 55 is reset, counts the horizontal synchronizing signal / HS in the same manner, and when the fourth decoder 57 detects that the count value matches the vertical blanking period, JK
-FF58 causes 2-1 selector 53 to output horizontal sync signal / HS
To output. Therefore, as shown in FIG. 5, the second switching signal becomes “high (H)” during the output period of the display signal in the vertical direction of the video signal and “low (L)” during the vertical retrace line period. While the second switching signal is "H",
The third clock signal is supplied to the gate driver 3, and the same operation as the normal image display is performed. While the second switching signal is "L", the fourth clock signal is supplied to the gate driver 2 and the shift pulse is shifted faster than usual. The display signal portion of the video signal shown in FIG. 5 is actually a continuous video signal as shown in FIG.

When the frequency of the fourth clock signal for driving the shift register of the gate driver 3 is increased during the vertical blanking period, it is necessary to increase the operating speed of the data driver 2 accordingly. However, this causes a problem that the data driver 2 becomes large and the cost also increases. The clock control circuit is a circuit for solving such a problem.

The data output from the data driver 2 while the second switching signal is "L" may be constant data corresponding to black display or the like. Therefore, if the data to be displayed for one line of the data driver 2 is held after the second switching signal becomes "L", the second switching signal becomes "L".
There is no need to hold new data until the end of the period. Therefore, it is not necessary to shift the clock signal in the data driver 2, and the speed can be increased.

The clock control circuit 6 includes a counter 61 and
It has fifth and sixth decoders 62 and 63 and a JK flip-flop (FF) 64. The counter 61 counts the horizontal synchronizing signal / HS, and when the fifth decoder 62 detects that the count value is larger than the value of the vertical row of the video signal by 1, the JK-FF 64 outputs 2-
The 1 selector 64 is switched so that the "L" signal is output. The counter 61 is reset, counts the horizontal synchronizing signal / HS in the same manner, and the sixth decoder 6 determines that the count value matches a value smaller by 1 than the vertical blanking period.
When 3 is detected, the JK-FF 64 is the 2-1 selector 64.
Is switched to output the clock signal output by the data driver clock generation circuit 4.

Therefore, the signal output from the clock control circuit 6 is "low (L)" for a period shorter than the vertical blanking period by one horizontal scanning period, as shown in FIG. 6, and to the data driver 2 during that period. The supply of the clock signal is stopped. When the output of the last line of the video signal is completed and the second switching signal is switched to "L", the data to be displayed in the non-video part such as black display is supplied, and this data is held for one line of the data driver. To be done. When the data of the non-video portion is held in one line of the data driver, the supply of the clock signal to the data driver is stopped, so the held data remains as it is until the vertical blanking period ends. Figure 6
In the above, the clock signal input to the data driver during this period is shown as being input with the first clock signal as in the case of normal display, but this may be used as the second clock signal.

Data is written in the pixels of the portion that displays black during the period when no video data is input, but the period during which no video data is input is usually not very long, and if a clock signal similar to the display period is used, black display is performed. It is difficult to write data to all the pixels of the part to be performed. However, as in the present embodiment, by increasing the speed of the clock signal during the period when the video data is not input, it becomes possible to write the data to all the pixels of the portion that displays black.

In the first embodiment, both the data driver clock generating circuit 4 and the gate driver clock generating circuit 5 are used. However, when there is a portion where the video signal is not displayed only in one direction of the liquid crystal display screen, one of them is used. Only the above configuration may be used. Further, in order to reduce the shift operation of the display data in the vertical blanking period, the clock control circuit 6 is used to write the data only for one horizontal line. The circuit 6 may not be used.

FIG. 7 is a diagram showing the structure of the liquid crystal panel of the second embodiment. As is apparent from comparison with FIG. 12, in the liquid crystal panel of the second embodiment, the data driver and the gate driver are provided on both sides of the panel, and the data line and the scan line are alternately extended from the drivers on both sides. The point is different from that of FIG. Such a structure is called a comb structure.

FIG. 8 is a diagram showing the structure of the liquid crystal display device of the second embodiment. As is apparent from comparison with FIG. 2, the liquid crystal display device according to the first embodiment is provided with data drivers 2a and 2b, gate drivers 3a and 3b, and a video signal upper / lower half circuit 8 on both sides of the liquid crystal panel 1. The point is different. In the second embodiment as well, as in the first embodiment, by increasing the frequency of the clock signal input to the driver during the blanking period of the video signal, data can be written in the non-video display portion.

In the first embodiment, the frequency of the clock signal input to the driver is increased during the blanking period of the video signal so that the data can be written in the non-video display portion. The frequency is limited due to the driving speed of the driver, and it is difficult to scan too many data drivers and gate drivers during the blanking period of the video signal. Therefore, the operation speed of the data driver can be halved by dividing the data driver into two and halving the number of lines that each driver needs to drive. In the case of FIG. 7, the display data of the even-numbered columns is the upper data driver 2a.
Therefore, the display data of the odd-numbered columns is stored in the lower data driver 2b
Supplied from The upper data driver 2a and the lower data driver 2b are operated in parallel.

As for the gate driver, as shown in the timing chart of FIG. 9, the left and right gate drivers 3a are provided.
And 3b are operated in parallel, and the operating frequency can be reduced to half by enabling left and right alternately so that the two gate drivers are not turned on at the same time. Of course, only one of the data driver and the gate driver may be divided.

Further, as in the first embodiment, a clock control circuit may be provided to cause the data driver to hold the data of the non-video portion at the beginning of the vertical blanking period and maintain that state. Usually, in the shift register of the data driver and the gate driver, one shift pulse is sequentially shifted. Therefore, even in the case where the video portion is arranged substantially in the center of the display screen as shown in FIG. 15 in the first and second embodiments, one shift pulse is sequentially shifted in the shift registers of the data driver and the gate driver. It Therefore, in the case of a gate driver, a shift pulse is input to the gate driver from about the midpoint of the blanking period, and the shift pulse reaches the start position of the video portion of the screen by the end of the blanking period with the high-speed scanning clock signal. To be shifted. Then, a normal scanning pulse is input to the video portion so that the shift pulse is shifted to the end position of the video portion of the screen. And
The high-speed scanning clock signal is used again so that the shift pulse reaches the lower end of the screen by about the middle point of the blanking period.

In the third embodiment, the shift speed of the shift pulse in the blanking period is reduced to half. FIG.
0 is a diagram for explaining the shift pulse of the gate driver in the third embodiment. As shown in FIG. 10, in the third embodiment, a new shift pulse is input when the shift pulse is shifted to the end position of the video portion of the screen. As a result, the portions where the upper and lower images are not displayed are scanned in parallel at the same time. When the newly input shift pulse is shifted to the start position of the image part of the screen, the previously input shift pulse reaches the lower edge of the screen, so it passes through the shift register and is not displayed. It has no effect. By doing so, only the upper half or the lower half of the portion where no image is displayed is scanned during the blanking period, and the shift speed of the shift pulse may be half. This method can be applied to the data driver as well.

With the configuration of the third embodiment, the shift speed of the shift pulse can be halved, so that it is not necessary to make the operating speed of the data driver and the gate driver remarkably faster than in normal use. for that reason,
Therefore, a low-speed driver can be used and the time for writing data in the liquid crystal can be extended.

[0034]

As described above, according to the present invention,
It is possible to display a video signal with a smaller number of display dots than the display pixels of the liquid crystal, and it is possible to support each display mode with one liquid crystal panel, allowing the liquid crystal display device to be used more generally. become.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the first embodiment.

FIG. 3 is a diagram showing details of a clock generation circuit of the first embodiment.

FIG. 4 is a diagram showing horizontal operation timings in the first embodiment.

FIG. 5 is a diagram showing vertical operation timings in the first embodiment.

FIG. 6 is a diagram showing an operation timing of the clock control circuit of the first embodiment.

FIG. 7 is a diagram showing a configuration of a liquid crystal panel of a second embodiment.

FIG. 8 is a block diagram showing an overall configuration of a second embodiment.

FIG. 9 is a diagram showing the operation of the gate driver of the second embodiment.

FIG. 10 is a diagram showing a shift pulse according to a third embodiment.

FIG. 11 is a diagram showing a basic configuration of a TFT type liquid crystal display device.

FIG. 12 is a diagram showing a configuration example of a conventional liquid crystal panel.

FIG. 13 is a diagram showing a configuration example of a conventional data driver.

FIG. 14 is a diagram showing a configuration example of a conventional gate driver.

FIG. 15 is a diagram showing an example of displaying a video signal on a part of the screen.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel 2 ... Data driver 3 ... Gate driver 4 ... Data driver clock generation circuit 5 ... Gate driver clock generation circuit 6 ... Clock control circuit

Claims (12)

[Claims] 1. An active matrix comprising an active matrix type liquid crystal panel (1), a data driver (2) for driving a data line of the liquid crystal panel, and a gate driver (3) for driving a scan line of the liquid crystal panel. Type liquid crystal display device, when a video signal having a number of pixels different from the number of pixels in the horizontal or vertical direction of the liquid crystal panel (1) is input and a part where no image is displayed occurs on the display surface of the liquid crystal panel, the liquid crystal panel An active matrix type liquid crystal display device, characterized in that a predetermined voltage is supplied to the pixels in the non-display part of the video signal during the non-video signal period of the video signal. 2. The data driver (2) includes a shift register that shifts according to a dot clock signal of the video signal, and the number of dot clocks in the horizontal scanning period of the video signal is a pixel in the horizontal direction of the liquid crystal panel. 2. The active matrix type according to claim 1, wherein a clock signal having a frequency higher than that of the dot clock signal is supplied to the shift register of the data driver during a non-driving period of the horizontal scanning period when the number is smaller than the number. Liquid crystal display device. 3. The gate driver (3) includes a shift register that shifts in accordance with a horizontal synchronizing signal of the video signal, and the number of horizontal synchronizing signals in a vertical scanning period of the video signal is the liquid crystal panel (1). 2. When the number of pixels in the vertical direction is smaller than the number of pixels in the vertical direction, a scanning signal having a frequency higher than that of the horizontal synchronizing signal is supplied to the shift register of the gate driver during the vertical blanking period of the video signal. Two
The active matrix liquid crystal display device according to item 1. 4. The data driver (2) fetches data of one line at the start of the vertical blanking period and outputs the data until the display data of the video signal is input next. The active matrix liquid crystal display device according to claim 3. 5. When the number of dot clocks in the horizontal scanning period of the video signal is smaller than the number of pixels in the horizontal direction of the liquid crystal panel, the display portion of the video is set to the substantially center of the liquid crystal panel, and the portion where the video is not displayed is set to the center. The active matrix liquid crystal display device according to claim 1, wherein the active matrix liquid crystal display device is provided on both sides. 6. When the number of dot clocks in the horizontal scanning period of the video signal is smaller than the number of pixels in the horizontal direction of the liquid crystal panel, the video display portion is set to be substantially the center of the liquid crystal panel, and the non-video display portion is set. The active matrix type liquid crystal display device according to claim 2, wherein the liquid crystal display device is provided on both sides. 7. The shift register of the data driver is further input with a shift pulse at the start of a non-driving period of the horizontal scanning period, and shifts two pulses in parallel. The active matrix liquid crystal display device according to item 1. 8. When the number of horizontal synchronizing signals in the vertical scanning period of the video signal is smaller than the number of pixels in the vertical direction of the liquid crystal panel, the display portion of the video is substantially in the center of the liquid crystal panel and no video is displayed. The active matrix type liquid crystal display device according to claim 1, wherein the portions are provided above and below. 9. When the number of horizontal synchronizing signals in the vertical scanning period of the video signal is smaller than the number of pixels in the vertical direction of the liquid crystal panel, the display portion of the video is set to substantially the center of the liquid crystal panel and the video is not displayed. 6. The active matrix type liquid crystal display device according to claim 3, wherein the portions are provided above and below. 10. The shift register of the gate driver is further input with a shift pulse at the start of the vertical blanking period, and the two pulses are shifted in parallel, so that pixels on the upper and lower sides of the image are not displayed. 9. The active matrix type liquid crystal display device according to claim 8, wherein voltage is supplied at the same time. 11. The data driver is provided on each of upper and lower sides of the liquid crystal panel, and the data lines extend alternately from the data drivers on both sides of the liquid crystal panel. The active matrix liquid crystal display device according to item 1. 12. The gate driver is provided on both sides of the liquid crystal panel, and the scan lines extend alternately from the gate drivers on both sides. The active matrix liquid crystal display device described.