JP2924842B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of displaying a television signal such as NTSC or PAL.

[0002]

2. Description of the Related Art At present, there is an increasing demand for a thin and lightweight flat panel display as a personal computer or an audio visual display device instead of a CRT display. A liquid crystal display device is generally used as the flat panel display. This liquid crystal display device is thinner and lighter than a CRT display, so that a dead space generated when laying out a monitor display can be minimized and can be realized with low power consumption. As such a liquid crystal display device, there is a liquid crystal television for displaying a signal such as a television and a video (hereinafter, referred to as a video signal). Conventionally, when a video signal is displayed on a liquid crystal display device, a technology for displaying the video signal using a digital technique such as scanning line interpolation using a memory so as to have the same number of scanning lines as a CRT display, and in particular, for converting a video signal into a digital signal, There has been reported a technique for performing display by devising a driving method without performing processing. Hereinafter, each technique will be described.

[Conventional Example 1] FIG. 8 is a block diagram showing a technique for processing and displaying a video signal using a digital technique. Here, a double-speed conversion technique is used. This liquid crystal display device includes a liquid crystal display panel 17, an X driver 14,
A liquid crystal module 16 is configured by the driver 15,
A video signal input to the input terminal 11 is input to the X driver 14 via a double speed conversion circuit 20 and a polarity inversion circuit 13. FIG. 9 is a configuration diagram of each part of the liquid crystal module 16 and the liquid crystal display panel 17. The liquid crystal display panel 17 includes a thin film transistor 25 (hereinafter abbreviated as TFT), an additional capacitor 26, and a liquid crystal 2.
7, a data line 28, a pixel electrode 29, a common electrode 30, and gate lines Y1, Y2,. Data line 28 is T
The gate line Yl is connected to the drain D of the FT25,
It is connected to 25 gates G. Source S of TFT25
Is connected to the pixel electrode 29, and the pixel electrode 29 and the common electrode 30
The space between them is filled with liquid crystal 27. Also, the pixel electrode 29
An additional capacitor 26 for maintaining a stable pixel potential is connected between the common electrode 30 and the common electrode 30. When the TFT 25 is turned on by a gate signal, a pixel signal is supplied to the liquid crystal 27 and the additional capacitor 26. The data lines 28 are usually provided in the order of several hundreds.

[0004] The X driver 14 samples and holds the input video signal Sin, and outputs the TF provided to each pixel of the liquid crystal display panel 17 of the liquid crystal module 16.
A signal is output to the T data line. The X driver 14 includes a shift register 21, a level converter 2
2. Sample hold circuit 23, buffer driver 24
It is composed of When the start pulse STH indicating the start of the horizontal display period is supplied, the shift register 21 sequentially turns on from the first register of the shift register 21 at a timing synchronized with the horizontal clock CLK, and outputs an on pulse. When two X drivers are used, a carry-out occurs when the bit shift of the ON pulse in the first stage X driver is completed, and the start pulse STH of the shift register of the next stage X driver 14 is obtained. Since the horizontal clock CLK is double-speed scanning, the horizontal clock CLK has a timing such that the on-pulse of the shift register is output twice as many as the horizontal pixels of the liquid crystal module during one horizontal effective scanning period. For example, if the number of pixels in the horizontal direction is 7
In the case of 50 pixels, if one horizontal effective scanning period is 50 μsec, the horizontal clock CLK is 30 MHz. The level converter 22 amplifies the ON pulse of the shift register 21 and outputs the amplified ON pulse to the sample and hold circuit 23. The sample hold circuit 23 samples and holds the input video signal Sin at the timing of an on-pulse from the level converter 22. Thus, the sample and hold circuit 23 holds signals of a plurality of pixels controlled by one gate line of the liquid crystal module. The output from the sample and hold circuit 23 is
, And the buffer driver 24 outputs the output instruction signal OE.
The output of the sample-and-hold circuit 23 is amplified by the ON signal, and is output to the data line 28 of the TFT 25 of the liquid crystal module. The output instruction signal OE is turned on during the retrace period of the video signal Sin waveform (a) as shown in FIG.

On the other hand, a Y driver 15 is a device for controlling a gate line of a TFT. The pixel signal output from the X driver 14 to the data line 28 by the gate signal is set to 1
It is controlled to supply only to the TFT to which the gate line is connected. Referring to FIG. 10, it is assumed that the signal Yl represents the signal of the gate line Yl connected to the Y driver 15, and the signal Y2 represents the signal of the gate line Y2. The gate line Yl is a gate line that is turned on first, and an on signal is output from the Y driver 15 to the gate line Yl at the same time as the on signal of the first OE in the field period, so that the gate line is turned on for about 1/2 horizontal scanning period. At this time, all the gate lines other than the gate line Yl are off. Next, when the gate line Yl is turned off, the gate line Y2 is turned on instead. Similarly, when the gate line Y2 is turned off, the next gate line is turned on, and the gate lines are sequentially turned on from top to bottom. as a result,
A signal can be written to all pixels of the liquid crystal module in one field period. Thus, the Y driver 15
In accordance with the timing of the output from the driver 14, an ON signal is sequentially output to each gate line for about 水平 horizontal scanning period, and the TFT supplies a pixel signal from the X driver 14 to the liquid crystal 27 when the gate line is ON. can do.

Next, the double speed conversion circuit 12 will be described. When a video signal as shown in FIG. 10A is input to the input terminal 11,
A video signal is output in a half of one horizontal scanning period as shown in FIG. 3B, that is, a signal is output at double speed. Such a double-speed conversion circuit includes a typical circuit for clear vision broadcasting using a field period memory and a circuit using a horizontal scanning period memory for its representative circuit.
Both circuits convert to double speed by digital processing. Here, a double speed conversion circuit using a horizontal scanning period memory will be described.

FIG. 11 shows a simple configuration example of a double-speed conversion circuit using a horizontal scanning period memory, and FIG. 12 shows an operation waveform diagram thereof. In FIG. 11, a video signal as shown in FIG. This signal passes through a low frequency band pass filter (LPF) 43,
Varying the digital signal by the D converter device (A / D) 44
After the conversion , the data is selectively input to one of the two horizontal scanning period memories 41a and 41b by the switch 45. The switcher 45 is doing switching operation by the switching control signal SWP. It illustrates the timing of the switching control signal SWP in Fig. For example, the switch 45 is connected to the horizontal scanning period memory 41a when the switching control signal SWP is at a high level, and is connected to the horizontal scanning period memory 41b when the switching control signal SWP is at a low level. As an example, when SWP is at a high level, that is, when the switch 45 is turned on as shown in FIG.
A description will be given of the case where the connection is made to the connection a. The digital video signal input to the horizontal scanning period memory 41a is approximately 16 when the horizontal scanning period memories 41a and 41b are 1K word memories.
It is sampled and held by the write clock WCLK of MHz. The write clock WCLK is switched by the switch 49 with the read clock RCLK. Switching of the switching 49 is performed by the same switching control signal SW as that of the switch 45.
The write clock WCLK is input to the horizontal scanning period memory to which the switch 45 is connected, and the read clock RCLK is input to the horizontal scanning period memory to which the switch 45 is not connected. is there.

The switch 45 is switched in one horizontal scanning period by the SWP shown in FIG.
A is switched after sampling and holding one horizontal scanning signal, and is connected to the memory 41b during the horizontal scanning period. The signal held in the horizontal scanning period memory 41a is output through the switch 46. The switch 46 is provided with the switching control signal SWP.
Are switched by a control signal XSWP obtained by inverting. At the time of switching, the clock of the memory 41a is also switched from the write clock WCLK to the read clock RCLK by the switch 49 during the horizontal scanning period. The read clock RCLK has a frequency twice that of the write clock WCLK. For example, when using a 1-K word memory, the write clock WCLK is 16 MHz, but the read clock RCLK is about 32 MHz. The signal read through the switch 46 is supplied to a D / A converter device (D / A
A) The signal is converted into an analog signal by 47, and is output to the output terminal 48 through the low-frequency band-pass filter LPF43.

As described above, the horizontal scanning period memory 4
Since 1a is read at twice the frequency of writing, it outputs to the first word again after outputting the last word of the held signal and outputs the signal. Therefore, a signal is output twice within one horizontal scanning period, and the video signal is output as shown in FIG.
It is a double speed signal like The polarity inversion circuit 13
Converts the video signal converted into a signal having a double horizontal frequency by the double speed conversion circuit 12 into a signal whose polarity is inverted at a half of a field period cycle or a horizontal scanning period cycle, and then converts the signal into an X driver 14. To enter.

As described above, when the liquid crystal module performs double-speed line sequential scanning, as shown in FIG. 11, a low-frequency band-pass filter, an A / D converter, a horizontal scanning period memory,
A video signal is converted to double speed and displayed using a digital circuit including an A / A converter. Therefore, both the circuit scale and the cost are large, and the frequency characteristics of the X driver are twice as large as those of the standard signal. When the number of pixels in the horizontal direction is 750 pixels in the horizontal direction, if the horizontal effective scanning period is 50 μsec, it becomes as fast as 30 MHz, making it difficult to implement an X driver in a medium-voltage CMOS integrated circuit.

[Conventional Example 2] FIG. 13 is a configuration diagram showing a technique for displaying a display by devising a driving method among the above-mentioned conventional techniques. This prior art example 2 is reported in Japanese Patent Application Laid-Open No. 3-280676. In the block diagram shown in the figure, the same reference numerals are given to parts equivalent to the conventional example 1. However, in the driving circuit of the liquid crystal display device of the conventional example 2, there is no double speed conversion circuit.
The difference from the first conventional example is that the driver 15A has a function of simultaneously outputting an ON signal to two adjacent gate lines and a function of shifting the gate lines to be turned on in the odd field and the even field by one gate line. . That is, the liquid crystal module 16 has a lattice pixel array, similarly to the configuration of the conventional example 1. Further, as in the first conventional example, the video signal Sin input to the X driver is sampled at the timing of the on-pulse of the level converter 22 and is held by the sample-and-hold circuit 23. The ON pulse of the level converter 22 is supplied to the shift register 2 in the same manner as in the prior art 1.
One ON pulse is amplified, and this ON pulse is output at the timing of the horizontal clock CLK. Since the horizontal clock CLK is double-speed sequential scanning in Conventional Example 1, the number of pixels in the horizontal direction is 750 pixels, and one horizontal effective scanning period is 50 μs.
In the case of ec, the frequency is 30 MHz, but in the second conventional example, the on-pulse may be output from the shift register 21 by the number of pixels in the horizontal direction in one horizontal scanning period. Will be.
The signal held by the sample and hold circuit 23 is supplied to the buffer driver 24 as in the first conventional example.
The signal is output to the data line 28 by the ON signal of the output instruction signal OE. OE is the video signal Sin waveform (a) as shown in FIG.
(In this case, ON is referred to as a high level state).

Next, the operation of the Y driver will be described. In the first conventional example, the Y driver 15A is sequentially turned on by one gate line, but in the second conventional example, the gate lines Y1 and Y2 are simultaneously turned on as shown in FIG. Signal Y in FIG.
1, Y2 are gate lines Yl, Y2 connected to the Y driver.
Signal. The gate lines Yl and Y2 are turned on at the same time as the OE, are turned on for one horizontal scanning period, and turned off at the next OE. Next, instead of turning off Yl and Y2, Y
3 and Y4 are turned on for one horizontal scanning period. This gives 2
The same signal is written to the line, and this operation is sequentially performed to
Write signals to all pixels in the field. Polarity inversion circuit 1
3 converts the signal into a signal whose polarity is inverted in the field period cycle or the horizontal scanning period cycle and inputs the signal to the X driver 14 in the same manner as in the conventional example 1.

In Conventional Example 2, signal writing to pixels is repeated by turning on two gate lines simultaneously during one horizontal scanning period. Therefore, when the liquid crystal module has 480 pixels in the vertical direction, about 240 pixels are used. Vertical resolution. Therefore, in the second conventional example, as shown in FIG. 15, the gate lines are further turned on by one gate line in the odd field and the even field in order to increase the resolution. This is because the gate lines Y1 and Y2 are turned on at the same time in the odd field, and then the gate lines Y3 and Y4 are turned on at the same time, whereas the gate lines Y2 and Y3 are turned on at the same time in the even field and then the gate lines Y4 and Y4. The Y driver 15A is set to turn on Y5 at the same time. By shifting the gate lines that are turned on in the odd and even fields, the display becomes closer to the interlaced scanning display of the CRT, and the vertical resolution is improved to about 330 lines. As a result, a sufficient resolution can be obtained even in a lattice pixel array, and a low-cost medium-voltage CM having no double-speed conversion circuit as in the conventional example 1 is required.
The display can be made using the OS integrated circuit X driver. However, in this example, the configuration of the Y driver is unique to this method, and the versatility is applied. In addition, when viewed on the field time axis, signals of the same polarity are written to specific lines of two consecutive fields, so that the DC component of each liquid crystal element is canceled. Is likely to be insufficient, and there is a concern about flicker noise that occurs.

[0014]

The following problems are also encountered in the techniques of the prior arts 1 and 2 described above. The first problem is that, in the second conventional example, writing to the gate line is shifted by one gate line in the odd field and the even field, so that two consecutive lines are seen on the field time axis.
A signal of the same polarity is written to a specific line of the field,
Therefore, cancellation of the DC component of the liquid crystal element tends to be insufficient, and the flicker noise that flows from the top to the bottom or from the bottom to the top occurs due to accumulation of the DC component despite the increased resolution.

The second problem is that the prior art 2 employs a configuration in which two adjacent gate lines are simultaneously turned on, which is different from a general Y driver configuration. It is necessary to change the configuration of the Y driver itself in order to be compatible with the method of sequentially driving each time, and in some cases, the circuit scale is increased, which leads to an increase in cost.

Further, the third problem is that, when the flicker noise is to be solved by a digital processing technique as in the conventional example 1, depending on the processing method in the X driver direction in the conventional example 2, the horizontal driving of the X driver is performed. The clock becomes twice the system clock, and the X driver
It becomes difficult to form a MOS integrated circuit. In addition, the use of digital processing technology requires a low-frequency band-pass filter, an A / D converter, a memory, a D / A converter, and the like. As a result, the size of the signal processing circuit increases, resulting in a significant increase in cost. .

An object of the present invention is to provide NTSC or PAL
As a liquid crystal display device that displays TV signals such as TV, it is possible to increase the resolution without increasing the circuit scale, and even in that case, reduce the flicker noise caused by the accumulation of the DC component in the liquid crystal element. It is an object of the present invention to provide a liquid crystal display device which is enabled.

[0018]

According to the present invention, there is provided a liquid crystal display device for supplying a video signal to a scanning line side Y driver and a signal line side X driver provided in an active matrix type liquid crystal display panel. In addition to the signal processing circuit, a polarity inversion circuit for converting the liquid crystal display panel into a signal that can be driven without deteriorating the image quality, a timing generation circuit for generating a timing signal for controlling the Y driver and the polarity inversion circuit, and And the odd field is
Scanning lines 2n-1 and 2n, and even fields
Same video signal for 2n-th line and 2n + 1-th line
(N = 0, 1, 2, 3, ...)
A positive integer, including m, is half the number of scanning lines on the liquid crystal display panel.
1 where 1 ≦ 2n−1,2n, 2n + 1 ≦ 2m
And the polarity of the video signal applied to each liquid crystal element of the liquid crystal display panel is such that the direction in which the polarity of the video signal changes on the field time axis is not fixed.
As shown in FIG.
The polarity inverting circuit is controlled by a timing signal so as to rotate. As described above, the polarity of the video signal applied to each liquid crystal element of the liquid crystal display panel is changed every four fields.
By reversing the direction of change in polarity, for example, the fourth field the polarity of the video signal to be input to the liquid crystal element from the first field + polar → + polarity → - polar → - Once the polarity of the next 4 Fields 5 to 8
Up to the field, the opposite-polarity →-polarity → + polarity → +
By controlling the pattern to reverse the polarity,
It is possible to remove the superposition of the DC component which causes flicker noise.

Here, in order to display the same video signal on the (2n-1) -th and 2n-th and 2n-th and 2n + 1 -th liquid crystal display panels, the speed of the ON period of the scanning line Y driver is one horizontal scanning period. scanning at twice the speed of.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an embodiment of the liquid crystal display device of the present invention. It is to be noted that the same reference numerals are used for portions equivalent to the configurations of the above-described conventional examples. That is, the liquid crystal module 16 includes a liquid crystal panel 17, an X driver 14 for driving the liquid crystal panel 17, and a Y driver.
It is composed of a driver 15. Then, a video signal input to the input terminal 11 is supplied to the X driver 14 via a signal processing circuit 12 and a polarity inversion circuit 13, and the configuration is the same as that of the previous embodiment. In the configuration, a timing generation circuit 1 for supplying a control signal to be described later to the X driver 14 and the Y driver 15
8 are provided.

The signal processing circuit 12 includes an X driver 14
Is a circuit that converts a video signal into a format that conforms to the input specifications of, for example, when a video signal such as a video signal is input, the video signal is decomposed into color primary color signals RGB. Therefore, a configuration using a digital technique such as a double-speed conversion technique is not employed here. Since this circuit has a well-known circuit configuration, a description of the specific circuit configuration will be omitted.

FIG. 2 shows the X driver 14 and the liquid crystal panel 1.
7 is a diagram showing the configuration of FIG. 7. This X driver 14 samples and holds an input video signal Sin as shown in FIG. 7 and is arranged in each pixel of a liquid crystal display panel 17 of the liquid crystal module 16. A signal is output to a data line 28 of the TFT , and is composed of a shift register 21, a level converter 22, a sample and hold circuit 23, and a buffer driver 24. The shift register 21 has a start pulse S indicating the start of a horizontal display period.
When TH is supplied, the shift register 21 sequentially turns on from the first register at a timing synchronized with the horizontal clock CLK, and outputs an ON pulse. X driver 2
In the case of using, the carry-out occurs when the bit shift of the on-pulse in the first stage X driver is completed, and the next stage X driver
Start pulse STH of shift register of driver 14
Becomes Note that the horizontal clock CLK is a clock having a timing such that an ON pulse of the shift register is output only for pixels in the horizontal direction of the liquid crystal module 16 during one horizontal effective scanning period. For example, when the number of pixels in the horizontal direction is 750, if one horizontal effective scanning period is 50 μsec, 1
The horizontal clock CLK is 5 MHz. That is, the frequency is one half that of the horizontal clock CLK of the first conventional example.
The level converter 22 amplifies the ON pulse of the shift register 21 and outputs the amplified ON pulse to the sample and hold circuit 23.
The sample hold circuit 23 receives the input video signal Sin
At the timing of the on-pulse from the level converter 22. Thus, the sample and hold circuit 23 holds signals of a plurality of pixels controlled by one gate line of the liquid crystal module. The output from the sample and hold circuit 23 is supplied to a buffer driver 24. The buffer driver 24 amplifies the output of the sample and hold circuit 23 with the ON signal of the output instruction signal OE, and outputs the amplified signal to the data line 28 of the TFT of the liquid crystal module 16. doing.

On the other hand, as shown in FIG. 3, the timing generation circuit 18 includes counters 31 and 34 and the counter 3
A decoder 33 for outputting an X driver control signal based on the X-direction display position control data 32 in response to the output of the counter 1;
5 that outputs a Y driver control signal based on
6 is provided. Further, D-type flip-flop circuits (DF / F circuits) 37 and 38 for dividing the frequency of Vsync, and E
An X-OR circuit 39 is provided to output polarity control signals POTA and POTB to be described later.

The operation of the embodiment having the above configuration will be described.
In this liquid crystal display device, the timing generation circuit 18 converts the gate signals Y1, Y2,... And the polarity control signal POTA for controlling the polarity of the output signal of the polarity inversion circuit 13 into noise as shown in FIGS. It is characterized in that it is controlled for the purpose of reducing noise. That is, the output instruction signal OE input to the X driver 14 is turned on during the retrace period of the video signal Sin waveform (a) as shown in FIG. In the conventional example 1, the Y driver 15 sequentially turns on one gate line at a time, and in the conventional example 2, two adjacent gate lines are simultaneously turned on. However, in this embodiment, a half of one horizontal scanning period is used. Gate lines are sequentially turned on. The signal Yl in FIG. 4 represents the signal on the gate line Y1 connected to the Y driver 15 in FIG. 2, and the signal Y2 represents the signal on the gate line Y2.
That is, Y1, Y2, Y3,... Shown in FIG. 4 are the same as the gate lines connected to the Y driver.

These gate lines Y1, Y2, Y3,.
Are sequentially turned on in a half horizontal scanning period. That is, a method is employed in which the on-time of the gate line is moved at a double speed without turning on the two gate lines at the same time as in Conventional Example 2. The control of the on-time of the gate line is the same as in the first conventional example.
Here, the scanning speed of the gate line is set to 2 in one horizontal scanning period.
The reason for setting the value to 1/1 is that the same video signal is written to two lines in one horizontal scanning period, so that an interpolation signal for one line is pseudo-generated on the liquid crystal display panel. Interpolation generally indicates that a signal for one line is artificially generated when an interlaced signal such as a video signal is displayed in a non-interlaced manner. Also, since this is interpolation, it shows the same circuit operation as the enlarged display operation such as multi-scan, but the purpose is different. With this operation, signals can be written to all pixels in one field.

The writing in the next field will be described. In the operation of the next field, that is, the second field, the same gate line operation as that of the first field is performed. However, since it is desired to realize the same resolution as the CRT as in the second conventional example,
Writing is shifted by one gate line for each field. The next third
The field is written at the timing of the first field, and the fourth field is written with the signal to all the pixels at the timing of the second field. That is, signals are written by shifting one gate line in the preceding and succeeding fields. However, here, as seen in the question between the fourth field and the fifth field in FIG. 7, a singular point occurs such that the gate line is not shifted once every four fields.

Next, when the same video signal is supplied to the liquid crystal pixels from the X driver during the ON period of the two gate lines, and the display is performed so as to increase the resolution by shifting one gate line for each field, FIG. As seen from the field time axis, the video signal of the same polarity is written to the specific lines of two consecutive fields, so that the DC level of each liquid crystal element is likely to be insufficiently canceled, and from the top to the bottom or from the bottom to the top. A so-called flicker noise-like one in which a DC component flows is generated. Therefore, in this embodiment, when a video signal as shown in FIG. 4A is input to the input terminal 11 of FIG. 1, the video signal input to the polarity inversion circuit 13 via the signal processing circuit 12 is After the polarity is converted in the field period cycle or the horizontal scanning period cycle, it is input to the X driver 14.

In the polarity inversion circuit 13 described above, since the polarity management is further performed for each field, the control signal PO shown in FIG.
The polarity is managed by TA. As shown in FIG. 5, the polarity of the control signal POTA of the polarity reversing circuit is managed for each field, and the control signal POTA also has a form in which the control signal is turned back every four fields. When the polarity of each field is managed in this relation, the output signal of the polarity inversion circuit 13, that is, the polarity of the leftmost pixel of the Gl line is applied to each pixel of the liquid crystal display panel 17 as shown in FIG. Is a field cycle, which is one polarity → + polarity → + polarity → one polarity → one polarity → + polarity → + polarity → −polarity. Focusing on the minus (1) component here, the change of the minus component is different from the change in the range of four pixels in the field direction, and the operation does not always move upward or downward. In addition, since the folding operation is performed for four vertical pixels in the field direction, a canceling effect also appears.

In the prior art, the control operation of the polarity inverting circuit is controlled by a simple control signal whose polarity alternates every two fields like the POTB of FIG. The change of the component is a change within one screen, and the change is large and conspicuous as compared with the present invention. In other words, conventionally, in the case of a liquid crystal display panel having 480 lines, the variation of this noise is 48
Although the line appeared to be one period in the 0 line, the present invention
When the line changes to a one-period one and the traveling direction also changes, a canceling effect also appears, so that the remaining DC component is alleviated and this noise component is reduced.

Here, the above-mentioned timing generation circuit 18
The operation of the polarity inversion circuit when generating a POTA signal for managing the polarity in the field and a Y driver control signal serving as a source of a gate line ON signal will be described. The Y driver control signal is input to a counter 34 that performs a count-up operation using Vsync as a counter clock. Next, the output of the counter 34 is the Y direction display position control data 3
The data is input to the decoder 36 in the same manner as the five-output data. The decoder 36 is configured to output a positive polarity pulse when the value of both the counter 84 and the Y direction display position control data 35 match. The output pulses of the decoder 36 of the gate line signals Y1, Y2,... Are transferred by the Y driver vertical clock. Further, the polarity control signal POTA converts the Vsync signal to D-
The frequency is divided by the F / F circuits 37 and 38, and the D / F-F circuit 3
7 and 38 are input to an EX-OR circuit 39,
A timing signal as shown in FIG. 5 is generated. Here, the generation of the X driver control signal is also shown, but the description is omitted because it has the same configuration as the generation of the Y driver control signal and is not directly related to the present invention.

In the above-described embodiment, the description has been given of the method of sequentially turning on the gate lines. However, the method of performing the simultaneous gate-on operation as in the conventional example 2 to display the liquid crystal display panel is also used. It goes without saying that it can be adapted as well.

[0032]

As described above, according to the present invention, the following effects can be obtained. The first effect is to reduce the flicker noise due to the remaining DC component generated when displaying a television signal (video signal) such as NTSC or PAL on the liquid crystal display panel by the method of the conventional example 2 without using the double speed conversion technology. Can be. The reason is that the polarity of a video signal to be written for each field is managed while flicker noise caused by writing the same signal to two adjacent lines and changing the writing position for each field is maintained. This is because the control is performed so as to narrow the area where this phenomenon occurs and to cancel each other. The second effect is that the digital technology unlike the conventional example 1 is not used,
A liquid crystal display device can be realized without increasing the circuit scale. Further, the third effect is that the same signal is written to two adjacent lines and the writing position is changed for each field, so that the resolution does not deteriorate as compared with the conventional example.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of the liquid crystal module of FIG.

FIG. 3 is a circuit diagram for explaining a timing generation circuit.

FIG. 4 is a timing chart illustrating an operation of a gate line driver of the liquid crystal display device shown in FIG.

FIG. 5 is a timing chart for explaining the operation of the polarity inversion circuit of the liquid crystal display device shown in FIG.

FIG. 6 is a diagram illustrating the polarity of writing to each pixel according to the present invention.

FIG. 7 is a diagram for explaining a write polarity in Conventional Example 2.

FIG. 8 is a drive circuit diagram of a double-speed line-sequential scanning method in the liquid crystal display device of Conventional Example 1.

FIG. 9 is a timing chart for explaining the operation of the double-speed line sequential scanning method of FIG.

FIG. 10 is a configuration diagram of the liquid crystal module of FIG. 8;

11 is a configuration diagram when a horizontal scanning period memory is used as the double speed conversion circuit in FIG. 8;

FIG. 12 is a timing chart for explaining the operation of FIG. 11;

FIG. 13 is a configuration diagram of a liquid crystal display device of Conventional Example 2.

FIG. 14 is a timing chart for explaining the operation of FIG. 13;

FIG. 15 is a diagram illustrating an operation of writing to the liquid crystal display panel of FIG.

[Explanation of symbols]

 Reference Signs List 11 input terminal 12 signal processing circuit 13 polarity inversion circuit 14 X driver 15 Y driver 16 liquid crystal module 17 liquid crystal display panel 18 timing generation circuit 21 shift register 22 level converter 23 sample and hold circuit 24 buffer driver 25 TFT 26 additional capacitance 27 liquid crystal 28 data Line 29 pixel electrode 30 common electrode

Claims (2)

(57) [Claims] 1. An active matrix type liquid crystal display panel having a plurality of liquid crystal elements arranged corresponding to intersections of a plurality of data lines and gate lines, and a scanning line side Y for driving gate lines of the liquid crystal display panel. A driver, an X driver on a signal line side for driving a data line of the liquid crystal display panel, a polarity inversion circuit for converting a video signal into a signal that can drive the liquid crystal display panel without deteriorating image quality, and and a timing generating circuit for generating a timing signal for controlling the polarity inversion circuit and the driver, odd Fi
Fields are 2n-1st and 2nth scanning lines,
The fields are the same for the 2n-th and 2n + 1-th scanning lines, respectively.
When displaying a video signal (n = 0, 1, 2, 3,...
A positive integer including 0, where m is the number of scanning lines of the liquid crystal display panel
, Where 1 ≦ 2n−1,2n, 2n + 1 ≦
2m), the polarity of the video signal applied to each liquid crystal element of the liquid crystal display panel is set to a direction in which the direction in which the polarity of the video signal changes on the field time axis is constant.
The polarity changes every four fields so as not to face
A liquid crystal display device, wherein the polarity inversion circuit is controlled by the timing signal so as to invert the direction . 2. The 2n-1st liquid crystal display panel and the 2nd liquid crystal display panel
n-th, when displaying 2n present eyes 2n + 1 -th same video signal, the time of the on period of the Y driver output waveform of the scanning line, according to claim 1 wherein the first time half of one horizontal scanning period Liquid crystal display device.