JP2001027887A - Method for driving plane display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obscure the boundary lines of divided screens and to embody a good display screen by supplying an image data group for compensation to video bus wiring during a non-writing period in one horizontal scanning period. SOLUTION: The same image data as the image data (block 1) outputted first in the one horizontal scanning period is determined as the image data A for compensation and is added just before the initially outputted image data. When the image data A for compensation is added to the above image data in the manner described above, the video bus wiring is already held charged by the image data A for compensation at the rising of the writing period (W). The image data first sampled in a data line may, therefore, be made to attain the normal voltage. As a result, the degradation in the contrast caused by the failure of the image data in attaining the necessary voltage within the block 1 where the image data is sampled first in the writing period (W) may be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a flat display device, for example, a method for driving an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art A flat display device represented by a liquid crystal display device is utilized in various fields by utilizing its characteristics of light weight, thinness, and low power consumption. In particular, a liquid crystal display device (hereinafter, L
CD) is widely used as a display device for OA equipment and home electric appliances. Among LCDs, an active matrix LCD with a switch element for each pixel
Are rapidly spreading as display devices for OA equipment.

In recent years, in an active matrix type LCD, a p-type switch element for a pixel portion or a peripheral drive circuit has been used.
A device using a -Si (polysilicon) TFT is becoming mainstream. This p-SiTFT-LCD is advantageous for simplifying wiring, downsizing the device, and the like because a driving circuit can be integrated on a glass substrate of a liquid crystal panel.

An FPC is provided between a driving circuit integrated on a glass substrate of a p-Si TFT-LCD and an external driving circuit.
(Flexible wiring board). The analog image data sent from the external drive circuit to the drive circuit of the liquid crystal panel is sampled to a data line through a video bus line and an analog switch. Then, the image data held on the data line is written to the pixel electrode through the TFT.

The transfer speed of image data transferred from an external drive circuit is, for example, SVGA (800 × 60).
0 pixel) 40MHz, XGA (1024 ×
768 pixels) is 65 MHz. With current p-Si TFTs, it is difficult to operate the drive circuit at this speed. Therefore, one screen is divided into a plurality of areas, and the plurality of areas are driven in parallel to reduce the transfer speed. In addition, one screen is divided into a plurality of areas, and one area is further divided into a plurality of blocks (one block is a group of image data for n data lines), and each area is driven one by one in order. In this case, the speed can be further reduced.

Next, a driving method when one area is divided into a plurality of blocks will be described. Here, a case where one area is divided into 32 blocks will be described in order to correspond to an embodiment described later. In the area illustrated here, blocks are driven in the order of 1, 2,... 32.

FIG. 10 shows a conventional p-Si TFT-LCD.
5 is a timing chart showing a driving method when one area is divided into 32 blocks.

First, the relationship between image data (c) supplied to an external drive circuit (not shown) and image data (d) for one block supplied from the external drive circuit to the drive circuit (data line drive circuit) will be described. explain.

However, in FIG. 10, image data (d)
Is an enlarged view of the content of the image data (b). It is assumed that the image data (c) and the image data (d) are in an asynchronous relationship.

The external drive circuit includes, for example, a personal computer (hereinafter referred to as a PC), R249 and R2.
50 ... R256, G249, G250 ... G25
6, B249, B250 ... B256,
Image data (c) corresponding to R, G, and B are transmitted serially. In the external drive circuit, these image data are rearranged, and R249, G249, B249,
The image data is converted into parallel image data (d) such as R250... B256 and supplied to a driving circuit of the liquid crystal panel. Since the rearrangement of the image data will be described in a later embodiment, only the result of the rearrangement is shown here.

Image data (d) shown in FIG. 10 shows the arrangement of image data supplied to the first block (hereinafter, block 1). Each block is collectively supplied with one block of image data rearranged for each block. By sequentially supplying such image data to all blocks in one area, image data is written on one horizontal line in one area.

[0012]

As shown in FIG.
One horizontal scanning period is divided into a writing period (W) and a blanking period (B) which is a non-writing period. The image data (b) is supplied to the video bus wiring in synchronization with the writing period (W) of the horizontal synchronization signal (a). FIG.
Then, in the writing period (W), block 1.
The state in which image data is supplied in order such as block 31 and block 32 is shown. Then, after the blanking period (B), the blocks 1 to 32 are returned again.
Image data is sequentially supplied up to this point. In the blanking period (B), appropriate image data that does not contribute to display is supplied.

A data line or a video bus line to which image data is supplied has a capacitance component and a resistance component. The sizes of these components are not constant due to variations during manufacturing and the like. Therefore, when the time constant on the wiring is large, the image data sampled and held in the data line may not reach a required voltage (this is called a voltage delay). In addition, shift registers included in the driving circuit also have manufacturing variations. For this reason, a required voltage may be sampled and held on one data line, but the required voltage may not be sampled and held on another data line. In particular, when one area is divided into a plurality of blocks and driven one by one in order, near a boundary of the divided areas, that is, in a block where image data is sampled at the beginning of a writing period,
Because the image data sampled and held on the data line hardly reaches the normal voltage due to the voltage delay,
There has been a problem that the contrast is reduced and the boundary line becomes conspicuous.

Further, when such a voltage delay becomes large, image data to be sampled on a certain data line is sampled on an adjacent data line, and a double image, that is, a so-called ghost image is generated. This phenomenon tends to occur particularly in a block where image data is sampled at the end of a writing period.

Further, when halftone display is performed on successive pixels on one horizontal line and black display is performed on the last pixel, a phenomenon occurs in which a part of the line becomes white. Similarly, when halftone display is performed on consecutive pixels on one horizontal line and white display is switched on the last pixel, a phenomenon occurs in which a part of the line becomes black. This phenomenon is considered to occur because crosstalk occurs in the horizontal direction. Such disturbance of the display color causes a decrease in display quality.

A first object of the present invention is to provide a driving method in which one screen is divided into a plurality of areas and driven, whereby boundaries between the divided screens are made inconspicuous, and a good display image can be realized. It is an object of the present invention to provide a method for driving a flat panel display.

A second object of the present invention is to provide a method of driving a flat display device capable of realizing a high-quality display image by eliminating ghosts and horizontal crosstalk in addition to the first object. Is to provide.

[0018]

In order to achieve the above object, the present invention is directed to a plurality of data lines and a plurality of gate lines arranged in a matrix, and a pixel arranged near an intersection of these two lines. A switch element that is turned on / off by an electrode and a gate signal supplied to the gate line and that conducts between the data line and the pixel electrode when on to write image data sampled on the data line to the pixel electrode; A first electrode substrate including a first electrode substrate, a second electrode substrate including a counter electrode disposed at a predetermined distance from the pixel electrode, and a second electrode substrate sandwiched between the first electrode substrate and the second electrode substrate. A light modulation layer, a data line driving circuit that supplies image data for n data lines to a video bus line leading to the data line in synchronization with one horizontal scanning period, and a data line driving circuit in synchronization with one horizontal scanning period, A gate line driving circuit for supplying a gate signal to the gate line, and converting image data input from the outside into an image data group for n data lines, and collectively supplying the image data group to the data line driving circuit In a method of driving a flat panel display device having an external driving circuit, a compensating image data group A having substantially the same voltage as an image data group supplied at the beginning of a writing period in one horizontal scanning period And the compensation image data group A is supplied to the video bus line during the non-writing period in the previous horizontal scanning period. And

According to a second aspect of the present invention, in the first aspect, 1
Compensation image data group B having substantially the same voltage as the image data group supplied at the end of the writing period in the horizontal scanning period
Is added after the last supplied image data group, and the compensation image data group B is supplied to the video bus line during a non-writing period in one horizontal scanning period. I do.

According to a third aspect of the present invention, in the second aspect, a black display image data group is added subsequent to the compensation image data group B, and the compensation image data group is added during a non-writing period in one horizontal scanning period. A black display image data group is supplied to the video bus line following the image data group B.

According to a fourth aspect of the present invention, in the first to third aspects, the compensation image data group A is the same as the image data group supplied at the beginning of the writing period in one horizontal scanning period. And

According to a fifth aspect of the present invention, in the second to fourth aspects, the compensation image data group B is the same as the image data group supplied at the end of a writing period in one horizontal scanning period. I do.

According to a sixth aspect of the present invention, in the first to fifth aspects, the compensation image data group A is added immediately before an image data group supplied at the beginning of a writing period in one horizontal scanning period. And

According to a seventh aspect of the present invention, in the second aspect, the compensation image data group B is added immediately after the image data group supplied at the end of the writing period in one horizontal scanning period. And

According to a eighth aspect of the present invention, in the first to seventh aspects, in the non-writing period in the one horizontal scanning period,
The continuity between the data line and the video bus line is cut off.

According to a ninth aspect of the present invention, in the first aspect, the gate line drive circuit and the data line drive circuit are integrated on the first electrode substrate.

According to a tenth aspect of the present invention, in the ninth aspect,
The data line driving circuit includes the video bus wiring.

According to an eleventh aspect of the present invention, in the ninth or tenth aspect, the data line driving circuit divides the plurality of data lines into at least a first data line group and a second data line group. Image data is sampled in parallel with the data line group, and the image data is sampled in a direction away from the data lines existing at the boundary between the first data line group and the second data line group. And

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method of driving a flat display device according to the present invention will be described with reference to an active matrix p-Si.
An embodiment when applied to a TFT-LCD will be described.

[First Embodiment] FIG. 3 is a block diagram showing the overall configuration of a p-Si TFT-LCD according to the first embodiment. The p-Si TFT-LCD 100 includes a liquid crystal panel 101 in which a driving circuit is built, a driving circuit board 102 that supplies analog image data, vertical / horizontal synchronization signals, and clock signals to the liquid crystal panel 101, and electrically connects these components. And the FPC 106 which is connected to the network.

FIG. 4 is a circuit diagram of the liquid crystal panel 101. The liquid crystal panel 101 includes the active matrix unit 1
And a gate line driving circuit 2 and a data line driving circuit 3 for driving the active matrix section 1. The common circuit (counter electrode drive circuit) 4 is a circuit arranged on the drive circuit board 102 side as shown in FIG. 3, but is shown in FIG. 4 for ease of explanation.

The active matrix section 1 has a plurality of liquid crystal pixels 5 arranged in a matrix. Each liquid crystal pixel 5 includes a pixel electrode 8, a counter electrode 7, and a liquid crystal layer 9 held between these electrodes. The supply of image data to each pixel electrode 8 is controlled by a TFT 6 as a switch element. The gate of each TFT 6 is commonly connected to gate lines G1, G2... Gn for each row, and the drains are data lines D1, D2.
It is connected to the. The source is connected to the pixel electrode 8. Further, the counter electrodes 7 corresponding to all the liquid crystal pixels 5 are commonly connected to the common circuit 4.

The gate line driving circuit 2 is constituted by a circuit including a shift register and a buffer (not shown). The gate line drive circuit 2 is provided with a vertical synchronization signal STV and a vertical clock signal CKV supplied from the drive circuit board 102.
, An address signal is supplied to each of the gate lines G1, G2,... Gn.

The data line driving circuit 3 is turned on / off by a control signal, and when turned on, the data lines D1, D2,.
An analog switch circuit (not shown) for conducting between Dm and the video bus wiring, and a sample and hold circuit (not shown) for outputting a control signal to the analog switch circuit
And a shift register (not shown) for controlling the operation timing of the sample and hold circuit. The data line drive circuit 3 includes a drive circuit board 102
Supplies a horizontal synchronization signal STH, a horizontal clock signal CKH, a polarity inversion signal Vpol, and analog image data. The data line drive circuit 3 is internally divided into four as described later.

The TFT 6, the pixel electrode 8, the gate line driving circuit 2 and the data line driving circuit 3 are integrated on an insulating substrate 14. The shift register and the switch circuit of the gate line driving circuit 2 and the data line driving circuit 3 are p
-SiTFT.

The drive circuit board 102 shown in FIG. 3 includes a control IC 103, a positive D / A converter 11, a negative D / A converter 12, and a common circuit 4. The drive circuit board 102 and the PC main body (not shown) are connected by the FPC 107.

In this example, in order to reduce the power consumption of the D / A converter, two D / As having a small output amplitude are used.
Converters are used for positive and negative polarity. In the data line driving circuit 3, positive image data and negative image data are supplied to the data lines through different paths. Thereby, the video bus lines of the data line driving circuit 3 are always set to the same polarity, and the amplitude of the image data can be reduced by half. Where D
The configuration of the / A converter is not limited to the example of the embodiment, and may be configured using one D / A converter.

FIG. 5 is a circuit diagram of a main part of the drive circuit board 102. The control IC 103 is supplied with digital image data, a reference clock signal, and a composite synchronization signal (synchronization signal including vertical / horizontal) from a PC (not shown). The horizontal direction of the liquid crystal panel 101 (1
The number of pixels in the horizontal line is 1024. R, G, B
Since one pixel is composed of one color, digital image data is supplied as 1024 bit data for each of R, G, and B colors, for a total of 3072 bit data.

The control IC 103 comprises a rearrangement circuit 15, a selection output circuit 16, a control signal generator 17, and an image data control circuit 18.

The rearranging circuit 15 rearranges digital image data supplied from a PC (not shown) into a format suitable for polarity inversion driving. This rearranging circuit 15 includes:
A two-line memory is included.

The selection output circuit 16 sorts and outputs image data to a positive or negative D / A converter according to the polarity of each frame.

The control signal generator 17 generates and outputs a polarity inversion signal (Vpol) and various clock signals based on a reference clock signal and a composite synchronization signal taken from a PC (not shown).

The image data control circuit 18 adds image data for compensation to the image data rearranged by the rearrangement circuit 15 and outputs the result. Specifically, the same image data as the image data output at the beginning of one horizontal scanning period is used as compensation image data, and this is added immediately before the image data output at the beginning of the one horizontal scanning period. ing.

Positive D / A Converter 11 and Negative D
The / A converter 12 parallelizes the digital image data output from the control IC 103,
The data is converted into analog image data and supplied to the video bus wiring of the data line driving circuit 3.

In the liquid crystal panel 101 according to the first embodiment, the display screen is divided into four areas along data lines. Then, 24 image data corresponding to one block are supplied in parallel for each area. The positive D / A converter 11 outputs 12 positive image data to four areas, respectively, for a total of 48 data, and the negative D / A converter 12 outputs negative image to four areas, respectively. Data is 12
And a total of 48 are output.

Inside the positive polarity D / A converter 11,
Forty-eight D / A converters for positive polarity (not shown) are arranged. Further, inside the negative polarity D / A converter 12, 48 D / A converters for negative polarity (not shown) are arranged.

Next, the polarity inversion driving of the liquid crystal panel in the active matrix type LCD will be described.

In a general LCD, in order to prevent the characteristic deterioration of the liquid crystal layer, the pixel / pixel of the liquid crystal panel is set every frame.
The polarity of the potential difference applied between the opposing electrodes is inverted.
Such a polarity inversion driving method includes, for example, a V (vertical) line inversion driving method in which the polarity of a potential difference applied between a pixel and a counter electrode is inverted for each adjacent vertical pixel line (for each column), or for an adjacent pixel. An H / V (horizontal / vertical) line inversion driving method for inverting the polarity of a potential difference applied between a pixel and a counter electrode every time is known.

In order to drive the liquid crystal, a voltage of about ± 5 V is usually required. Therefore, in order to implement the above inversion driving method, a withstand voltage of 10 V is required as an output of the driving circuit, and it has been difficult to reduce power consumption. Therefore, a liquid crystal display device for reducing power consumption has been proposed.

For example, Japanese Patent Application No. Hei 9-186151 discloses that a plurality of D signals for converting serial digital image data input from the outside into serial signals and then converting them into analog signals.
/ A conversion circuits, and amplifiers connected to the respective D / A conversion circuits. The amplifiers connected to the adjacent D / A conversion circuits are connected to power supply voltages of opposite polarities, and one pair is connected to each amplifier. A display device is disclosed in which the switch pairs are connected to each other, and the switches constituting the switch pairs are connected to data data lines, respectively. According to this configuration,
Since the driving circuits can be operated with the same polarity withstand voltage, power consumption can be reduced. Further, since the display signal bus can be shared by adjacent data lines, the number of display signal buses can be reduced, and the circuit scale can be reduced.

In the display device disclosed in Japanese Patent Application No. Hei 9-186151, in a certain frame period, the odd-numbered D / A conversion circuit drives the odd-numbered data lines, and the even-numbered D / A. The conversion circuit drives the even-numbered data lines. Then, in the next frame period, the odd-numbered D / A conversion circuits drive the even-numbered data lines,
The even-numbered D / A conversion circuits drive odd-numbered data lines. In order to enable such a polarity inversion drive, the image data is rearranged in accordance with the frame by a memory arranged beforehand outside.

In the method of driving the liquid crystal panel 101 described below, the polarity inversion drive is performed similarly to the display device of Japanese Patent Application No. 9-186151, and the image data is rearranged.

Next, a basic driving method of the liquid crystal panel 101 will be described.

FIG. 6 is a wiring diagram for explaining a method of driving the liquid crystal panel 101, and mainly shows the relationship between data lines and video bus lines connected thereto.

In the liquid crystal panel 101, the display screen constituted by the active matrix section 1 is divided into four along data lines. L1, L2, R1, and R2 in FIG. 6 indicate respective divided areas. The image data supplied to each area is simultaneously scanned in the direction of the arrow, centering on the left and right two lines (line L and line R) among the three lines dividing the screen into four. This is to eliminate discontinuities at the boundaries of the divided areas.

In order to perform such scanning, the data line driving circuit 3 (FIG. 3) is internally divided into four parts. That is, a circuit group such as a shift register and a sample-and-hold circuit constituting the data line driving circuit 3 is provided for each area.

As described above, when one screen is driven in parallel with four areas, the sampling time in the shift register is four times longer than in the case where one screen is driven by one shift register. It is possible to do.
Therefore, a good display image can be realized.

To each of the channels CN-L and CN-R, 48 pieces of analog image data are input from the drive circuit board 102 (FIG. 3). That is, channel C
In NL, 48 pieces (24 pieces) supplied to the areas L1 and L2 are provided.
Book × 2) image data is input, and the channel CN-R
Are supplied to the areas R1 and R2.
2) The image data is input.

The image data input to the liquid crystal panel 101 is output to an analog switch circuit (not shown) through 24 video bus lines (for example, L1P1, L1N1,..., L1N12) wired for each area.

In the video bus wiring, lines to which positive-polarity image data is supplied and lines to which negative-polarity image data are supplied are alternately arranged. In the video bus wiring shown in FIG. 6, "P" is attached to a line with a positive polarity, and "N" is attached to a line with a negative polarity. For example, the video bus line L1P1 indicates a positive line, and L1N1 indicates a negative line.

FIG. 7 is a partially enlarged view of the area L1 shown in FIG. The inside of one area is further divided into 32 blocks. And in one block, R,
Eight data lines corresponding to each of the colors G and B are distributed. For example, block 1 contains R249
..R256, G249 ... G256, B249
・ B256 is sorted. Block 31
R9 ... R16, G9 ... G16, B9 ...
B16 includes R1... R8, G1.
G8, B1,..., B8 are distributed respectively.

As described above, in each block, eight data lines corresponding to each of the colors R, G, and B are distributed. Therefore, image data for 24 data lines is simultaneously sampled in a total of one block. The image data sampled on these 24 data lines constitutes 8 pixels on the screen. Further, as shown in FIG. 7, by sequentially sampling 32 blocks with one block as one unit, image data for one horizontal line is written to the pixel.

For example, from block 1 to block 3 in FIG.
By performing sampling in the order of 2, image data is sequentially sampled from B256 to R1 in the area L1 in FIG. Similar sampling is performed in other areas. Thus, in one area, 76
Sampling is performed on eight (24 × 32) data lines. Then, in a total of four areas, sampling for 3072 data lines is achieved in one horizontal scanning period. The image data sampled by the 3072 data lines forms 1024 pixels in one horizontal line on the screen. By repeating such sampling of image data by the number of gate lines, 1
Image data for a frame is sequentially written to each pixel.

The liquid crystal panel 101 of the first embodiment uses the V-line inversion driving method. That is, during each frame period, the data line driving circuit 3 samples the image data so that the potentials of the adjacent data lines have opposite polarities to each other with respect to the reference voltage, and the potential of each data line is set to the frame period. , The polarity is inverted.

FIG. 8 is a partial circuit diagram of the data line driving circuit 3, and shows a circuit configuration of a portion corresponding to the area L1 in FIG. That is, FIG. 8 shows one circuit configuration of the data line driving circuit 3 divided into four. The common components in FIG. 8 will be described on behalf of one of them.

The data line driving circuit 3 includes a shift register 1
11, a sample and hold circuit 112 for controlling conduction of an analog switch circuit 113 based on a control signal Q from the shift register 111, and an analog switch circuit 113. The data line drive circuit 3 is configured to sample the analog image data supplied from the drive circuit board 102 (FIG. 3) to each data line in synchronization with the horizontal clock signal CKH.

The control signal Q of the shift register 111 is input to the odd-numbered signal switching circuit 112a and the even-numbered signal switching circuit 112b. Video bus wiring 12
5, a positive analog signal is input, and the video bus line 126 receives a negative analog signal.

The analog switch circuit 113 includes a pair of P
ch transistor 114 and Nch transistor 116
And a pair of Pch transistor 115 and Nch transistor 117. The video bus line 125 of positive polarity is connected to the data lines Dm-n and Dm- (n-1) via Pch transistors 114 and 115. On the other hand, the negative video bus line 126
Data line Dm- via the transistors 116 and 117
n, Dm- (n-1).

The gate of the Pch transistor 114 is
The output terminal of the R gate 118 is connected, and the gate of the Nch transistor 116 is connected to the output terminal of the AND gate 119. Also, the gate of the Pch transistor 115 is connected to the output terminal of the NAND gate 120, and Nc
The gate of the h transistor 117 is connected to the output terminal of the NOR gate 121.

The OR gate 118, the AND gate 119,
The polarity inversion signal Vpol is input to the NAND gate 120 and the NOR gate 121. Also, AND gate 1
19 and the NAND gate 120 have the shift register 11
The control signal Q from 1 is input. The control signal Q from the shift register 111 is input to the OR gate 118 via the inverter 122. The control signal Q from the shift register 111 is input to the NOR gate 121 via the inverter 123. Shift register 111
Are configured to sequentially shift the horizontal synchronization signal STH in synchronization with the horizontal clock signal CKH. The control signal Q from the shift register 111 is a horizontal synchronization signal STH.
Is output based on

Next, the operation of the circuit shown in FIG. 8 will be described. Here, the operation of a pair of adjacent data lines Dm-n and Dm- (n-1) and the operation of the analog switch circuit 113 and the signal switching circuits 112a and 112b connected thereto will be described. Also, the signal switching circuit 112
a, 112b supplied to the polarity inversion signal Lo
The w level indicates a positive polarity, and the High level indicates a negative polarity. Further, it is assumed that the polarity inversion signal Vpol is switched every frame.

In the writing period (W) of one horizontal scanning period, the following operation is performed. When the polarity inversion signal Vpol is at a low level, the OR gate 118
, And the output of the AND gate 119 becomes Low level. Also, NAND
The output of the gate 120 is at a high level, and the NOR gate 121 is in a state of inverting and passing the control signal Q. Therefore, Pch transistor 114 is turned on by control signal Q from shift register 111, and Nch transistor 116 and Pch transistor 115 are turned off. Further, the Nch transistor 117 is turned on by the control signal Q from the shift register 111. As a result, positive polarity image data is sampled on the data line Dm-n based on the control signal Q from the shift register 111. On the other hand, negative image data is sampled on the data line Dm- (n-1) based on the control signal Q from the shift register 111.

When the polarity inversion signal Vpol is at a high level, the OR gate 118 is at a high level, and
D gate 119 is set to pass control signal Q.
Further, the NAND gate 120 is in a state where the control signal Q is inverted and passed therethrough, and the output of the NOR gate 121 is Lo.
It becomes w level. Therefore, the Pch transistor 11
4 is turned off, and the Nch transistor 116 is turned on by the control signal Q from the shift register 111. Further, the Pch transistor 115 is turned on by the control signal Q from the shift register 111,
Nch transistor 117 is turned off. As a result, negative image data is sampled on the data line Dm-n based on the control signal Q from the shift register 111. On the other hand, positive polarity image data is sampled on the data line Dm- (n-1) based on the control signal Q from the shift register 111.

Blanking period (B) of one horizontal scanning period
In this case, since the control signal Q is not output from the shift register 111, all the transistors included in the analog switch circuit 113 are turned off. Accordingly, the image data for compensation supplied to the video bus lines 125 and 126 during this time is charged on the video bus lines 125 and 126.

The above operation is repeated for each frame, so that adjacent data lines Dm-n and Dm- (n-
In 1), the positive image data and the negative image data are alternately sampled. For other data lines,
Positive image data and negative image data are alternately sampled on adjacent data lines.

In the circuit configuration shown in FIG. 8, only the video data of the positive polarity is supplied to the video bus wiring 125,
The video bus line 126 is supplied with only negative image data. According to this, the sample and hold circuit 112
Since each of the gate elements can be operated with a unipolar breakdown voltage, power consumption can be reduced.

FIG. 9 shows the control IC 103 (FIG. 4).
FIG. 4 is an explanatory diagram showing a data array of image data rearranged in FIG. On the right side of the figure, the image data for one horizontal line supplied from the PC main body is stored in areas L1, L2, R1, R2.
3 shows a data sequence in the case of rearranging every 1 to 32 blocks. Also, the left side of the figure shows the polarity (P
ol) and the rule of distribution to each video bus wiring at that time. Pol = 0 (Low level) is used when the polarity inversion signal has a positive polarity, and Pol = 1 (H level).
(high level) indicates distribution when the polarity inversion signal has a negative polarity.

Next, data distribution will be described with reference to the block 1 in the area L1 as an example.

When the polarity inversion signal is Pol = 0, "R249" is applied to the video bus line L1P1 of the block 1.
However, “G249” is supplied to L1N1.
The image data “R249” passes through the Pch transistor 114 in FIG. 8 and is sampled on the data line Dm-n, and the image data “G249” passes through the Nch transistor 117 in FIG. 8 and the data line Dm- ( n-1). On the other hand, when the polarity inversion signal is Pol = 1, “G249” is supplied to the video bus wiring L1P1 of block 1 and “R249” is supplied to L1N1. The image data of “G249” is Pc in FIG.
The data line Dm- (n-
The image data of “R249” is sampled to the data line Dm-n through the Nch transistor 116 in FIG. 8. By rearranging the data as shown in FIG. 9, only the positive image data is always supplied to the video bus wiring 125 in FIG.
Only the video data of the negative polarity is always supplied to the video bus line 126. That is, adjacent data lines Dm-n,
In Dm- (n-1), the polarity of image data is inverted for each frame, but image data of the same polarity is always supplied to each video bus line.

Next, in the first embodiment, the liquid crystal panel 1
The image data supplied to the video bus line 01 will be described.

FIG. 1 shows the p-SiTFT-L of the first embodiment.
6 is a timing chart showing a driving method when one area is divided into 32 blocks in a CD. The timing chart of FIG. 1 corresponds to the timing chart of FIG.

Analog image data is transferred from the drive circuit board 102 to the data line drive circuit 3 of the liquid crystal panel 101 at a timing synchronized with the rise of the horizontal synchronization signal (a). The image data includes the rearranged digital image data and the image data A for compensation. That is, the same image data as the image data (block 1) output first at the time of one horizontal scanning period is used as compensation image data A, which is added immediately before the image data output first. Although not shown in FIG. 1, in the other periods of the blanking period (B), appropriate image data not related to display is supplied.

As shown in FIG. 1, when the same compensation image data A is added immediately before the image data output at the beginning of one horizontal scanning period, the writing period (W)
At the time of the rise, the video bus wiring has already been charged with the image data for compensation. For this reason, the image data sampled first on the data line can reach the normal voltage. Thereby, in the block 1 where the image data is sampled at the beginning of the writing period (W), it is possible to prevent a decrease in contrast caused by the image data not reaching the required voltage.

Therefore, according to the driving method of the first embodiment, in the block where the image data is sampled at the beginning of the writing period (W), the boundaries of the divided screens are made less noticeable, and a good display image is realized. can do.

In the first embodiment, the same image data as the first output image data (block 1) is used as the image data A for compensation. However, the image data A for compensation only needs to be image data having substantially the same voltage as the image data output first, and need not necessarily be the same image data as the image data output first.

The image data A for compensation only needs to be added within the blanking period (B) of the previous horizontal scanning period, and the block where the image data is sampled at the beginning of the writing period (W) is not necessarily required. It does not have to be immediately before.

Further, the output period of the image data in the blanking period may be longer or shorter than the period corresponding to one block within the blanking period. However, in order to sufficiently charge the video bus wiring with the image data for compensation, it is desirable to set the period more than the period corresponding to one block.

[Second Embodiment] Next, a second embodiment will be described. P-SiTFT-L according to the second embodiment
Since the configuration of the CD is almost the same as that of the first embodiment, only the differences will be described. The same parts as those in the first embodiment will be described with the same reference numerals.

The image data control circuit 18 according to the second embodiment
Two image data for compensation and image data for black display are added to the image data rearranged by the rearrangement circuit 15 and output. Specifically, the same image data as the image data output first in one horizontal scanning period is used as compensation image data A, which is added immediately before the image data output first. Further, the same image data as the image data output at the end of one horizontal scanning period is used as compensation image data B, which is added immediately after the image data output last. Further, following the image data B for compensation, image data for black display is added.

Next, in the second embodiment, the liquid crystal panel 1
The image data supplied to the video bus line 01 will be described.

FIG. 2 shows the p-SiTFT-L of the second embodiment.
6 is a timing chart showing a driving method when one area is divided into 32 blocks in a CD. The timing chart of FIG. 2 corresponds to the timing charts of FIG. 1 and FIG.

Analog image data is transferred from the drive circuit board 102 to the data line drive circuit 3 of the liquid crystal panel 101 at a timing synchronized with the rise of the horizontal synchronization signal (a). The image data includes the rearranged digital image data, the image data A and B for compensation, and the image data for black display.

The compensating image data A is the same as the image data (block 1) output at the beginning of one horizontal scanning period, and the compensating image data B is at the end of one horizontal scanning period. Output image data (block 32)
Are the same image data. Then, the image data for black display is added for one block following the image data B for compensation. In other periods of the blanking period (B), appropriate image data not involved in display is supplied.

As shown in FIG. 2, when the same image data A for compensation is added immediately before the image data output at the beginning of one horizontal scanning period, the data lines are sampled first. Image data can reach a regular voltage. Thereby, in the block 1 where the image data is sampled at the beginning of the writing period (W), it is possible to prevent a decrease in contrast caused by the image data not reaching the required voltage. If the same image data B for compensation is added immediately after the image data output at the end of one horizontal scanning period, the block 32 where the image data is sampled at the end of the writing period (W). In this case, the occurrence of ghost due to the voltage delay can be suppressed. Further, following the image data B for compensation, the image data for black display is set to 1
By adding the blocks, the crosstalk in the horizontal direction can be suppressed. Therefore, even when halftone display is performed on consecutive pixels on one horizontal line and display is switched to white or black display at the last pixel, a part of the line does not become black or white. In addition, disturbance of display colors can be prevented.

Therefore, according to the driving method of the second embodiment, in the block where the image data is sampled at the beginning of the writing period (W), the boundaries between the divided screens are made inconspicuous, and a good display image is realized. can do. Further, it is possible to suppress occurrence of ghost in a block where image data is sampled at the end of the writing period (W). Furthermore, even when halftone display is performed on consecutive pixels on one horizontal line and display is switched to white or black display at the last pixel, high-quality display images are eliminated without horizontal crosstalk. Can be realized.

In the second embodiment, in order to eliminate horizontal crosstalk, it is sufficient to add at least one block of image data for black display. If necessary, image data for black display may be added for two or more blocks.

In the second embodiment, the same image data as the first output image data (block 1) is used as compensation image data A, as in the first embodiment. However, the image data for compensation only needs to be image data having substantially the same voltage as the image data output first, and need not necessarily be the same image data as the image data output first.

Further, the same compensating image data A is added immediately before the image data output at the beginning of one horizontal scanning period, and immediately after the image data output at the end of one horizontal scanning period. Alternatively, the same compensation image data B may be simply added. Also in this case, it is possible to make the boundary of the divided screen less noticeable, and to suppress the occurrence of ghost in the block where the image data is sampled at the end of the writing period (W). In the first and second embodiments, the columns using the V line inversion driving method have been described. However, a so-called H / V line inversion driving method in which the polarity of image data supplied to the data lines is further inverted for each row may be used. it can.

[0099]

As described above, in the driving method of the flat panel display according to the present invention, immediately before the image data output at the beginning of one horizontal scanning period, the same voltage for compensating for almost the same voltage as this is output. The image data A is added, and the image data A for compensation is supplied to the video bus wiring during the non-writing period in the previous horizontal scanning period. Is charged by the image data A. Therefore, in the block where the image data is sampled at the beginning of the writing period, the image data sampled and held on the data line can reach the normal voltage. Therefore, a decrease in contrast in this block is prevented, and the boundaries between the divided screens are less noticeable, so that a good display image can be realized.

Further, the above-described compensation image data A is added, and immediately after the image data output at the end of one horizontal scanning period, compensation image data B having substantially the same voltage as this is added. If the image data B for compensation is supplied to the video bus wiring during the non-writing period in the horizontal scanning period, the image data for compensation A
In addition to the effect described above, the occurrence of ghost in the block where the image data is sampled at the end of the writing period can be suppressed, so that a better display image can be realized.

Further, the compensation image data A and B
Is added, and image data for black display is added following the image data B for compensation. During the non-writing period in the previous horizontal scanning period, the image data A and B for compensation are added.
When the image data for black display is supplied to the video bus wiring, in addition to the effects of the image data for compensation A and B, halftone display is performed on continuous pixels on one horizontal line, Even in the case where the display is switched to white or black at the last pixel, a high-quality display image can be realized without horizontal crosstalk.

[Brief description of the drawings]

FIG. 1 is a timing chart illustrating a driving method according to a first embodiment.

FIG. 2 is a timing chart illustrating a driving method according to a second embodiment.

FIG. 3 is a block diagram showing the overall configuration of a liquid crystal display device.

FIG. 4 is a circuit configuration diagram of a liquid crystal panel.

FIG. 5 is a circuit configuration diagram of a drive circuit board.

FIG. 6 is a wiring diagram illustrating a method for driving a liquid crystal panel.

7 is a partially enlarged view of an area L1 shown in FIG.

FIG. 8 is a partial circuit diagram of a data line driving circuit.

FIG. 9 is an explanatory diagram showing a data array of image data rearranged by the control IC.

FIG. 10 is a timing chart of a conventional example showing a relationship between image data supplied to a video bus line and a horizontal synchronization signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Active matrix part, 2 ... Gate line drive circuit 3 ... Data line drive circuit, 4 ... Common circuit, 15 ... Rearrangement circuit 16 ... Selection output circuit, 17 ... Control signal generation part, 18 ... Image data control circuit 100 ... Liquid crystal display device, 101 ... Liquid crystal panel, 102 ...
Drive circuit board 103: control IC, 110: shift register 111: sample / hold circuit

Continued on the front page F term (reference) 2H093 NA16 NA22 NA33 NA80 NC13 NC22 NC24 NC26 NC34 NC68 ND05 ND43 ND48 ND58 NE07 5C006 AA01 AA22 AC28 AF44 AF46 AF73 AF82 BB14 BB16 BC12 BC16 BF03 BF05 BF11 FA20 FA22 5C06 A03 DD11 JJ03 JJ05 JJ06

Claims (11)

[Claims] 1. A plurality of data lines and a plurality of gate lines arranged in a matrix, a pixel electrode arranged near an intersection of these two lines, and on / off control by a gate signal supplied to the gate line, A first electrode substrate including a switch element for writing the image data sampled to the data line to the pixel electrode by conducting between the data line and the pixel electrode when turned on, and disposed opposite to the pixel electrode at a predetermined interval; A second electrode substrate including the separated counter electrode, a light modulation layer sandwiched between the first electrode substrate and the second electrode substrate, and a data line connected to the data line in synchronization with one horizontal scanning period. A data line driving circuit for supplying image data for n data lines to a video bus line extending therethrough; a gate line driving circuit for supplying a gate signal to the gate line in synchronization with one horizontal scanning period; The image data input from the unit is converted into an image data group for n data lines, and the image data group is collectively supplied to the data line driving circuit. A compensating image data group A having substantially the same voltage as the image data group supplied at the beginning of the writing period in one horizontal scanning period.
Is added after the image data group supplied at the end of the writing period in the previous horizontal scanning period, and the compensation image data group A is supplied to the video bus wiring during the non-writing period in the previous horizontal scanning period. A method for driving a flat panel display device, comprising: 2. A compensating image data group B having substantially the same voltage as an image data group supplied at the end of a writing period in one horizontal scanning period is added subsequent to the last supplied image data group. 2. The method according to claim 1, wherein the compensation image data group B is supplied to the video bus line during a non-writing period in a horizontal scanning period. 3. A black display image data group is added subsequent to the compensation image data group B. During a non-writing period in one horizontal scanning period, a black display image data group is added following the compensation image data group B. 3. The method according to claim 2, wherein a group of image data is supplied to the video bus wiring. 4. The flat display apparatus according to claim 1, wherein the compensation image data group A is the same as an image data group supplied at the beginning of a writing period in one horizontal scanning period. Drive method. 5. The flat display device according to claim 2, wherein the compensation image data group B is the same as an image data group supplied at the end of a writing period in one horizontal scanning period. Drive method. 6. The flat display device according to claim 1, wherein the compensation image data group A is added immediately before an image data group supplied at the beginning of a writing period in one horizontal scanning period. Drive method. 7. The flat display device according to claim 2, wherein the compensation image data group B is added immediately after an image data group supplied at the end of a writing period in one horizontal scanning period. Drive method. 8. The method according to claim 1, wherein conduction between the data line and the video bus line is cut off during a non-writing period in the one horizontal scanning period. 9. The method according to claim 1, wherein the gate line driving circuit and the data line driving circuit are integrated on the first electrode substrate. 10. The method according to claim 9, wherein the data line driving circuit includes the video bus wiring. 11. The data line driving circuit divides the plurality of data lines into at least a first data line group and a second data line group, and samples image data in parallel for each data line group. 11. The flat display device according to claim 9, wherein image data is sampled in a direction away from a data line existing at a boundary between the first data line group and the second data line group. Drive method.