JPH09106265A - Voltage output circuit and picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the reducing of cost by reducing number of multilevel power source lines and also simplifying the constitution of a driving circuit without impairing display diginity in a picture display device using a digital signal as an input video signal. SOLUTION: The digital signal having n bits is sampled by a sampling circuit 12. K bits of the sampled signal are converted into 2<k> pieces of decoded signals in the decoder 14 of one side and remaining II bits are converted into 2<m> pieces of decoded signals in the decoder 14 of other side. In a selection circuit 16, a signal for selecting one period of the period obtained by equally dividing one horizontal scanning period by 2<k> based on k pieces of timing signals by using 2<k> pieces of decoded signals. In a logic circuit 17, 2<m> pieces of signals are generated with the combination of this outputted signal and the 2m pieces of decoded signals. Then, one line is selected from 2<m> lines of multilevel power source lines PL by using the outputted signals by an output switch 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage output circuit for selecting, capturing and outputting a voltage of a power supply line based on a digital input signal, and more specifically, it is possible to reduce the number of power supply lines. The present invention relates to a voltage output circuit and an image display device using the voltage output circuit as a data signal line driving circuit.

[0002]

2. Description of the Related Art Conventionally, various driving methods have been proposed or put into practical use for image display devices such as liquid crystal display devices. Among them, the active matrix driving method is suitable for graphics display and is being actively researched and developed.

As shown in FIG. 32, an active matrix driving type liquid crystal display device includes a pixel array 101, a data signal line driving circuit 102, and a scanning signal line driving circuit 10.
3 is provided. The pixel array 101 includes a large number of data signal lines SL ... And a large number of scanning signal lines GL ...
And Two adjacent data signal lines SL / S
One pixel 104 is provided in the portion surrounded by the two scanning signal lines GL and GL adjacent to L, and the pixels 104 ... Are arranged in a matrix over the entire pixel array 101. There is.

The data signal line drive circuit 102 samples the input video signal DAT in synchronization with a timing signal such as a clock signal CKS, amplifies it as necessary, and writes it in each data signal line SL. Has become.
The scanning signal line driving circuit 103 sequentially selects the scanning signal lines GL in synchronization with a timing signal such as a clock signal CKG and controls the opening / closing of a switching element (for example, thin film transistor) (not shown) in the pixel 104. Has become. As a result, the video signal (data) written in each data signal line SL is written in each pixel 104 ... And the written data is held.

By the way, in the conventional active matrix type liquid crystal display device, the above-mentioned switching element, that is, the pixel transistor is generally formed by an amorphous silicon thin film formed on a transparent substrate. Further, the circuits such as the data signal line drive circuit 102 and the scanning signal line drive circuit 103 have been configured by external ICs.

On the other hand, in recent years, due to demands such as improvement in driving force of pixel transistors accompanying reduction in screen size, reduction in mounting cost of driving ICs, reliability in mounting, etc., a monolithic pixel is formed using a polycrystalline silicon thin film. A technique for forming the array 101 and the driving circuits 102 and 103 has been reported. Also, aiming for a larger screen and lower cost,
At process temperatures below the glass strain point (about 600 ° C),
Attempts have also been made to form the device with a polycrystalline silicon thin film on a glass substrate.

A method of writing video data in the data signal line SL in the above liquid crystal display device will be described below. There are an analog method and a digital method as a driving method of the data signal line SL, but here, only the digital method will be described.

In the conventional digital data signal line drive circuit, as shown in FIG.
Is input, the sampling pulse is output from the scanning circuit 105 in time series. The video data DAT is sampled by the sampling circuit 106 in synchronization with the sampling pulse.

The sampled n-bit digital signal is held in the latch 107 and then transferred in synchronization with the transfer signal TF in the next horizontal scanning period, and the decoder 1
It is decoded by 08 and controls the opening and closing of the output switch 109. By turning on the output switch 109, 2
^{One of the n} gradation power supply lines is selected, and the gradation power supply line is connected to the data signal line SL.

Although the above-mentioned data signal line driving circuit can display an image of 2 ⁿ gradations, it requires the same number of gradation power supply lines as the number of gradations. Has a limit, and is usually used with 8 gradations or 16 gradations or less.

In the data signal line drive circuit shown in FIG. 34,
The digital signal sampled by the sampling circuit 106 is divided into m bits and h bits. The respective signals are latch 110, 110 and decoder 111.
Via 111, it is converted into 2 ^m decoded signals and 2 ^h decoded signals. 2 ^m decoded signals are 2 ^m +
It is given to the output switch 109 to select two from one gradation power supply line. The 2 ^h decoded signals are supplied to an intermediate value generator 112 that generates an intermediate value of the two voltages output from the output switch 109.

The intermediate value generator 112 is a circuit in which a large number of resistance elements are connected in series between adjacent grayscale power supply lines to generate an intermediate potential by resistance division. For example, the SID 94 DIGEST
Proposed on p.351-354. Further, in the above data signal line drive circuit, the output switch 109 selects two gradation power supply lines for the intermediate value generator 112, so that the number of gradation power supply lines is about 1/8 of the number of gradations ( It is reduced to 9 lines for 64 gradation display).

As another structure for reducing the number of gradation power supply lines, there is a digital driver using an oscillating voltage as shown in FIG. As proposed in SID 93 DIGEST p.11 to 14, this uses a signal oscillating between two voltages V _CC and V _SS and displays a halftone according to its duty ratio. . In the example of FIG. 35, the voltages V _{1 to} V ₈ for 8 gradations are output by the two voltages V _CC and V _SS, but if this method is expanded, it is similar to the data signal line drive circuit shown in FIG. 34. In addition, it is possible to display 64 gradations with 9 power supplies.

Further, as another method, as shown in FIG. 36, a stepwise ramp waveform V changing from a low level to a high level is inputted to one power supply line, so that the timing corresponding to the display data is obtained. (Basic signals for gradation F _{1 to} F
There is a driving method in which the voltage of the power supply line is taken in ( _n ) (see Japanese Patent Publication No. 7-50389). According to this method, theoretically, it is possible to display an image having any number of gradations with only one power line.

[0015]

By the way, an element (transistor, formed of the above-mentioned polycrystalline silicon thin film) is used.
In the case of forming a resistor or the like), the grain size of the silicon crystal increases, so that the grain size and the size of the element are almost the same.
Therefore, the element formed of the polycrystalline silicon thin film has a problem that variations in characteristics cannot be avoided as compared with the element formed on the single crystal silicon substrate.

By using such an element, the intermediate value generator 1
If it is attempted to configure twelve divided resistors, the resistance values of the resistors vary. Therefore, it becomes difficult for the data signal line drive circuit including the intermediate value generator 112 to obtain a highly accurate intermediate value, and there is a limit to the increase in the number of gradations. For example, in the data signal line drive circuit of FIG. 34, when the increase in the number of gradations due to the dividing resistance is practically up to 4 times,
If there are nine gradation voltages, the maximum number of gradations that can be displayed by combining these is 32 gradations, which is not suitable for high gradation display.

When a polycrystalline silicon thin film transistor is used as a pixel transistor, the polycrystalline silicon thin film transistor has a driving force (carrier mobility) several tens to several hundreds of times that of an amorphous silicon thin film transistor.
Therefore, when the bus line (data signal line) and the pixel transistor are regarded as a low pass filter, the cutoff frequency of the low pass filter becomes high. Therefore, if an attempt is made to perform halftone display using the above-described vibration signal using such an element, the integration of the vibration signal may become insufficient, and good gradation display may not be possible.

Further, in the driving method using only one power supply line to which the ramp waveform is applied, the number of power supply lines is only one, but the time given for taking in the gradation signal is the horizontal scanning period. The number of gradations is reduced to one. Therefore, in reality, the number of display gradations is limited due to the constraint from the time constant (especially load capacitance) of the data signal line.

The present invention has been made in order to solve the problems of the prior art, and in a digital data signal line drive circuit, the number of gradation power supply lines is suppressed while suppressing deterioration of halftone display performance. And to provide an image display device using this data signal line drive circuit.

[0020]

In order to solve the above-mentioned problems, the first voltage output circuit of the present invention applies a different voltage to each divided period in the scanning period divided into a plurality of periods. By applying a plurality of power supply lines and one of the power supply lines based on a digital signal of a plurality of bits in at least one of the divided periods, application to the power supply line selected in the selected period And a selective output means for outputting the generated voltage.

In the above structure, when a digital signal of a plurality of bits is input, the selection output means selects one power supply line in one or more divided periods based on the digital signal. As a result, the voltage output to the selected power supply line during that period is output.

Therefore, when this voltage output circuit is applied to the data signal line drive circuit of the image display device, the number of power supply lines can be reduced as compared with the gradation of the image to be displayed. As a result, the structure of the external power supply circuit can be simplified, and the number of external terminals for connecting the power supply line can be significantly reduced. In addition, since the divided period is sufficiently long, which is a fraction of the scanning time, a precise gradation voltage can be output when the scanning period is the horizontal scanning period.

Specifically, the first voltage output circuit is
The power supply line is 2 for the digital signal of n bits.
^m (1 <m <n) are provided, and the selection output means is 2
a period selection means for selecting on the basis of at least one period of the divided said divided period ^k to 2 ^k-number of signal generated by k bits of said digital signal (k = n-m),
Based on the output signal of the period selecting means and the 2 ^m signals generated by the m bits of the digital signal, a signal that is valid only during the period selected by the period selecting means of one of the power supply lines is selected. It has an output control means for outputting, and an output means for conducting a signal by the output control means and outputting a voltage applied to the selected power supply line.

In the above configuration, when an n-bit digital signal is input, 2 ^k signals and 2 ^m signals are created by the k bits and m bits, respectively. Then, the period selecting means selects at least one period of the divided periods using the 2 ^k signals. On the other hand, by the output control means, for example, the output signal of the period selection means and 2 ^m
A logical product is obtained with the individual signals, and a signal that is valid only during the period selected by the period selecting means on one of the power supply lines is output. And from the output means,
When the output means is made conductive based on this signal, the voltage of the selected period is output from the selected one power supply line.

As a result, the ^number of power supply lines required to display an image of 2 ⁿ gradation is 2 ^m, which is greatly reduced. For example, when displaying an image of 64 gradations, if m = 3, the number of power supply lines is eight.

Further, since the output means has 2 ^m transfer gates respectively connected to the power supply lines, only one transfer gate is required to take in the voltage from the power supply lines. . Therefore, the conduction characteristic from the power supply line to the output has a low resistance, and the voltage drop can be suppressed.

Further, a counter for generating k pulse signals having different periods is provided, and the period selecting means outputs 2 ^k signals which are effective in each divided period based on the pulse signal from the counter. As a result, the counter outputs k pulse signals based on the clock, so that it is not necessary to input k pulse signals from the outside, and the number of input signal lines can be reduced.

In the first voltage output circuit, since the ranges of the voltages applied to the power supply lines do not overlap between the power supply lines during the scanning period, the level change amount of the voltage of each power supply line is reduced. Get smaller. Therefore, the time required for the voltage level to stabilize becomes shorter and the scale of the external power supply circuit for applying the voltage to the power supply line can be reduced. In addition, the external power supply circuits that supply voltages that are close to each other can be the same, and it is difficult for the inversion of gray scales due to the output variations of the external power supply circuits to occur.

In order to solve the above problems, the second voltage output circuit of the present invention has a plurality of power supply lines to which different voltages are applied in each divided period in the scanning period divided into a plurality of periods. By selecting any two of the power supply lines in at least one of the divided periods based on a digital signal of a plurality of bits, the voltage applied to the power supply line selected in the period is output. It is characterized in that it is provided with a selection output means and an intermediate value generation means for generating a voltage between the two voltages selected by the selection output means.

In the above structure, when a digital signal of a plurality of bits is input, the selection output means selects two power supply lines in one or more divided periods based on the digital signal. As a result, the two voltages output to the selected power supply line during that period are output. Then, the intermediate value generating means generates a voltage between the two voltages by using resistance division or the like.

Therefore, when this voltage output circuit is applied to the data signal line drive circuit of the image display device, the number of power supply lines can be reduced as compared with the gradation of the image to be displayed. As a result, the structure of the external power supply circuit can be simplified, and the number of external terminals for connecting the power supply line can be significantly reduced. In addition, since the divided period is sufficiently long, which is a fraction of the scanning time, a precise gradation voltage can be output when the scanning period is the horizontal scanning period. Further, since the voltage between the two voltages is output by the intermediate value generating means, it is possible to output voltages of different levels and increase the number of gradations.

Specifically, the second voltage output circuit is
The power supply line is 2 for the digital signal of n bits.
^{There are provided m} + 1 (1 <m <n) lines, and the selection output means performs at least one period of the divided period divided into 2 ^k by k bits (1 <k <n−m) of the digital signal.
Of the power supply lines based on the period selecting means for selecting based on the 2 ^k signals generated by the above and the output signal of the period selecting means and the 2 ^m signals generated by m bits of the digital signal. Two output control means for outputting a signal that is valid only during the period selected by the period selection means, and an output for outputting a voltage applied to the selected power supply line by conducting a signal from the output control means. A voltage divided into a plurality of voltages between two voltages based on 2 ^h signals generated by the h (h = n−m−k) bits of the digital signal. Select one of the

In the above configuration, when an n-bit digital signal is input, 2 ^k signals and 2 ^m signals are created by k bits and m bits, respectively. Then, the period selecting means selects at least one period of the divided periods using the 2 ^k signals. On the other hand, by the output control means, for example, the output signal of the period selection means and 2 ^m
The logical product of these signals is calculated, and a signal that is valid only during the period selected by the period selecting means is output to two of the power supply lines. Then, the output means conducts on the basis of this signal, whereby two voltages in the selected period are output from the selected two power supply lines. Then, in the intermediate value generating means, one of the 2 ^h voltages between the two voltages is generated based on the 2 ^h signals.

As a result, the ^number of power supply lines required for displaying an image of 2 ⁿ gradation is 2 ^m +1 and it is greatly reduced. For example, if m = k = h = 2, it is possible to display an image of 64 gradations with five power lines. Also, m =
When 3, k = 3 and h = 2, an image with 256 gradations can be displayed with nine power lines.

Further, since the output means has 2 ^{m + 1} transfer gates respectively connected to the power supply lines, when the voltage is taken in from the two power supply lines to the intermediate value generation means. Each is only through one transfer gate. Therefore, the conduction characteristic from the power supply line to the output has a low resistance, and the voltage drop can be suppressed.

Further, a counter for generating k pulse signals having different periods is provided, and the period selecting means outputs 2 ^k signals which are effective in each divided period based on the pulse signal from the counter. As a result, the counter outputs k pulse signals based on the clock, so that it is not necessary to input k pulse signals from the outside, and the number of input signal lines can be reduced.

In the second voltage output circuit, since the range of the voltage applied to the plurality of power supply lines is continuous in each of the divided periods, two adjacent levels of the intermediate value generating means are provided. One voltage can be easily obtained.

In the first and second voltage output circuits, the period selecting means selects one of the divided periods to simplify the circuit configuration.

In the first and second voltage output circuits, the period selecting means selects a continuous period from the first period of the divided periods to the period in which a desired digital signal is input. As a result, it is possible to take a long time to take in a voltage at a level where there is a risk of insufficient writing with respect to the capacity of the output line, and it is possible to accurately output the voltage.

In the image display device of the present invention, a plurality of display pixels arranged in a matrix, data signal lines connected to these pixels, and a video signal formed of a digital signal are data signals at a predetermined timing. In the image display device including a data signal line drive circuit for writing in a line, the data signal line drive circuit includes any one of the above voltage output circuits, and the voltage output circuit causes the power supply line to be connected to the power supply line based on a video signal. It is characterized in that the applied voltage is output to the data signal line.

In this configuration, the data signal line drive circuit is provided with any one of the above voltage output circuits, so that the number of power supply lines can be reduced as compared with the gradation of an image to be displayed, and the power supply circuit It is possible to simplify the configuration and reduce the number of external terminals for power lines. Further, it is possible to secure a sufficient time required for writing the video signal to the data signal line, and it is possible to output a precise gradation voltage.

In the image display device, the polarity of the voltage applied to the power supply line is alternately changed for each horizontal scanning period, so that a good image without flicker can be displayed.

In the image display device, the polarity of the voltage level applied to the power supply line is alternately changed in each vertical scanning period, so that the number of times the output polarity of the power supply circuit is switched is reduced and the power consumption is reduced. Is planned.

In the above image display device, a digital signal generated by using the pseudo gradation display method utilizing the characteristics of the human eye is input, so that more images are displayed in addition to the gradation display by the voltage output circuit. It is possible to display gradation.

In the above image display device, since the switching element forming the pixel is a polycrystalline silicon thin film transistor, the time required for writing the video signal into the pixel is shortened, and one horizontal scanning period is reduced to one.
Writing can be performed well even in the period of / 2 ^k .

In the above image display device, since the data signal line drive circuit is composed of the polycrystalline silicon thin film transistor, the data signal line drive circuit can be formed on the same substrate as the pixel in the same process. Therefore, the manufacturing process of the image display device is simplified.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 1 to 31.

[Structure of Liquid Crystal Display Device] The image display device according to the present embodiment is an active matrix liquid crystal display device, and as shown in FIG. 2, a pixel array 1, a source driver 2, and a gate driver. 3 and control circuit 4
A power supply circuit 5 and a gradation power supply 6.

The pixel array 1, the source driver 2 and the gate driver 3 are formed on the substrate 7. Substrate 7
Is formed of an insulating and translucent material such as glass. Further, a substrate 8 made of the same material as the substrate 7 is bonded to face each other, and liquid crystal is sealed between them, thereby forming a liquid crystal panel 9.

The pixel array 1 has a large number of source lines S.
L ... and a large number of gate lines GL ... Are arranged so as to be orthogonal to each other. In addition, adjacent gate lines GL and GL
One pixel 10 is provided in each of the regions surrounded by the source lines SL and SL which are adjacent to each other.
0 ... Are arranged in a matrix.

As shown in FIG. 3, the pixel 10 is composed of a switching element SW composed of a field effect transistor and a pixel capacitance C _P. The pixel capacitance C _P has a liquid crystal capacitance C _L , and an auxiliary capacitance C _S is added if necessary.

The source line SL and one electrode of the pixel capacitor C _P are connected via the source and drain of the switching element SW. The gate of the transistor SW is connected to the gate line GL, and the other electrode of the pixel capacitance C _P is connected to a common electrode line common to all pixels. Then, the voltage applied to each liquid crystal capacitance C _L modulates the transmittance or reflectance of the liquid crystal to perform display.

The source driver 2 selects one of a plurality of grayscale voltages from the grayscale power source 6 for a specific period based on the input digital video signal and outputs it to one source line SL. It is like this. The source driver 2 will be described in detail later with an example.

The gate driver 3 sequentially selects the gate lines GL ... Based on the control signals CKG / SPG / GPS from the control circuit 4 to control the opening / closing of the switching elements SW in the pixels 10. There is. As a result, the data (gradation signal) given to each source line SL ... Is written in each pixel 10. The written data is held in the pixels 10.

The control circuit 4 controls the digital video signal DAT.
And the control signals CKS / SPS to be supplied to the source driver 2 and output the control signals CKG / SPG.
-GPS is output so as to be supplied to the gate driver 3. Further, the control circuit 4 outputs various control signals necessary for selecting the gradation voltage.

The power supply circuit 5 has power supply voltages V _SH , V _SL, and V _GH.
A circuit that generates V _GL , ground potential COM, and reference voltage V _REF . The power supply voltages V _SH and V _SL have different levels, and are supplied to the source driver 2.
The power supply voltages V _GH and V _GL are voltages having different levels, and are _{supplied to} the gate driver 3. Ground potential COM
Are applied to a common electrode line (not shown) provided on the substrate 8. The reference voltage V _REF is _supplied to the gradation power supply 6.

The gradation power source 6 is provided with a plurality of voltage generating circuits (not shown), and these voltage generating circuits generate the gradation voltages V of different levels based on the reference voltage V _REF . The voltage is applied to the source driver 2 via the gradation power supply line PL. The gradation power source 6 is _{supplied with} a clock CK from the control circuit 4 in addition to the above-mentioned reference voltage V _REF , and generates a stepwise gradation voltage V described later based on this clock CK. .

[First Source Driver] The first source driver is, as shown in FIG. 1, a scanning circuit 11, a sampling circuit 12, latches 13 and 13, and a decoder 14.
14 and a selection output circuit 15 are provided.

As shown in FIG. 4, the scanning circuit 11 includes a latch composed of clocked inverters 11a and 11b and an inverter 11c, and a sampling circuit for sampling one digital signal based on the start pulse SPS. The signal smp _i · / smp _i is generated. The shift register formed by connecting the scanning circuits 11 in multiple stages sequentially shifts the start pulse SPS in synchronization with the clock CKS (CLK / CLK).

As shown in FIG. 5, the sampling circuit 12 includes as many circuits as clocked inverters 12a and 12b and inverters 12c as many as the number of bits of a digital signal. The sampling circuit 12 shown in FIG. 5 has a configuration when the digital signal is 4 bits. The sampling circuit 12 is a circuit similar to the latch forming the scanning circuit 11, but the clocked inverters 12a and 12b are provided.
Is supplied with the sampling signal smp _i · / smp _i .

The latches 13 and 13 are n-bit digital signals DA output from the sampling circuit 12, respectively.
The upper k bits and lower m bits of T are held. The bits held in the latches 13 and 13 do not necessarily have to be divided into upper and lower bits. As shown in FIG. 6, the latch 13 includes a clocked inverter 13
It is a circuit provided with a circuit composed of a · 13b and an inverter 13c, the number of bits of data to be held. This circuit is
The held bit data D _j is transferred to the decoders 14 in synchronization with the transfer signal TF.

The decoders 14 and 14 have latches 13 and 13
2 based on the bit data D _j transferred from
^{The k} and 2 ^m decoded signals A are output. Decoder 14, for example, as shown in FIG. 7, an inverter ID ₁ ~ID _j to invert the bit data D ₁ to D _j of j bits, the AND circuit AD ₁ to AD
_{and f} (f = 2 ^j ).

When j = 4, AND circuits AD _{1 to} AD ₁₆
Is bit data D _{1 to} D ₄ and inverter ID ₁ to
From the bit data D _{1 to} D ₄ inverted by ID ₄ , four signals are logically ANDed in different combinations.

The selection output circuit 15 includes decoders 14 and 14
Based on the decode signal from, the level of one specific period in one of the plurality of grayscale voltages is selected.

As shown in FIG. 8, the gradation voltage is a voltage generated by the gradation power supply 6 described above so that the levels do not overlap between the 2 ^m gradation power supply lines PL. In addition, the gradation voltage is a period T ₁ divided into 2 ^k from the beginning of the horizontal scanning period (H).
~ T ₂ ^k (each about 1/2 ^k of horizontal scanning period)
Is a voltage with a ramp waveform whose level increases stepwise. Each of the gradation power supply lines PL has V _{1 to} V ₂ ^k and V ₂ ^{k.
_{+1 ~V 2 * 2 k, ...}} , V (2 m -1) gradation voltage ₂ ^k ₊₁ ~V ₂ ^m ₂ ^k is applied.

The gradation voltage may be, for example, a voltage as shown in FIGS. 9 to 11 other than the above voltages.

The gray scale voltage shown in FIG. 9 is a ramp waveform voltage that rises linearly instead of stepwise.

The voltages shown in FIG. 10 are simultaneously generated in the 2 ^m grayscale power supply lines PL in the same period, and the levels of the voltages are sequentially increased in the periods T _{1 to} T ₂ ^k with the level intervals kept uniform. It is a voltage having a waveform that rises stepwise. In this case, for each of the 2 ^m gradation power supply lines PL, V ₁ , V ₂ ^m ₊₁ , V _{2 * 2} ^m ₊₁ , ..., V are connected to the first gradation power supply line PL.
₍₂ ^k _{-1) 2} ^m ₊₁ , V ₂ to the second gradation power supply line PL,
V ₂ ^m ₊₂ , V _{2 * 2} ^m ₊₂ , ..., V ₍₂ ^k _{−1) 2} ^m ₊₂ , V ₂ ^m , V _{2 * 2} ^m , V _{3 * on} the m-th gradation power supply line PL ₂ ^m ,…, V ₂
^A gradation voltage is applied such as ^k ₂ ^m .

Similar to the voltage shown in FIG. 10, the voltage shown in FIG. 11 is generated simultaneously in the 2 ^m gradation power supply lines PL in the same period, but is a voltage having a waveform rising linearly instead of stepwise. Is.

The gradation voltage may be not only a ramp waveform that rises like the above-mentioned gray scale voltages but also a ramp waveform that falls. Other than that, period T ₁ , T ₂ , T ₃
It is sufficient that the gray scale voltage of each level described above is applied to the gray scale power supply line PL at any of T ₂ ^k , and the voltage level may change irregularly. Further, in the above example, the length of each period is 1/2 ^{k of the} horizontal scanning period, but the length is not limited to this and may be a different length. Further, in order to prevent the write signal from being mixed into pixels other than the pixel in which writing is performed, a certain period of the horizontal scanning period may not be used as the reset period.

The selection output circuit 15 is the selection circuit 1
6, a logic circuit 17 and an output switch 18.

The selection circuit 16 selects 2 of the above gradation voltages based on the timing signals TIM _{1 to} TIM _k shown in FIG.
It is a circuit that selects one of ^k periods. This selection circuit 16 is, for example, as shown in FIG. 13, an inverter I that inverts _k timing signals TIM _{1 to} TIM _k.
S _{1 to} IS _k , AND circuit AS _{1 to} AND circuit AS
_g (g = 2 ^k ) and transistors TS _{1 to} TS _g .

When k = 3, AND circuits AS _{1 to} AS ₈
Is a timing signal TI inverted by timing signals TIM _{1 to} TIM ₃ and inverters IS _{1 to} IS _3.
From M _{1 to} TIM ₃ , three signals are logically ANDed in different combinations. The transistors TS _{1 to} TS ₈ are turned on by the _eight decode signals AT _{1 to} AT 8 from the one decoder 14 to turn on the period T ₁
And outputs one of the period selection signal PRD ₁ ~PRD ₈ corresponding to through T _8.

The selection circuit 16 is similar to that shown in FIG.
As shown in, the counter 19 may be provided in the preceding stage of the selection circuit 16. In this configuration, the counter 19
However, based on the clock CK and the reset signal RES applied to the gradation power source 6, the timing signals TIM ₁ to
TIM _k is generated and supplied to the selection circuit 16. Therefore, the signal lines for the timing signals TIM _{1 to} TIM _k wired to the source driver are unnecessary.

The logic circuit 17 uses the above period selection signal PR.
This is a circuit for selecting one from the 2 ^m gradation power supply lines PL based on D. For example, as shown in FIG. 15, the logic circuit 17 includes a period selection signal PRD and the other decoder 14
2 ^m (m = 3) decoded signals AV _{1 to} AV _{8 from}
This is a circuit composed of AND circuits AL _{1 to} AL ₈ which respectively take the logical product of and.

The output switch 18 is composed of a plurality of analog switches. As shown in FIG. 16, the output switch 18 includes AND circuits AL _{1 to} A ₁ of the logic circuit 17.
ON by write pulse S _{1 to} S ₈ (m = 3) from L ₈
The transistors TO _{1 to} TO ₈ are provided. One of the eight gradation voltages V _{1 to} V ₈ is selected and output to the source line SL by turning on only _one of the transistors TO _{1 to} TO ₈ .

The output switch 18 has a configuration other than that described above.
Each of the transistors TO _{1 to} TO ₈ may be replaced with the transfer gate 21 shown in FIG.

The transfer gate 21 includes an n-channel type transistor 21a and a p-channel type transistor 21b.
And has a CMOS configuration in which parallel connection is made. In order to operate the transistor 21b at the same time as the transistor 21a, the inverter 22 for inverting the write pulse S is required. In such an analog switch, by using the transfer gate 21, the conduction resistance can be lowered as compared with the case where an n-channel type or p-channel type transistor is used alone.

Next, the operation of the source driver configured as above will be described.

First, the n-bit digital signal DAT is
The sampling circuit 12 samples and holds in synchronization with the sampling signal generated by the scanning circuit 11. The held n-bit digital signal DAT
Is divided into m bits and k bits, and latches 13.1.
Holds at 3.

The m-bit data and the k-bit data are transferred to the decoders 14 and 14 in synchronization with the transfer signal TF in the horizontal scanning period next to the horizontal scanning period sampled by the sampling circuit 12, Each is decoded at 14. 2 from the decoder 14
^{The k} decoded signals and the 2 ^m decoded signals are respectively output and given to the selection output circuit 15.

In the selection circuit 16, 2 ^k period selection signals PRD are generated from the ^k timing signals TIM.
Further, one of the 2 ^k period selection signals PRD is selected by the 2 ^k decoded signals from one latch 13.

On the other hand, in the logic circuit 17, the write pulse S which is a product signal of the period selection signal PRD and the 2 ^m decode signals output from the other latch 13 is written.
Is generated.

Of the 2 ^m grayscale power supply lines PL, one transistor of the output switch 18 is turned on for the ON period of the period selection signal PRD using the 2 ^m write pulses S. One is selected. As a result, the desired grayscale voltage V is output to the source line SL during one of the 2 ^k periods.

[0085] At this time, each of the 2 ^m the gradation power line PL, as shown in FIG. 8, is divided one horizontal scanning period is a period T ₁ through T ₂ ^k of 2 ^k, each period T ₁ A gradation voltage that changes stepwise is given to T ₂ ^k . therefore,
By giving an n-bit digital signal, 2
Any one of the ^{m + k} (= 2 ⁿ ) levels of the gradation voltage is output.

As described above, according to the present source driver, in order to output the voltage of 2 ⁿ gradations, only 2 ^m gradation power supply lines PL and k timing signal lines are required. , The number of external terminals is greatly reduced. Further, since the period for writing the gradation voltage is about 1/2 ^k of the horizontal scanning period, it is possible to sufficiently write the video data, and highly accurate gradation display can be obtained.

For example, if a 6-bit digital signal is m = 3
When divided into bits and k = 3 bits, 64 (= 2 ⁶ ) gradations can be displayed by 8 (= 2 ³ ) gradation power supply lines PL. Moreover, the writing period of the gradation voltage can be secured to about 1/8 (= 2 ³ ) of the horizontal scanning period.

Further, the transfer gate 21 is connected to the output switch 18.
By using, the grayscale voltage from the grayscale power supply line PL is taken in via one transfer gate (analog switch) 21. As a result, the conduction resistance from the gradation power supply line PL to the output becomes low, and sufficient writing characteristics can be obtained. As a result, the write shortage can be resolved and the size of the analog switch (channel length) can be reduced. In particular, a reduction in the size of the analog switch not only reduces the size of the circuit but also reduces noise (depending on the channel capacity) generated when the analog switch is cut off, which has the advantage of improving the writing accuracy. .

By the way, in the above-mentioned source driver, as shown in FIG. 8, the gradation voltages in the range not overlapping with each other are applied to the gradation power supply lines PL. By applying the voltage having such a waveform, the same voltage generating circuit is used for the adjacent voltages.

Therefore, it is possible to prevent the inversion of the voltages whose gradations are close to each other between the voltage generation circuits due to the influence of the variation (offset voltage or the like) of the voltage generation circuits.
Further, since the voltages applied to the respective gradation power supply lines PL are close and continuous within the horizontal scanning period, the gradation power supply lines P are
The charge / discharge current to L can be suppressed, and the power consumption can be reduced.

Further, in this source driver, as shown in FIG. 12, the period selection signal PRD for controlling the period for writing the gradation voltage is a pulse having a length of one period, but not limited to this, for example, As shown in FIG. 18, the control signal PRD having a length from the beginning of the horizontal scanning period to the period in which the grayscale voltage corresponding to desired video data is applied may be used.
At this time, the writing time is substantially lengthened by applying a gradation voltage having a large level, which takes a long time to write by the output switch 18, in time later.
Therefore, there is no risk of insufficient writing of video data, and precise control of signal output becomes possible.

To generate the period selection signal PRD as described above, for example, the selection circuit 16 as shown in FIGS. 19 and 21 is adopted. In addition, the following selection circuit 16
This is the configuration when k = 3.

The selection circuit 16 shown in FIG. 19 is provided with inverters IS _{1 to} IS ₃ , AND circuits AS _{1 to} AS ₈ and transistors TS _{1 to} TS _{8 in} the selection circuit 16 shown in FIG. But AND circuit AS ₁
OR circuit OS ₁ ~OS ₇ is provided between the ～AS ₈ and the transistor TS ₁ ~TS _8. OR circuit OS ₁ ~
OS ₇ is adapted to take the logical sum of the corresponding AND circuit and the adjacent AND circuit.

In such a configuration, as shown in FIG. 20, the signals P _{1 to} P ₈ are output from the AND circuits A _{11 to} A ₁₈ . The OR circuit OS ₁ ~OS _7, the signal P ₁ to P ₇
And the signals P _{2 to} P ₈ are respectively ORed,
A period selection signal PRD is obtained in which the period is gradually increased.

In the selection circuit 16 shown in FIG. 21, flip-flops FS _{1 to} FS ₈ connected to AND circuits AS _{1 to} AS ₈ are replaced with OR circuits OS _{1 to} OS ₇ in the selection circuit shown in FIG. I have it. As shown in FIG. 22, the flip-flop FS is an SR-type flip-flop, and has a configuration in which the NOR circuits 23 and 24 are connected by crossing. Also, the flip-flop FS ₁
~ FS ₈ is a reset signal RES common to the set input S
Is given.

[0096] In such a configuration, as shown in FIG. 23, by using a timing signal TIM ₁ ~TIM ₃ different from the timing signal TIM ₁ ~TIM ₃ shown in FIG. 20, A
The signals P _{1 to} P ₈ are output from the ND circuits AS _{1 to} AS ₈ . The flip-flops FS _{1 to} FS ₈ receive the signals P _{1 to} P ₈ at the reset input R,
A period selection signal PRD that outputs a period that becomes longer is output.

[0097] In the configuration shown in FIG. 1, it had the logical operation of k timing signals TIM generates the 2 ^k-number of periods selection signal PRD, not limited to this, direct 2 ^k number of period from the outside The selection signal PRD may be input. Although this configuration increases the number of external input signal lines, it has the advantage of simplifying the circuit configuration in the source driver.

On the contrary, by incorporating the counter 19 in the source driver as shown in FIG. 14, it is possible to generate k timing signals TIM based on the clock CK input to the gradation power supply 6. Is. In this case, the number of external input signal lines becomes smaller.

Further, in this source driver, the digital signal which is a video signal is output from n video signal lines.
Although it was captured in synchronization with the sampling signal output from one scanning circuit 11, the digital signal itself may be scanned and captured for each one horizontal scanning period.

To realize this, the configuration shown in FIG. 24 is adopted. In this configuration, n scanning circuits 11 ... Are provided for an n-bit digital signal, and each scanning circuit 11 ... Samples each bit data D _{1 to} D _n of the video signal directly. . Therefore,
This source driver does not require the sampling circuit 12 in the source driver shown in FIG.

In the above source driver, the case where the number of gradation signal lines and period selection signals PRD is a power of 2 has been described. This is because the digital signal is a binary number representation, which is more efficient. However, in consideration of the performance and the number of external control circuits 4 that divide and expand the video signal, for example, the number of gradation signal lines is three.
In some cases, the case such as 5 is more convenient. Therefore, the number of reference signal lines and period selection signals PRD does not necessarily have to be a power of 2, and may be any number.

For example, the source driver shown in FIG. 25 has a structure in which m gradation power supply lines PL and k timing signals TIM (= period selection signal PRD) are applied to an n-bit digital signal. And 2 ⁿ ≤m *
k. Further, the gradation voltage having the waveform shown in FIG. 26 is input to each gradation power supply line PL. The gradation voltage has a stepwise stepwise level like V ₁ to V _k (first gradation power supply line PL) in _k periods T _{1 to} T _{k in} which the horizontal scanning period is evenly divided. It has a rising waveform.

In this source driver, the n-bit digital signal sampled by the sampling circuit 12 is held in the latch 13 as it is and further decoded by the decoder 14. Then, the selection output circuit 15
Then, one gradation power supply line PL and one period are selected based on the 2 ⁿ decoded signals from the decoder 14 and the timing signal TIM. As a result, the selected voltage is output to the source line.

For example, in the case of n = 5, m = 5, k = 7,
In the selection output circuit 15, 2 ⁵ = 3 in the selection circuit 16.
Seven of the two decoded signals are used for the periods T _{1 to} T _7.
, One of the period selection signals PRD _{1 to} PRD ₇ corresponding to is selected. Then, using the 32 write pulses S output from the logic circuit 17 based on the 7 decode signals, the output switch 18 causes only one period from one of the five grayscale power supply lines PL. The voltage is output. As a result, 35 levels of voltage can be obtained. However, 3
When displaying two gradations, the voltage for three gradations is not used.

The various changes in the source driver described above are applicable not only to the source driver but also to the following source drivers.

[Second Source Driver] As shown in FIG. 27, the second source driver includes a scanning circuit 11, a sampling circuit 12, latches 13, 13, 13, decoders 14, 14, 14, A selection output circuit 31 and an intermediate value generator 32 are provided.

The constituent elements of the present source driver having the same functions as the constituent elements of the first source driver are designated by the same reference numerals, and the description thereof will be omitted.

In this source driver, the n-bit digital signal DA sampled by the sampling circuit 12 is used.
T is divided into k bits, m bits, and h bits for processing. Therefore, the three latches 13.1.
3.13 and three decoders 14.14.14 are provided.

The selection output circuit 31 selects the level of one specific period in two gradation voltages of a plurality of gradation voltages based on the decode signals from the first and second decoders 14 and 14. It is supposed to do.

The gradation voltage is as shown in FIG.
The waveform is similar to the gradation voltage shown in, but 2 ^m +
It is applied to one gradation power supply line PL. Further, it differs from the gradation voltage shown in FIG. 10 in that the highest voltage in each period and the lowest voltage in the next period are set to the same level.

The selection output circuit 31 is the selection circuit 1
6, a logic circuit 17 and an output switch 33.

[0112] The output switch 33, as shown in FIG. 29, includes a transistor TOA ₁ ~TOA ₈ and transistor TOB ₁ ~TOB _8, based on the 2 ^m-number of write pulse S from the logic circuit 17 2 Two voltages VA and V
B is output.

[0113] transistor TOA ₁ ~TOA ₈ is connected to the output line commonly, the transistor TOB ₁ ~TOB ₈
Are connected to a common output line different from the transistors TOA _{1 to} TOA ₈ . Also, the transistor TOA ₁
TOB ₁ or the transistors TOA ₈ and TOB ₈ are paired, and the same write pulse S (S
_{1 to} S ₈ ) are input. Furthermore, the transistor TOA
_The gradation power supply lines PL which are adjacent to each other are sequentially connected to ₁ · TOB ₁ or the transistors TOA ₈ · TOB ₈ .

The intermediate value generator 32 uses the above voltage VA · V.
It is a circuit for outputting a plurality of intermediate values between the voltages VA and VB from B using the 2 ^h decoded signals from the third decoder 14. The intermediate value generator 32 shown in FIG.
In the case of 3, the resistors R _{1 to} R connected in series are connected.
₈ and transfer gates G _{1 to} G ₈ .

The transfer gates G _{1 to} G ₈ are write pulses S _{1 to} S from the logic circuit 17 to the n-channel type transistors.
₈ is given, inversion pulses of the write pulse S ₁ to S ₈ is applied to the p-channel transistor. The transfer gate G ₁ is connected to one end of the resistor R ₁ , and the transfer gates G _{2 to} G ₈ are connected to respective connection points of the resistors R _{1 to} R ₈ .

The intermediate value generator 32 has a voltage of VA · V.
If it is possible to output a plurality of intermediate voltage values from B,
It may be composed of other circuits.

Next, the operation of the source driver configured as above will be described.

First, in synchronization with the sampling signal generated by the scanning circuit 11, the sampling circuit 12 samples and holds the n-bit digital signal DAT which is video information. The held n-bit digital signal DAT is divided into m bits, k bits, and h bits, and held by the three latches 13, 13, 13.

The m-bit data and the k-bit data are 2 in synchronization with the transfer signal TF in the horizontal scanning period next to the horizontal scanning period sampled by the sampling circuit 12.
Is transferred to each decoder 14
4 are decoded respectively. Decoders 14 and 14 output 2 ^k decoded signals and 2 ^m decoded signals, respectively, and provide them to the selection output circuit 31.

Operations of the selection circuit 16 and the logic circuit 17 in the selection output circuit 31 are similar to those of the first source driver. That is, the selection circuit 16 selects one of the 2 ^k period selection signals PRD, while the logic circuit 17 generates the write pulse S from the period selection signal PRD and the 2 ^m decoded signals. To be done.

By using these 2 ^m write pulses S, two transistors of the output switch 33 are rendered conductive only during the ON period of the period selection signal PRD, so that 2 ^m +1 gradation power supply lines PL are connected. Two of them are selected.

[0122] At this time, each of the 2 ^m +1 pieces of gradation power line PL, as shown in FIG. 28, is divided one horizontal scanning period is a period T ₁ through T ₂ ^k of 2 ^k, in the same period A gradation voltage that is generated at the same time and that changes stepwise in each period T _{1 to} T ₂ ^k is applied. Therefore, by applying an n-bit digital signal, two adjacent voltages VA and VB having a level of 2 ^{m + k} are output.

Further, 2 ^h decoded signals obtained by decoding the h-bit digital signal by the other decoder 14 are applied to the intermediate value generator 32. Intermediate value generator 3
2, any _one of the transfer gates G _{1 to} G ₈ is turned on by the decode signal, and an arbitrary intermediate value of the above two voltages VA and VB is selected and desired via the transfer gate G. Is output to the source line SL as a grayscale signal.

As described above, according to the present source driver, in order to output the voltage of 2 ⁿ gradations, only 2 ^m +1 gradation power supply lines PL and k timing signal lines are required. Therefore, the number of external terminals is significantly reduced. Also,
The period for writing the gradation voltage is approximately 1/2 ^{k of the} horizontal scanning period.
Since this is the length, it is possible to write the video data sufficiently, and it is possible to obtain a highly accurate gradation display.

Moreover, since the highest voltage in each period of the gradation voltage and the lowest voltage in the next period are set to the same level, the potential difference between the voltages VA and VB is obtained by dividing the potential difference at equal intervals. be able to. Therefore, the first
Compared with the source driver of (1), even with the same number of external input signals, it is possible to output a signal voltage of multiple gradations (2 ^h times). For example, when the digital signal is 6 bits and m = k = h = 2, five gradation power supply lines PL are used.
Thus, it is possible to display 2 ⁶ = 64 gradations. Also, m =
If 3, k = 3, and h = 2, it is possible to display 256 gradations with the 9 gradation power supply lines PL.

By the way, in the present source driver, one intermediate value generator 32 is provided for each stage of the source line SL, but a different configuration may be used. For example, in the configuration shown in FIG. 31, the intermediate value generator 34 common to all stages is provided in the gradation power supply line PL.
The intermediate value generator 34 is a circuit that connects two adjacent grayscale power supply lines PL that are connected via a resistance division circuit as shown in FIG.

Therefore, after the intermediate value generator 34, the gradation power supply line PL is increased to 2 ^{m + h} . Therefore, in the selection output circuit 31, one latch 13 and one decoder 14 are provided.
One voltage is output from the logic circuit 17 based on the 2 ^{m + h} decoded signals obtained by.

According to the above intermediate value generator 34, as shown in FIG.
Similar to the source driver shown in FIG. 2, 2 ⁿ gray scale display can be performed. Further, since the intermediate value generator 34 is common to each stage of the source line SL, it is not necessary to provide one for each stage like the intermediate value generator 32, and the configuration of the source driver can be simplified.

Further, in this source driver, since it is possible to secure the number of gradations by 2 ^m +1 gradation power supply lines PL and k timing signal lines, the intermediate value generator 32.
By reducing the resistance number of 34, it is possible to suppress the influence of variation in resistance value. Therefore, it is possible to increase the number of gradations and maintain good gradation display. For example, assuming that the upper limit of the practical resistance division number is 4 (h = 2), the present source driver has 64 gradations or 2 gradations as described above.
High gradations such as 56 gradations can be obtained, and the number of gradations can be significantly improved as compared with a conventional driver using a dividing resistor.

[Role of Source Driver in Liquid Crystal Display Device] By providing the first and second source drivers in the liquid crystal display device, even if the number of signals supplied to the liquid crystal panel 9 is small, multi-gradation is possible. The image signal of can be output. Therefore, even in a liquid crystal display device provided with a small number of external terminals on the liquid crystal panel 9, multi-gradation display is possible.

In particular, when the switching element SW forming the pixel 10 is a polycrystalline silicon thin film transistor having a small driving force, the writing of image data into the pixel capacitance C _P is speeded up. Therefore, even in the case of a large-sized liquid crystal display device, that is, even when the load of the source driver is large, it is possible to sufficiently write the pixel data within a predetermined time (1/2 ^{k of} one horizontal scanning period), which results in high quality. Image display becomes possible. This also applies to a high-definition liquid crystal display device (when the horizontal scanning period is short). Further, since the number of divisions of the writing period can be increased for the same load, an image with more gradation can be displayed.

When the active element forming the source driver is a polycrystalline silicon thin film transistor, the active element can be manufactured in the same process as the switching element SW. Therefore, the product cost of the liquid crystal display device can be reduced.

Further, since the polarity of the voltage applied to the gradation power supply line PL is switched every horizontal scanning period or every vertical scanning period, the flicker of the display image can be suppressed, so that the display quality of the liquid crystal display device is improved. To do. In the former case, the gate line inversion driving method is used. In the latter case, the frame inversion drive system is used, but by using two power supply systems for the source driver, a source line inversion drive system with even better display quality can be used (SID 93 DI
GEST p.15-18). At this time, the number of times the output polarity of the external power supply circuit is switched is reduced, so that power consumption can be reduced.

Further, when the image signal input to the liquid crystal display device is generated by using the pseudo gradation display method,
It is possible to effectively display a multi-tone image.
In particular, since the present invention has a configuration in which a digital signal is used as an input signal, the result of the arithmetic processing for pseudo gradation display can be used as it is. Therefore, the increase in the circuit scale accompanying this is small.

The pseudo gradation display method here is a gradation display method utilizing the characteristics of human eyes, and examples thereof include a dither method and an error diffusion method. What kind of method may be used? I don't mind. Further, the area gradation method is also included in the category of the pseudo gradation display method in a broad sense.

In the present embodiment, an example in which the present invention is applied to a liquid crystal display device has been described, but the present invention is also applied to other image display devices. The present invention is not limited to this, and the present invention can be applied to devices other than the image display device for the same purpose.

[0137]

As described above, the voltage output circuit according to claim 1 of the present invention includes a plurality of power supply lines to which different voltages are applied in each divided period in a scanning period divided into a plurality of periods. By selecting any one of the power supply lines in at least one of the divided periods based on a digital signal of a plurality of bits, the voltage applied to the power supply line selected in the selected period is output. And a selection output unit for performing the selection.

Thus, for example, when the present voltage output circuit is applied to the data signal line drive circuit of the image display device, the number of power supply lines can be reduced as compared with the gradation of the image to be displayed. Therefore, it is possible to simplify the configuration of the external power supply circuit and reduce the number of external terminals for power supply lines. In addition, it is possible to secure a sufficient divided period and output a precise gradation voltage. Therefore, it is possible to reduce the cost of the external power supply circuit and the mounting cost of the voltage output circuit.

A voltage output circuit according to a second aspect of the present invention is the voltage output circuit according to the first aspect, wherein the power supply line is 2 ^m (1 <
m <n) present provided, 2 ^k of the selection output means, at least one period of the divided the divided period 2 ^k created by k bits of said digital signal (k = n-m)
One of the power supply lines based on the period selecting means for selecting based on the number of signals and the output signal of the period selecting means and the 2 ^m signals generated by m bits of the digital signal. It has an output control means for outputting a signal which is effective only during the period selected by the selection means, and an output means for outputting a voltage applied to the selected power supply line by conducting a signal from the output control means. It has a structure.

As a result, the ^number of power supply lines required for displaying an image of 2 ⁿ gradations is 2 ^m , which can be greatly reduced, and the cost can be further reduced in the voltage output circuit according to claim 1. There is an effect that can be.

A voltage output circuit according to a third aspect of the present invention is the voltage output circuit according to the second aspect, wherein the output means has 2 ^m transfer gates respectively connected to the power supply lines. , Only via one transfer gate when taking in the voltage from the power supply line. Therefore, the conduction characteristic from the power supply line to the output has a low resistance, and the voltage drop can be suppressed. Therefore, there is an effect that the video signal can be favorably written to the data signal line.

According to a fourth aspect of the present invention, in the voltage output circuit according to the first aspect, the range of the voltage applied to each of the power supply lines within the scanning period is different between the power supply lines. Since they do not overlap, the level change amount of the voltage of each power supply line becomes small. Therefore, the time required for the voltage level to stabilize becomes shorter and the scale of the external power supply circuit for applying the voltage to the power supply line can be reduced. In addition, the external power supply circuits that supply voltages that are close to each other can be the same, and it is difficult for the inversion of gray scales due to the output variations of the external power supply circuits to occur. Therefore, there is an effect that the video signal can be favorably written to the data signal line.

According to the fifth aspect of the present invention, in the voltage output circuit, a plurality of power supply lines to which different voltages are applied in each divided period in a scanning period divided into a plurality of periods, and a digital signal of a plurality of bits are provided. And selecting output means for outputting the voltage applied to the power supply line selected in the period by selecting any two of the power supply lines in at least one of the divided periods based on the above; And intermediate value generating means for generating a voltage between the two voltages selected by the selecting and outputting means.

Thus, for example, when the present voltage output circuit is applied to the data signal line drive circuit of the image display device, the number of power supply lines can be reduced as compared with the gradation of the image to be displayed. This can simplify the configuration of the external power supply circuit and reduce the number of external terminals for power supply lines. Further, since the divided period can be ensured to have a sufficient length, it is possible to output a precise gradation voltage. Further, since the voltage between the two voltages is output by the intermediate value generating means, it is possible to output more voltages of different levels, and it is possible to increase the number of gradations or reduce the number of power supply lines. . Therefore, it is possible to reduce the cost of the external power supply circuit and the mounting cost of the voltage output circuit.

According to a sixth aspect of the present invention, in the voltage output circuit according to the fifth aspect, the power supply line is 2 ^m +1 for the n-bit digital signal.
(1 <m <n) are provided, and the selection output means is 2 ^k
Period selecting means for selecting at least one period of the divided period divided based on 2 ^k signals created by k bits (1 <k <n−m) of the digital signal, and the period selecting means. Output control for outputting a signal that is valid only during the period selected by the period selecting means in two of the power supply lines based on the output signal of 2 ^m and 2 ^m signals generated by m bits of the digital signal. Means for outputting a voltage applied to the selected power supply line by means of a signal from the output control means, wherein the intermediate value generating means is a digital signal h of the digital signal.
The configuration is such that one of the voltages divided into a plurality of two voltages is selected based on the 2 ^h signals generated by (h = n−m−k) bits.

As a result, the ^number of power supply lines required to display an image of 2 ⁿ gradations is 2 ^m +1 and can be greatly reduced, and the cost can be further reduced in the voltage output circuit according to claim 5. The effect that it can be achieved is produced.

According to a seventh aspect of the present invention, in the voltage output circuit according to the sixth aspect, the output means includes 2 ^{m + 1} transfer gates respectively connected to the power supply lines. Since it has, it takes only one transfer gate each to take in the voltage from the two power supply lines. Therefore, the conduction characteristic from the power supply line to the output has a low resistance, and the voltage drop can be suppressed. Therefore, there is an effect that the video signal can be favorably written to the data signal line.

The voltage output circuit according to claim 8 of the present invention is the voltage output circuit according to claim 1 or 6, wherein:
Since the range of the voltage applied to the plurality of power supply lines is continuous in each of the divided periods, it is possible to easily obtain two voltages of the adjacent levels to be given to the intermediate value generating means, and to configure the circuit. The effect that it can be simplified is exhibited.

The voltage output circuit according to claim 9 of the present invention is the voltage output circuit according to claim 1 or 6, wherein:
Since the period selecting means selects one of the divided periods, there is an effect that the circuit configuration can be simplified.

A voltage output circuit according to claim 10 of the present invention is the voltage output circuit according to claim 1 or 6, wherein:
Since the period selection means selects a continuous period from the first period of the divided periods to the period in which a desired digital signal is input, the voltage of a level at which writing capacity may be insufficient with respect to the capacitance of the output line is selected. It can take a long time. Therefore, there is an effect that the voltage can be accurately output, and the video signal can be favorably written in the data signal line.

A voltage output circuit according to claim 11 of the present invention is the voltage output circuit according to claim 2 or 7, wherein:
A counter for generating k pulse signals having different periods is provided, and the period selecting means outputs 2 ^k signals that are effective in each of the divided periods based on the pulse signal from the counter, so that the counter clocks. The number of input signal lines can be reduced because k pulses are output based on Therefore, there is an effect that the configuration of the circuit can be simplified.

According to a twelfth aspect of the present invention, there is provided an image display device, comprising a plurality of pixels arranged in a matrix for display.
In an image display device including a data signal line connected to these pixels, and a data signal line drive circuit for writing a video signal composed of a digital signal to the data signal line at a predetermined timing, the data signal line drive circuit includes: In any one of the above voltage output circuits, the voltage output circuit outputs the voltage applied to the power supply line to the data signal line based on a video signal.

As a result, the number of power supply lines can be reduced as compared with the gradation of the image to be displayed, and the structure of the power supply circuit can be simplified and the number of external terminals for power supply lines can be reduced. Further, it is possible to secure a sufficient time required for writing the video signal to the data signal line, and it is possible to output a precise gradation voltage. Therefore, it is possible to reduce the cost of the image display device and improve the display quality.

An image display device according to a thirteenth aspect of the present invention is the image display device according to the twelfth aspect, wherein the polarity of the voltage applied to the power supply line alternates every horizontal scanning period. It is possible to display an excellent image without flicker.

An image display device according to a fourteenth aspect of the present invention is the image display device according to the twelfth aspect, wherein the polarity of the voltage level applied to the power supply line alternates every vertical scanning period. The number of times of switching the output polarity of the power supply circuit is reduced, and it is possible to achieve low power consumption.

An image display device according to a fifteenth aspect of the present invention is the image display device according to the twelfth aspect, wherein a digital signal generated by using a pseudo gradation display method utilizing the characteristics of human eyes is used. By inputting, in addition to gradation display by the voltage output circuit, display of more gradations is possible. Therefore, it is possible to provide an image display device having an extremely high display quality.

According to a sixteenth aspect of the present invention, in the image display apparatus according to the twelfth aspect, since the switching element forming the pixel is a polycrystalline silicon thin film transistor, a video signal is written in the pixel. The time required for this is shortened to 1 / one horizontal scanning period.
There is an effect that writing can be performed favorably even in the 2 ^k period.

An image display device according to a seventeenth aspect of the present invention is the image display device according to the twelfth aspect, wherein the data signal line drive circuit is composed of a polycrystalline silicon thin film transistor. The driver circuit can be formed over the same substrate as the pixel in the same process, and the manufacturing process of the image display device is simplified. Therefore, there is an effect that the cost of the image display device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first source driver in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of the liquid crystal display device.

3 is a circuit diagram showing a configuration of a pixel in the liquid crystal display device of FIG.

4 is a circuit diagram showing a configuration of a scanning circuit in the source driver of FIG.

5 is a circuit diagram showing a configuration of a sampling circuit in the source driver of FIG.

6 is a circuit diagram showing a configuration of a latch in the source driver of FIG.

7 is a circuit diagram showing a configuration of a decoder in the source driver of FIG.

8 is a waveform diagram showing a waveform of a stepwise gradation voltage applied to the source driver of FIG.

9 is a diagram showing a waveform of a linear gradation voltage applied to the source driver of FIG.

10 is a waveform diagram showing another stepwise waveform of a gradation voltage applied to the source driver of FIG.

11 is a diagram showing a waveform of another linear gradation voltage applied to the source driver of FIG.

FIG. 12 is a waveform diagram showing waveforms of input / output signals relating to a selection circuit in the source driver of FIG.

FIG. 13 is a circuit diagram showing a configuration of the selection circuit.

14 is a block diagram showing a configuration in which a counter is added to the source driver of FIG.

15 is a circuit diagram showing a configuration of a logic circuit in the source driver of FIG.

16 is a circuit diagram showing a configuration of an output switch in the source driver of FIG.

FIG. 17 is a circuit diagram showing another configuration of the analog switch which constitutes the output switch.

FIG. 18 is a waveform diagram showing waveforms of other input / output signals related to the selection circuit in the source driver of FIG.

19 is a circuit diagram showing a configuration of a selection circuit for generating an output signal having the waveform of FIG.

20 is a waveform chart showing the operation of the selection circuit of FIG.

21 is a circuit diagram showing the configuration of another selection circuit for generating the output signal having the waveform of FIG. 18. FIG.

22 is a circuit diagram showing a configuration of a flip-flop in the selection circuit of FIG.

23 is a waveform chart showing an operation of the selection circuit of FIG.

FIG. 24 is a block diagram showing another configuration of the first source driver.

FIG. 25 is a block diagram showing still another configuration of the first source driver.

FIG. 26 is a waveform diagram showing a waveform of a stepwise gradation voltage applied to the source driver of FIG. 25.

FIG. 27 is a block diagram showing a configuration of a second source driver in the liquid crystal display device according to the embodiment of the present invention.

28 is a waveform diagram showing a waveform of a stepwise gradation voltage given to the source driver of FIG. 27.

29 is a circuit diagram showing a configuration of an output switch in the source driver of FIG.

30 is a circuit diagram showing a configuration of an intermediate value generator in the source driver of FIG. 27.

FIG. 31 is a block diagram showing a block configuration showing another configuration of the second source driver.

FIG. 32 is a block diagram showing a configuration of a main part of a conventional liquid crystal display device.

FIG. 33 is a block diagram showing a configuration of a conventional source driver.

FIG. 34 is a block diagram showing another configuration of a conventional source driver.

FIG. 35 is a waveform diagram showing a waveform of an oscillating voltage used in a conventional source driver displaying halftone.

FIG. 36 is a waveform chart showing a waveform of a gray scale voltage applied to a conventional source driver having one gray scale power supply line and a signal for selecting a gray scale voltage.

[Explanation of symbols]

 2 source driver (data signal line drive circuit) 6 gradation power supply 10 pixels 15/31 selection output circuit (selection output means) 16 selection circuit (period selection means) 17 logic circuit (output control means) 18/33 output switch (output 21) transfer gate 32 intermediate value generator (intermediate voltage generating means) PL gradation power supply line (power supply line) PRD period selection signal

Claims (17)

[Claims] 1. A plurality of power supply lines to which different voltages are applied in each divided period in a scanning period divided into a plurality of periods, and any one of the power source lines based on a digital signal of a plurality of bits. A voltage output circuit, comprising: a selection output unit that outputs a voltage applied to a power supply line selected in the selected period by selecting at least one of the divided periods. 2. The power supply line is provided for 2 ^m (1 <m <n) lines for the n-bit digital signal, and the selection output means is at least one of the divided periods divided into 2 ^k. One period is selected based on 2 ^k signals generated by k bits (k = n−m) of the digital signal, and an output signal of the period selection means and m bits of the digital signal. The output control means for outputting a signal that is valid only during the period selected by the period selection means on one of the power supply lines on the basis of the 2 ^m signals that have been generated, and conduction by the signal from the output control means. The voltage output circuit according to claim 1, further comprising: an output unit that outputs a voltage applied to the selected power supply line. 3. The voltage output circuit according to claim 2, wherein the output means has 2 ^m transfer gates respectively connected to the power supply lines. 4. The voltage output circuit according to claim 1, wherein ranges of voltages applied to the respective power supply lines within the scanning period do not overlap with each other between the power supply lines. 5. A plurality of power supply lines to which different voltages are applied in each divided period in a scanning period divided into a plurality of periods, and any two of the power supply lines based on a digital signal of a plurality of bits. Between the selection output means for outputting the voltage applied to the power supply line selected in the selected period by selecting at least one of the divided periods, and the two voltages selected by the selection output means. And an intermediate value generating means for generating the voltage of the voltage output circuit. 6. The power supply line is provided for 2 ^m +1 (1 <m <n) lines for the n-bit digital signal, and the selection output means is at least in the divided period divided into 2 ^k. Period selecting means for selecting one period based on 2 ^k signals generated by k bits (1 <k <n−m) of the digital signal, an output signal of the period selecting means and m of the digital signal. 2 ^m created by bit
Output control means for outputting a signal that is valid only for a period selected by the period selection means on two of the power supply lines based on the individual signals, and a signal from the output control means conducts and selects. And an output means for outputting a voltage applied to the power supply line, wherein the intermediate value generation means has a function of h (h = n) of the digital signal.
6. The voltage output circuit according to claim 5, wherein one of the voltages divided into a plurality of two voltages is selected based on 2 ^h signals generated by −m−k) bits. . 7. The voltage output circuit according to claim 6, wherein said output means has 2 ^{m + 1} transfer gates respectively connected to said power supply lines. 8. The voltage output circuit according to claim 6, wherein the range of the voltage applied to the plurality of power supply lines is continuous in each of the divided periods. 9. The voltage output circuit according to claim 2, wherein the period selecting means selects one of the divided periods. 10. The period selecting means according to claim 2, wherein the period selecting means selects a continuous period from the first period of the divided periods to a period in which a desired digital signal is inputted. Voltage output circuit. 11. A counter for generating k pulse signals having different periods is provided, and the period selecting means outputs 2 ^k signals that are effective in each of the divided periods based on the pulse signal from the counter. The voltage output circuit according to claim 2 or 6, wherein: 12. A plurality of display pixels arranged in a matrix and data signal lines connected to these pixels,
An image display device comprising a data signal line drive circuit for writing a video signal composed of a digital signal to a data signal line at a predetermined timing, wherein the data signal line drive circuit is the voltage according to any one of claims 1 to 11. An image display device comprising an output circuit, wherein the voltage output circuit outputs the voltage applied to the power supply line to the data signal line based on a video signal. 13. The image display device according to claim 12, wherein the polarity of the voltage applied to the power supply line alternates every horizontal scanning period. 14. The image display device according to claim 12, wherein the polarity of the voltage level applied to the power supply line alternates every vertical scanning period. 15. The image display device according to claim 12, wherein the digital signal is generated by using a pseudo gray scale display method utilizing the characteristics of human eyes. 16. The image display device according to claim 12, wherein the switching element forming the pixel is a polycrystalline silicon thin film transistor. 17. The image display device according to claim 12, wherein the data signal line drive circuit is composed of a polycrystalline silicon thin film transistor.