KR0127102B1 - A driving circuit of display apparatus - Google Patents

Abstract

The driving circuit of the present invention is used to drive a display device having a pixel and a data line for applying a voltage to the pixel and displaying the image in multiple gradations according to image data composed of a plurality of bits. The driving circuit specifies one of a plurality of vibration signals having different duty ratios according to the image data composed of selected bits of the plurality of bits, and the vibration obtained by inverting the specified vibration signal T and the specified vibration signal. Vibration voltage specifying means for outputting a signal T; According to the image data consisting of bits other than the selected bit among the plurality of bits, for generating a gradation voltage specifying signal for specifying a first gradation voltage and a second gradation voltage among a plurality of gradation voltages supplied from the gradation voltage supply means. Gradation voltage specification means; And output means for outputting the first gradation voltage and the second gradation voltage specified by the gradation voltage specifying signal according to the vibration signal T and the vibration signal T as data lines.

Description

Drive circuit of display device

1 is a configuration diagram of a liquid crystal display device.

2 is a timing chart showing a relationship between input data, sampling pulses and output pulses in one horizontal period.

3 is a timing chart showing the relationship between input data, output pulses, output voltages, and gate pulses in one vertical period.

4 is a timing chart showing a relationship between an input data, an output pulse, an output voltage, a gate pulse, and a voltage applied to a pixel in one vertical period.

5 is a waveform diagram of an output voltage oscillating in one output period.

6 is a view showing a part of a configuration of a data driver of a driving circuit according to an embodiment of the present invention.

7 is a view showing a part of the configuration for the selection control circuit SCOL of the drive circuit according to an embodiment of the present invention.

8 is a view showing another part of the configuration of the selection control circuit SCOL of the driving circuit according to the embodiment of the present invention.

9 is a view showing another part of the configuration of the selection control circuit SCOL of the driving circuit according to the embodiment of the present invention.

10 is a view showing another part of the configuration of the selection control circuit SCOL of the driving circuit according to the embodiment of the present invention.

11 is a view showing a part of the configuration of the data driver of the conventional driving circuit.

12 is a view showing a part of the configuration for the data driver of the driving circuit of the related art.

13 is a waveform diagram of signals t ₁ -t ₄ supplied to the selection control circuit SCOL.

14 is a view showing a part of the configuration for the selection control circuit SCOL of the conventional driving circuit.

FIG. 15 shows another part of the configuration of the selection control circuit SCOL of the conventional driving circuit. FIG.

* Description of the symbols for the main parts of the drawings *

100 display unit 101 driving circuit

102: data driver 103: scanning driver

104: pixel 105: switching element

106: data line 107: scan line

The present invention relates to a driving circuit of a display device. In particular, the present invention relates to an active matrix liquid crystal display device which displays an image in multiple gradations according to a digital video signal.

An active matrix liquid crystal display device includes a display panel and a driving circuit for driving the display panel. The display panel includes a pair of glass substrates and a liquid crystal layer formed between the glass substrates. A plurality of gate lines and a plurality of data lines are formed on one of the pair of glass substrates. The driving circuit is disposed for each pixel of the display panel and applies driving to the liquid crystal of the display panel. The driving circuit includes a gate driver for individually selecting one of a plurality of switching elements connected to a data line and a gate line, and a data driver for supplying an image signal corresponding to an image to the pixel electrode through the selected switching element.

11 shows the configuration of a part of the data driver of the conventional driving circuit.

The circuit 110 shown in FIG. 11 outputs a video signal to one of the plurality of data lines. Thus, the data driver requires the same number of circuits as the number of data provided to the display panel. For convenience of explanation, it is assumed that the image data is composed of 3 bits (D ₀ , D ₁ , D ₂ ). Under this assumption, the image data has eight values of 0 to 7, and the signal voltage supplied to each pixel is one of eight levels V ₀ -V ₇ .

The circuit 11 includes a sampling flip-flop M _SMP , a holding flip-flop M _H , a decoder DEC, and an analog switch ASW ₀ -ASW ₇ . Each of the analog switch (ASW ₀ -ASW ₇₎ is supplied with one of the external sources of mutually different voltages of the eight levels V ₀ -V _7. In addition, control signals S ₀ -S ₇ are respectively supplied from the decoder DEC to the analog switches ASW ₀ -ASW ₇ . Each control signal S ₀ -S ₇ is used to switch the ON / OFF state of the analog switch.

Next, the operation of the circuit 110 will be described. When the sampling pulse T _SMPN corresponding to the n-th pixel _rises , the sampling flip-flop M _SMP obtains image data D ₀ , D ₁ , and D ₂ to hold these image signals. When image data sampling for one horizontal period is completed, the output pulse signal OE is applied to the holding flip-flop M _H. According to the application of the output pulse signal OE, the holding flip-flop M _H obtains the image data D ₀ , D ₁ , D ₂ from the sampling flip-flop M _SMP and transmits the image data to the decoder DEC. do.

The decoder DEC decodes the image data D ₀ , D ₁ , D ₂ , and converts the analog switch ASW ₀ according to each value 0-7 of the image data D ₀ , D ₁ , D ₂ . Generate a control signal to turn on one of ASW _7's . As a result, one of the external source voltages V ₀ -V ₇ is output to the data line On. For example, when the value of the image data held in the holding flip-flop M _H is 3, the decoder DEC outputs a control signal S ₃ for turning on the analog switch ASW ₃ . Accordingly, the analog switch ASW ₃ is in an ON state, the external source voltage V ₀ -V ₇ of ₇ V is outputted to the data line On.

However, the conventional data driver has a problem in that the circuit configuration becomes complicated and the circuit size increases as the number of bits of the image data increases. This is because a conventional data driver is required so that the number of gray voltages is equal to the gray level to be displayed. For example, when the video data for displaying 16 grayscale images is composed of 4 bits, the number of grayscale voltages required is 2 ⁴ = 16. Similarly, when the video data for displaying 64 grayscale images is composed of 6 bits, the number of grayscale voltages required is 2 ⁶ = 64. The number of gradation voltages required when the video data for displaying 256 gradation images is composed of 8 bits is 2 ⁸ = 256. As described above, the conventional data driver increases the number of gradation voltages as the number of bits of the image data increases. This complicates the circuit configuration and increases the circuit size. In addition, the connection between the voltage source circuit and the analog switch is complicated.

For this reason, the practical application of the conventional data driver is limited to three bits of image data or four bits of image data.

In order to solve this conventional problem, methods and circuits for driving a display device have been proposed in Japanese Patent Laid-Open Nos. 4-136983, 4-140787, and 6-27900. Since Japanese Patent Laid-Open No. 6-27900 was published on February 4, 1994, it is not a prior art of the present application.

12 shows a part of the drive circuit described in Japanese Patent Laid-Open No. 6-27900. The circuit 120 shown in FIG. 12 outputs a video signal to one of the plurality of data lines. Thus, the data driver requires as many circuits 120 as the number of data lines provided on the display panel. It is assumed here that the image data is composed of 6 bits (D ₀ , D ₁ , D _2, D ₃ , D ₄ , D ₅ ). Under these assumptions, the image signal can have 64 values of 0-63, and the signal voltages applied to each pixel are nine gray voltages V ₀ , V ₈ , V ₁₆ , V ₂₄ , V ₃₂ , V ₄₀ , V One of a plurality of interpolation voltages generated from ₄₈ , V _56, and V ₆₄ and the gray voltages V ₀ , V ₈ , V ₁₆ , V ₂₄ , V ₃₂ , V ₄₀ , V ₄₈ , V _56, and V ₆₄ .

The circuit 120 includes a sampling flip-flop M _SMP , a holding flip-flop M _H , a selection control circuit SCOL, and an analog switch ASW ₀ -ASW ₈ . Each of the analog switches ASW _{0 to} ASW ₈ includes one of gray level voltages V ₀ , V ₈ , V ₁₆ , V ₂₄ , V ₃₂ , V ₄₀ , V ₄₈ , V _56, and V ₆₄ that are different from each other. Is supplied. In the analog switches ASW _{0 to} ASW ₈ , control signals S ₀ , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S _56, and S ₆₄ are respectively selected by the selection control circuit SCOL. Supplied. Each control signal is used to switch the ON / OFF state of the analog signal.

Clock signals t ₁ , t ₂ , t _3, and t ₄ are supplied to the selection control circuit SCOL. As shown in FIG. 13, clock signals t ₁ , t ₂ , t _3, and t ₄ have different duty ratios in an oath. The selection control circuit SCOL receives 6-bit image signals d ₅ , d ₄ , d ₃ , d ₂ , d _1, and d ₀ , and according to the value of the received image data, the control signals S ₀ , S _8. Outputs one of, S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ and S ₆₄ . The relationship between the input and the output of the selection control circuit SCOL is determined using a logic table.

Table 1 is a logic table of the selection control circuit SCOL. The first and sixth columns of Table 1 represent values of the d ₅ , d ₄ , d ₃ , d ₂ , d ₁ , and d ₀ bits of the image data, and the seventh and fifteenth columns of Table 1 represent the control signal S. _{The values of 0} , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ and S ₆₄ are shown, respectively. Each blank in the seventh to fifteenth columns of Table 1 indicates that the value of the control signal is zero. In addition, ti indicates that the value of the control signal is 1 when the value of the clock signal ti is 1 and the value of the control signal is 0 when the value of the clock signal ti is 0. Also Indicates that the value of the control signal is 0 when the value of the clock signal ti is 1 and the value of the control signal is 1 when the value of the clock signal ti is 0. Where i = 1, 2, 3 and 4.

Table 1

As shown in Table 1, when the value of the image data is a multiple of 8, one of the gradation voltages V ₀ , V ₈ , V ₁₆ , V ₂₄ , V ₃₂ , V ₄₀ , V ₄₈ , V _56, and V ₆₄ is the data line. Outputs On. When the value of the image data is not a multiple of 8, the pair of gray voltages V ₀ ,..., With a duty ratio of one of the clock signals t ₁ , t ₂ , t ₃ , and t ₄ . The vibration voltage oscillating between V ₆₄ is output to the data line On. The data driver 120 generates seven different vibration voltages between each adjacent gray voltages according to the logic table of Table 1. Accordingly, 64 grayscale images can be obtained using only nine grayscale voltage levels.

The following equation shows the image data d ₅ , d ₄ , d ₃ , d ₂ , d ₁ , and d ₀ shown in Table 1, clock signals t ₁ , t ₂ , t ₃ and t ₄ and control signals S ₀ , S ₈ , S Logical expression defining the relationship between ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S _56, and S ₆₄ .

S ₀ = {0} + {1} t ₁ + {2} t ₂ + {3} t ₃ + {4} t ₄ + {5} t ₃ 2+

{6} t ₂ + {7} t ₁ . … … … … … … … … … … … … … … … … … … … … … (One)

S ₈ = {1} t ₁ + {2} t ₂ + {3} t ₃ + {4} t ₄ + {5} t ₃ +

{6} t ₂ + {7} t ₁ + {8} + {9} t ₁ + {10} t ₂ + {11} t ₃ +

{12} t ₄ + {13} t ₃ + {14} t ₂ + {15} t ₁ . … … … … … … … … … … … … (2)

S ₁₆ = {9} t ₁ + {10} t ₂ + {11} t ₃ + {12} t ₄ + {13} t ₃ +

{14} t ₂ + {15} t ₁ + {16} + {17} t ₁ + {18} t ₂ +

{19} t ₃ + {20} t ₄ + {21} t ₃ + {22} t ₂ + {23} t ₁ . … … … … … … … … (3)

Similarly, control signals S ₂₄ , S ₃₂ , S ₄₀ and S ₄₈ are defined. Control signals S ₅₆ and S ₆₄ are defined as follows.

S ₅₆ = {49} t ₁ + {50} t ₂ + {51} t ₃ + {52} t ₄ +

{53} t ₃ + {54} t ₂ + {55} t ₅ + {56} + {57} t ₁ +

{58} t ₂ + {59} t ₃ + {60} t ₄ + {61} t ₃ + {62} t ₂ +

{63} t ₁ . … … … … … … … … … … … … … … … … … … … … … … … (4)

S ₆₄ = {57} t ₁ + {58} t ₂ + {59} t ₃ + {60} t ₄ +

{61} t ₃ + {62} t ₂ + {63} t ₁ . … … … … … … … … … … … … … … … … (5)

In the above formula, {i} represents a value when binary data (d ₅ , d ₄ , d ₃ , d ₂ , d ₁ , d ₀ ) is represented by the decimal system. For example, {i} = (d ₅ , d ₄ , d ₃ , d ₂ , d ₁ , d ₀ ) = (0, 0, 0, 0, 0, 1). Further, ti denotes a signal inverted from the signal ti.

Based on the above logic equations, the logic circuits shown in Figs. 14 and 15 are obtained. The selection control circuit SCOL is composed of the logic circuits shown in Figs.

The logic circuit shown in FIG. 14 generates 64 kinds of gradation selection data {0}-{64} according to the values of 6 bit image data (d ₅ , d ₄ , d ₃ , d ₂ , d ₁ , d ₀ ). do. The logic circuit shown in FIG. 15 shows control signals S ₀ , S ₈ , S ₁₆ , S ₂₄ in accordance with the gradation selection data {0}-{64} and the clock signals t ₁ , t ₂ , t ₃ , and t ₄ . , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ and S ₆₄ . For example, the case where the image data (d ₅ , d ₄ , d ₃ , d ₂ , d ₁ , d ₀ ) = (0, 0, 0, 0, 0, 1) is input to the selection control circuit SCOL will be described. do. In this case, the logic circuit shown in Fig. 14 outputs gradation selection data {1}. The logic circuit shown in FIG. 15 receives the gradation selection data {1} and alternately outputs the control signal S ₀ and the control signal S ₈ at the duty ratio of the clock signal t ₁ . As a result, the gradation voltage V ₀ and the gradation voltage V ₈ are alternately outputted to the data line On through the analog switch ASW ₀ and the analog switch ASW ₈ at the duty ratio of the clock signal t ₁ .

The actual data driver requires the same number of selection control circuits SCOL as the number of data lines. Therefore, the circuit scale of the selection control circuit SCOL has a great influence on the chip size of the integrated circuit in which the data driver is formed. When the circuit scale of the selection control circuit SCOL becomes large, the cost of the integrated circuit increases. In addition, if the number of bits of the image data is increased to realize an image with a larger number of gradations, the circuit scale of the data driver becomes larger. This increases the size of the integrated circuit, increasing the manufacturing cost.

The driving circuit of the present invention includes a pixel and a data line for applying a voltage to the pixel, and is used to drive a display device for displaying an image in multiple gradations in accordance with image data composed of a plurality of bits. The driving circuit specifies vibrations obtained by specifying one of a plurality of vibration signals having different duty ratios and inverting the specified vibration signal T and the specified vibration signal according to image data composed of bits selected from the plurality of bits. signal Vibration voltage specifying means for outputting; According to the image data consisting of bits other than the selected bit among the plurality of bits, for generating a gradation voltage specifying signal for specifying a first gradation voltage and a second gradation voltage among a plurality of gradation voltages supplied from the gradation voltage supply means. Gradation voltage specifying means: and the vibration signal T and the vibration signal And output means for outputting the first gray voltage and the second gray voltage specified by the gray voltage specifying signal to the data line.

In one embodiment of the present invention, the first gray voltage and the second gray voltage are gray voltages adjacent to each other among the plurality of gray voltages.

In another embodiment of the present invention, the plurality of vibration signals may have a duty ratio of 8: 0, 7,: 1,6: 2,5: 3,4: 4,3: 5,2: 6,1: 7. It includes a vibration signal each having.

According to another aspect of the present invention, there is provided a driving circuit for driving a display device having a pixel and a data line for applying a voltage to the pixel and displaying the image in multiple gradations according to the image data composed of a plurality of bits. do. The driving circuit includes control signal generating means for generating a plurality of control signals in accordance with the video data composed of a plurality of bits; And a corresponding one of the plurality of control signals to each of the plurality of switch means is supplied with a corresponding one of the plurality of gray voltages generated by the control signal and the gray voltage generation means, and the gray voltage supplied to the switching means. Has a plurality of switching means, which are output to a data line through a switching means in accordance with a control signal, wherein the control signal generating means has different duty ratios from each other according to image data composed of bits selected from the plurality of bits. A vibration signal obtained by specifying one of a plurality of vibration signals and inverting said specified vibration signal T and this specified vibration signal T Vibration voltage specifying means for outputting; Gradation voltage specifying means for generating a gradation voltage specifying signal for specifying a first gradation voltage and a second gradation voltage among the plurality of gradation voltages according to the image data composed of bits other than the selected bit among the plurality of bits; And a first control signal oscillating at a duty ratio substantially equal to the vibration signal T to one of the switching means supplied with the first gray voltage specified by the gray voltage specifying signal, and specified by the gray voltage specifying signal. The vibration signal to one of the switching means supplied with a second gray voltage; And output means for outputting a second control signal oscillating with a duty ratio substantially equal to.

In one embodiment of the present invention, the first gray voltage and the second gray voltage are gray voltages adjacent to each other among the plurality of gray voltages.

In another embodiment of the present invention, the plurality of vibration signals may have a duty ratio of 8: 0, 7,: 1,6: 2,5: 3,4: 4,3: 5,2: 6,1: 7. It includes a vibration signal each having.

In another embodiment of the invention said switching means is an analog switch.

According to the driving circuit of the present invention, a pair of gradation voltages is selected (specifically) from a plurality of gradation voltages, and one of the plurality of vibration signals is specified. The driving circuit outputs a voltage signal oscillating between the pair of gradation voltages specified by the vibration frequency of the specified vibration signal. Thus, a plurality of interpolation gradations can be realized between a plurality of applied gradation voltages.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the following description, a matrix type liquid crystal display device is used as an example of the display device, but the present invention can be applied to other types of display devices.

1 is a configuration diagram of a matrix liquid crystal display device. The liquid crystal display of FIG. 1 includes a display unit 100 for displaying a video image and a driving circuit 101 for driving the display unit 100. The drive circuit 101 includes a data driver 102 for providing a video signal to a display unit and a scan driver 103 for providing a scan signal to a display unit. This data driver is also called a source driver or a column driver, and the scan driver is also called a gate driver or a row driver.

The display unit 100 includes a pixel 104 of an M × N (M is a pixel in each column, N is a pixel in each row; M and N are positive integer) array and a switching element 105 connected to each pixel 104. There is).

In FIG. 1, N data lines 106 are used to connect each output terminal S (i) (i = 1, 2, ..., N) of the data driver 102 to the corresponding switching element 105. In FIG. . Similarly, M scan lines 107 are used to connect each output terminal S (j) (j = 1, 2, ..., M) of the scan driver 103 to the corresponding switching element 105. As the switching device 105, a thin film transistor (TFT) may be used, but other types of switching devices may be used. Data lines are also called source lines or hot lines. Scan lines are also called gate lines or row lines.

The scan driver 103 sequentially outputs a voltage held at a high level for a specific time from the output terminal G (j) to the corresponding scan line 107. This specific time is called one horizontal period jH (j is an integer between 1 and M). The total period obtained by summing all the horizontal periods jH (ie, 1H + 2H + 3H +… + MH), the retrace period, and the vertical synchronization period is called one vertical period.

When the voltage level output from the output terminal G (j) of the scan driver 103 to the scan line 107 is high, the switching element 105 connected to the output terminal G (j) is in the ON state. When the switching element 105 is in the ON state, the pixel 104 connected to the switching element 105 is output in accordance with the voltage output from the output terminal S (j) of the data driver 102 to the corresponding data line 106. Is charged. The voltage of this charged pixel 104 remains unchanged for about one vertical period until it is again charged by a subsequent voltage supplied from the data driver 102.

2 shows the relationship between the digital image data DA, the sampling pulse T _smp1 and the output pulse signal OE during the jth horizontal period _jH determined by the horizontal synchronization signal H _Syn1 . As can be seen in FIG. 2, the sampling pulses T _smp1 , T _smp2 ,... , T _smp1 ,… While T _smpN is sequentially applied to the data driver 102, the digital image data DA ₁ , DA ₂ ,... , DA ₁ ,.. DA _N is supplied to the data driver 102. Then, the j th output pulse OE ₁ determined by the output pulse signal OE is applied to the data driver 102. When the j th output pulse OE _J is received, a voltage is output from the output terminal S (i) of the data driver 102 to the corresponding data line 106.

3 shows the relationship between the horizontal synchronization signal H _syn , the digital image data DA, the output pulse signal OE, and the output timing of the data driver 102 and the scan driver 103 during one vertical period determined by the vertical synchronization signal V _syn . It is shown. In FIG. 3, SOURCE (j) represents the level range of the voltage output from the data driver 102 at the same timing as that of FIG. 2 in accordance with the digital image data applied during the horizontal period jH. SOURCE (j) is a hatched rectangular area and represents the level range of all voltage outputs from all output terminals S (1) to S (N) of the data driver 102. While the voltages indicated by SOURCE (j) are applied to the data line 106, the voltage output from the jth output terminal G (j) of the scan driver 103 to the jth scan line 107 is maintained at a high level. Then, all the switching elements 105 connected to the j-th scanning line 107 are turned ON. As a result, N pixels 104 respectively connected to these N switching elements 105 are charged in accordance with the voltage applied from the data driver 102 to the corresponding data line 106.

The above process is repeated M times from the first scanning line to the Mth scanning line, so that an image corresponding to one vertical period is displayed. In the case of an interlaced display device, the generated image serves as a complete display image on the display screen.

In this specification, the time interval between the _jth output pulse OE _{1 of the} output pulse OE and the (j + 1) th output pulse OE _{j + 1} is called 1 output period. This means that one output period is equal to the period indicated by SOURCE (j) in FIG. In the case of general line sequential scanning, it is better to make one output period equal to one horizontal period. The reason for this is as follows. While the data driver 102 outputs a voltage corresponding to the digital image data for one horizontal (scanning) line to the data line 106, sampling of the digital image data for the horizontal line is then performed. The maximum allowable time for outputting these voltages from the data driver 102 is equal to one horizontal period. In addition, except in a special case, the longer the output period, the more precisely the pixel can be charged. Therefore, in the above-described driving circuit, one output period is equal to one horizontal period, but according to the present invention, one output period does not necessarily need to be equal to one horizontal period.

4 shows the voltage levels applied to the pixels P (j, i) (j = 1, 2, ..., M) in accordance with these timings, in addition to the timing of the respective signals shown in FIGS.

5 is a waveform diagram of a voltage signal output from the data driver 102 to the data line 106 during one output period. In the case of a normal data driver, the voltage level of the voltage signal output to the data line 106 is constant for one output period, but the voltage output from the data driver 102 of the present embodiment to the data line 106 according to the present invention. The signals have vibrating elements that vibrate for one output period. As shown in Fig. 5, the voltage signal is a pulsed signal, and the ratio of the high level to the low level period, that is, the duty ratio n: m is selected as described below.

6 is a partial view of the data driver 102 of the drive circuit 101. As shown in FIG. The circuit 60 of FIG. 6 outputs a video signal to one data line 106 at the nth output terminal S (n). The data driver 102 has the same number of circuits 60 as the number of data lines 106 of the display portion 100. It is assumed here that the image data is composed of 6 bits (D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ ). In this hypothesis, the image data has 64 values from 0 to 63, and the signal voltage applied to each pixel has 9 gradation voltages V ₀ , V ₈ , V ₁₆ , V ₂₄ , V ₃₂ , V ₄₀ , V ₄₈ , V _56, one of the V _64, and _{V 0, V 8, V 16} , V 24, V 32, V 40, V 48, V 56, a voltage generated by the interpolation gray-scale voltage pair is selected from V _64.

The circuit 60 includes a sampling flip-flop M _SMP for sampling, a holding flip-flop M _H for holding, a selection control circuit SCOL, and an analog switch ASW ₀ -ASW ₈ . Analog switches ASW ₀ -ASW _8, respectively 9, the gray scale voltages _{V 0, V 8, V 16} , V 24, V 32, V 40, V 48, V 56, V 64 is the corresponding voltage is supplied in. Each level of these gradation voltages V ₀ , -V ₆₄ is different from each other. The seven control signals t ₁ -t ₇ are supplied to the selection control circuit SCOL. The duty ratios of the vibration voltages t ₁ -t ₇ are different from each other.

Sampling flip-flop M _SMP and holding flip-flop M _H can be used as D flip-flops, but other types of circuitry can be used.

Next, the operation of the circuit 60 will be described with reference to FIG. In the rising _portion of the sampling pulse M _SMPn corresponding to the nth pixel, the sampling flip-flop M _{SMP takes and} holds the image data D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ . When the sampling of this video data is completed for one horizontal period, the output pulse signal OE is applied to the holding flip-flop M _H. When the output pulse signal OE is applied, the image data held in the sampling flip-flop M _SMP is supplied to the holding flip-flop M _H and output to the selection control circuit SCOL. The selection control circuit SCOL receives the image data and generates a plurality of control signals according to the value of the image data. These control signals are used to switch the ON / OFF state of each analog switch ASW _{0 to} ASW ₈ . The image data input to the selection control circuit SCOL is represented by D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , and the control signals output from the selection control circuit SCOL are S ₀ , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ , S ₆₄ .

Table 2 is a logical table of the lower 3 bits d ₂ , d ₁ , and d ₀ of 6-bit image data. Columns 1 to 3 of Table 2 indicate values of bits d ₂ , d ₁ , and d ₀ of these image data, and columns 4 to 11 indicate that vibration signals are specified as one of t ₀ -t ₇ . In columns 4 to 11 of Table 2, vibration signals indicated by one value are specified. For example, when (d ₂ , d ₁ , d ₀ ) = (0, 0, 0), the vibration signal t ₀ is specified. In this embodiment, each of the vibration signals t ₀ -t ₇ is a clock signal having a duty ratio of 8: 0, 7: 1, 6: 2, 5: 3. 4: 4, 3: 5, 2: 6, 1: 7 to be. If the duty ratio of the vibration signal is k: 0 or 0: k (k is a natural number), it is assumed that the level of the vibration signal is fixed. The vibration signals t ₅ , t ₆ and t ₇ are signals obtained by inverting the vibration signals t ₃ , t ₂ and t ₁ .

TABLE 2

From this logical table, the following equation is obtained.

T = (0) t ₀ + (1) t ₁ + (2) t ₂ + (3) t ₃ + (4) t ₄ + (5) t ₅ + (6) t ₆ + (7) t ₇ . … … … … … … … … (6)

In this equation, (i) is the binary representation of the binary data (d ₂ , d ₁ , d ₀ ). That is, (0) = (d ₂ , d ₁ , d ₀ ) = (0, 0, 0), (1) = (d ₂ , d ₁ , d ₀ ) = (0, 0, 1), (2 ) = (d ₂ , d ₁ , d ₀ ) = (0, 1, 0), (3) = (d ₂ , d ₁ , d ₀ ) = (0, 1, 1), (4) = (d ₂ , d ₁ , d ₀ ) = (1, 0, 0), (5) = (d ₂ , d ₁ , d ₀ ) = (1, 0, 1), (6) = (d ₂ , d ₁ , d ₀ ) = (1, 1, 0), (7) = (d ₂ , d ₁ , d ₀ ) = (1, 1, 1).

If the vibration signal t ₀ remains at 1, equation (6) is represented by the following equation.

T = (0) + (1) t ₁ + (2) t ₂ + (3) t ₃ + (4) t ₄ + (5) t ₅ + (6) t ₆ + (7) t ₇ . … … … … … … … … (7)

Table 3 shows the top 3 bits of 6-bit image data between d ₅ , d ₄ , d ₃ and the corresponding signals S ₀ , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ , and S ₆₄ . Logical table showing the relationship between In Table 3, the variable T means the signal T obtained from equations (6) and (7). Denotes an inverted signal obtained by inverting the signal T.

TABLE 3

In the above logical table, the following equation is obtained.

S ₀ = [0] T... … … … … … … … … … … … … … … … … … … … … … … … … (8)

S ₈ = [0] T + [8] T... … … … … … … … … … … … … … … … … … … … … … (9)

S ₁₆ = [8] T + [16] T... … … … … … … … … … … … … … … … … … … … … 10

S ₂₄ = [16] T + [24] T... … … … … … … … … … … … … … … … … … … … (11)

S ₃₂ = [24] T + [32] T. … … … … … … … … … … … … … … … … … … … (12)

S ₄₀ = [32] T + [40] T... … … … … … … … … … … … … … … … … … … … (13)

S ₄₈ = [40] T + [48] T. … … … … … … … … … … … … … … … … … … … (14)

S ₅₆ = [48] T + [56] T. … … … … … … … … … … … … … … … … … … … (15)

S ₆₄ = [56] T. … … … … … … … … … … … … … … … … … … … … … … (16)

In the above equation, [i] is the value of binary data (d ₅ , d ₄ , d ₃ ), i = (8 × j), and j is binary data (d ₅ , d ₄ , d ₃ ) Is expressed in decimal notation. Moreover, [8] = (d ₅ , d ₄ , d ₃ ) = (0, 0, 0). In addition, T is an inverted signal of signal T.

According to the above logic equations, the logic circuits 70, 80, 90, and 95 shown in Figs. 7 to 10 are obtained. The selection control circuit SCOL is composed of, for example, logic circuits 70, 80, 90, 95 shown in Figs.

The logic circuit 70 shown in FIG. 7 is a vibration signal specifying signal (0)-that specifies one of a plurality of vibration signals t ₀ -t ₇ according to the lower 3 bits d ₂ , d ₁ , d ₀ of the video signal. Optionally output (7). Specifically, that is, the video data d _2, d _1, d ₀ and the inverting circuit INV _0, by inverting the video data d _2, d _1, d ₀ to INV ₁ obtained inverted signals constituting a binary 0-7 They are input to the AND circuit AG ₀ -AG ₇ in combination. These vibration signal specific signals (0)-(7) are obtained as the output of the AND circuit AG ₀ -AG ₇ .

The logic circuit 80 shown in FIG. 8 specifies one of the plurality of vibration signals t ₀ -t ₇ according to the vibration signal specifying signals, and the vibration signal specified by the specific vibration signal T and the inversion circuit INV ₃ . Reverse drive signal obtained by inverting T Create Specifically, the vibration signal specifying signals (1)-(7) and the vibration signals t ₁ -t ₇ are respectively input to the AND circuits BG ₁ -BG ₇ as shown in FIG. The vibration signal specifying signal (0) and the outputs of the AND circuits BG ₁ -BG ₇ are supplied to the OR circuit CG. Vibration signal T and reverse vibration signal Is obtained as the output of the OR circuit CG.

The logic circuit 90 shown in FIG. 9 is a gradation voltage specification signal [0], [which specifies gradation voltage pairs among gradation voltages according to the upper three bits d ₅ , d ₄ , and d ₃ of the image data. 8], [16], [24], [32], [40], [48], and [56] are selectively output. Specifically, the inverted signals obtained by inverting the image data d ₅ , d ₄ , d ₃ and the data d ₅ , d ₄ , d ₃ with the inverting circuits INV ₄ -INV ₆ constitute 0-7 in binary. Input as AND circuit DG ₀ -DG ₇ as a combination. As the outputs of the AND circuits DG ₀ -DG ₇ , the gradation voltage specific signals [0], [8], [16], [24], [32], [40], [48], and [56] are obtained. .

The logic circuit 95 shown in FIG. 10 has vibrations with gray scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56]. Signal T and reverse vibration signal The control signals S _0- S ₆₄ are selectively outputted accordingly. Specifically, the gradation voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56], and the vibration signal T are the AND circuits EG ₀ and EG. ₂ , EG ₄ , EG ₆ , EG ₈ , EG ₁₀ , EG ₁₂ , EG _14, respectively. Gradient voltage specific signals [0], [8], [16], [24], [32], [40], [48], [56], and reverse vibration signal Are input to the AND circuits EG ₁ , EG ₃ , EG ₅ , EG ₇ , EG ₉ , EG ₁₁ , EG ₁₃ , and EG _15, respectively. The outputs of AND circuit EG ₁ and EG ₂ are connected to OR circuit FG ₁ , respectively. The outputs of AND circuit EG ₃ and EG ₄ are connected to OR circuit FG ₂ , respectively. The outputs of AND circuit EG ₅ and EG ₆ are connected to OR circuit FG ₃ , respectively. The outputs of AND circuit EG ₇ and EG ₈ are connected to OR circuit FG ₄ , respectively. The outputs of AND circuit EG ₉ and EG ₁₀ are connected to OR circuit FG ₅ , respectively. The outputs of AND circuit EG ₁₁ and EG ₁₂ are connected to OR circuit FG ₆ , respectively. The outputs of AND circuit EG ₁₃ and EG ₁₄ are connected to OR circuit FG ₇ respectively. AND circuit EG ₀ and OR circuit FG _1- FG ₇ and AND circuit EG ₁₅ outputs control signals S ₀ , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ , S ₆₄ Become.

These control signals S ₀ , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ and S ₆₄ are supplied to the corresponding analog switches ASW _{0 to} ASW ₈ . The control signals S ₀ , S ₈ , S ₁₆ , S ₂₄ , S ₃₂ , S ₄₀ , S ₄₈ , S ₅₆ , and S ₆₄ each have a high or low level value. For example, if the control signal is at the high level, the corresponding analog switch is adjusted to be in the ON state, and if the control signal is at the low level, the corresponding analog switch is adjusted to be in the OFF state. Otherwise, the relationship between the level of the control signal and the ON / OFF state of the analog switch may be set in reverse.

As described above, when the image data is composed of a plurality of bits, the waveform of the vibration voltage is specified according to the image data composed of at least one bit selected from these bits. Then, a pair of gray voltages is specified from a plurality of gray voltages in accordance with video data composed of bits other than the selected bits. As a result, a voltage signal of a level suitable for all values of the image data can be output. The vibration voltage is used to obtain a plurality of interpolation voltages between the pair of gray voltages specified among the plurality of gray voltages.

When the value of the video data is a multiple of 8, only one gray voltage can be selected. In this case, the duty ratio n: m of the vibration signal or the control signal is k: 0 or 0: k (k is a natural number).

On the other hand, whether the value of the image data is a multiple of 8 or not, a specific gray voltage pair among the plurality of gray voltages may be alternately output.

As described above, the configuration of the selection control circuit SCOL of the present invention consisting of the logic circuits 70, 80, 90, and 95 shown in Figs. 7 to 10 is composed of the logic circuits shown in Figs. Compared with the conventional 12 degree selection control circuit SCOL, it is simple. According to the present invention, an image can be displayed with multiple gray scales, such as 64 gray scales, using a drive circuit having a simple configuration. For example, only nine kinds of gradation voltages are required to realize a display image having 64 gradations.

The actual data driver requires the same number of selection control circuits SCOL as the data lines. Therefore, the circuit size of the selection control circuit SCOL has a great influence on the chip size of the integrated circuit (LSI) for installing the data driver. According to the present invention, the size of the integrated circuit including the selection control circuit SCOL can be significantly reduced. As a result, the production cost of the integrated circuit can be reduced. Increasing the number of bits of the image data to realize an image having a large number of gray scales is quite useful because the circuit size of the data driver is reduced by that amount. Therefore, the size and manufacturing cost of the integrated circuit can be further reduced.

According to the present invention, since one or more interpolation voltages can be obtained from a voltage source supplied from a given voltage source, the number of voltage sources can be considerably reduced as compared with a conventional driving circuit requiring many voltage sources. By arranging a voltage source outside the driving circuit, the number of input terminals of the driving circuit can be reduced. If the driving circuit is composed of LSIs, the number of LSI input terminals can be reduced. According to the present invention, it is possible to realize a driving LSI displaying an image having a plurality of gradations which cannot be realized in the prior art due to the increase in the number of terminals. The present invention has the following effects: (1) The manufacturing cost of the display device and the driving circuit is greatly reduced; (2) it is easy to produce a multi-gradation driving circuit which is practically impossible to produce due to chip size or LSI installation; (3) Power consumption is reduced because a large number of voltage sources are unnecessary.

Claims (7)

A driving circuit for driving a display device having a pixel and a data line for applying a voltage to the pixel, and displaying an image in multiple gradations according to image data composed of a plurality of bits, comprising a bit selected from the plurality of bits. A vibration signal obtained by specifying one of a plurality of vibration signals having different duty ratios according to the image data to be obtained, and inverting the specified vibration signal T and the specified vibration signal. And a first gray voltage and a second gray voltage among the plurality of gray voltages supplied from the gray voltage supply means according to the vibration voltage specifying means for outputting a signal. Gray voltage specifying means for generating a gray voltage specifying signal and the vibration signal T and the vibration signal And output means for outputting the first gray voltage and the second gray voltage specified by the gray voltage specifying signal to the data line. The driving circuit according to claim 1, wherein the first gray voltage and the second gray voltage are gray voltages adjacent to each other among the plurality of gray voltages. The vibration signal of claim 1, wherein the plurality of vibration signals have a duty ratio of 8: 0, 7: 1, 6: 2, 5: 3, 4: 4, 3: 5, 2: 6, and 1: 7 respectively. A drive circuit comprising a signal. A driving circuit for driving a display device that includes a pixel and a data line for applying a voltage to the pixel, and displays an image in multiple gradations in accordance with the image data composed of a plurality of bits. Accordingly, control signal generating means for generating a plurality of control signals; And a corresponding one of the plurality of control signals among the plurality of control signals and a corresponding one of the plurality of gray voltages generated by the gray voltage generation means are supplied to each of the plurality of switch means, and the gray level voltage supplied to the switching means. Has a plurality of switching means, which are output to a data line through a switching means in accordance with a control signal, wherein the control signal generating means has different duty ratios from each other according to image data composed of bits selected from the plurality of bits. A vibration signal obtained by specifying one of a plurality of vibration signals and inverting said specified vibration signal T and this specified vibration signal T A gradation voltage specifying signal for specifying a first gradation voltage and a second gradation voltage among the plurality of gradation voltages according to the vibration voltage specifying means for outputting a signal; Outputting a first control signal oscillating at a duty ratio substantially equal to the vibration signal T to one of the switching means supplied with the gray scale voltage specifying means and the first gray voltage specified by the gray voltage specifying signal, The vibration signal to one of the switching means supplied with the second gradation voltage specified by the specific signal. And output means for outputting a second control signal oscillating with a duty ratio approximately equal to that of the second. 5. The driving circuit of claim 4, wherein the first gray voltage and the second gray voltage are adjacent to each other among the plurality of gray voltages. 6. The vibration signal of claim 4, wherein the plurality of vibration signals have a duty ratio of 8: 0, 7: 1, 6: 2, 5: 3, 4: 4, 3: 5, 2: 6, 1: 7, respectively. A drive circuit comprising a signal. 5. The driving circuit according to claim 4, wherein the switching means is an analog switch.