JP2007010871A - Display signal processing apparatus and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a driving period of a pixel without requiring enhancement of a driving capability. <P>SOLUTION: A display signal processing apparatus includes a gradation reference voltage generation circuit 7 for generating a plurality of gradation reference voltages from a plurality of voltage output ends V0 to V9 and a signal conversion circuit 23 for converting a display signal to a pixel voltage by selectively using a prescribed number of gradation voltages obtained from resistance groups r0 to r8 which are connected in series so as to divide inter-terminal voltages of the plurality of voltage output ends V0 to V9. The gradation reference voltage generation circuit 7 includes output control parts VC1 to VC6 which temporarily set the plurality of gradation reference voltages to intermediate voltage values for precharge, which are mutually identical in a pixel voltage range corresponding to a maximum gradation difference of the display signal, and then set the plurality of gradation reference voltages to voltage values for display, which are mutually different in the pixel voltage range, in every conversion operation of the signal conversion circuit 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display signal processing device that converts a display signal into a pixel voltage and a liquid crystal display device having the display signal processing device.

  A flat display device typified by a liquid crystal display device is widely used as a display device for a personal computer, an information portable terminal, a television receiver, a car navigation system, or the like.

  A liquid crystal display device generally includes a display panel including a matrix array of a plurality of liquid crystal pixels, and a drive circuit that drives the display panel. A typical display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate. The array substrate has a plurality of pixel electrodes arranged in a matrix, and the counter substrate has a common electrode facing the pixel electrodes. The pixel electrode and the common electrode constitute a liquid crystal pixel together with the pixel region of the liquid crystal layer disposed between these electrodes, and the liquid crystal molecular arrangement in the pixel region is controlled by an electric field between the pixel electrode and the common electrode. In the driving circuit, for example, digital display signals for pixels in each row are converted into pixel voltages using a plurality of gradation reference voltages, and are output to the display panel. The pixel voltage is a voltage applied to the pixel electrode with reference to the potential of the common electrode. In order to avoid deterioration of the display panel due to uneven distribution of liquid crystal molecules, for example, as shown in FIG. 5, every horizontal scanning period (1H). The polarity is inverted with respect to the potential of the common electrode and output from the source driver. In FIG. 5, CKV represents a vertical clock signal CKV that is a pulse generated in one vertical scanning period with one horizontal scanning period as a cycle, and STB is generated every horizontal scanning period (1H) in synchronization with the vertical clock signal CKV. Strobe signal.

A conventional gradation reference voltage generation circuit is formed of, for example, a ladder resistor in which a plurality of resistors are connected in series between a pair of power supply terminals, and a plurality of gradation reference voltages are output by dividing the voltage between the power supply terminals ( For example, see Patent Document 1).
JP 2003-228332 A

  In recent years, high definition of liquid crystal display devices is required, and the number of pixels tends to increase. If the driving capability of the driving circuit is constant, it is necessary to shorten the driving time of the pixels in each row in order to drive all the pixels corresponding to the display signal within one vertical scanning period. The pixel voltage of the pixels for one line (line) changes within this drive time, and the gradation of these pixels is changed, for example, from the maximum value for white display to the minimum value for black display, or from the minimum value to the maximum value. It must be possible to change. However, if this drive time is too short for the drive capability of the drive circuit, it will be difficult to complete the transition of the pixel voltage within this drive time.

  The present invention has been made in view of such problems, and provides a display signal processing device and a liquid crystal display device capable of shortening the pixel driving period without requiring an increase in driving capability. is there.

  According to the present invention, a gradation reference voltage generation circuit that generates a plurality of gradation reference voltages from a plurality of voltage output terminals, and a group of resistors connected in series so as to divide voltages between terminals of the plurality of voltage output terminals And a signal conversion circuit that selectively converts a display signal into a pixel voltage by selectively using a predetermined number of gradation voltages obtained from the gradation reference voltage generation circuit, wherein the gradation reference voltage generation circuit has a plurality of gradation references for each conversion operation of the signal conversion circuit. The voltage is temporarily set to a precharge intermediate voltage value that is the same in the pixel voltage range corresponding to the maximum gradation difference of the display signal, and then a plurality of gradation reference voltages are displayed differently in the pixel voltage range. A display signal processing device including an output control unit for setting a voltage value for operation is provided.

  Further, according to the present invention, a plurality of display pixels arranged in a substantially matrix shape, a plurality of gate lines arranged along a row of the plurality of display pixels, and a plurality of rows arranged along a column of the plurality of display pixels. A source line, and a plurality of pixel switching elements disposed near the intersection of the plurality of gate lines and the plurality of source lines and electrically connecting the corresponding display pixel to the corresponding source line while each corresponding gate line is driven A liquid crystal display panel, a gate driver circuit that sequentially drives a plurality of gate lines, and a source driver circuit that drives a plurality of source lines in response to display signals for one row of display pixels. Obtained from a plurality of voltage output terminals and a resistor group connected in series so as to divide the voltage across the terminals of the plurality of voltage output terminals. And a signal conversion circuit that selectively uses a predetermined number of gradation voltages to convert a display signal into a pixel voltage, and the gradation reference voltage generation circuit generates a plurality of gradation reference voltages for each conversion operation of the signal conversion circuit. Temporarily set an intermediate voltage value for precharging that is the same in the pixel voltage range corresponding to the maximum gray level difference of the display signal, and then a plurality of gray scale reference voltages that are different from each other in the pixel voltage range A display signal processing device including an output control unit to set the two adjacent gate lines together in a precharge period in which the output control unit sets a plurality of gradation reference voltages to intermediate voltage values for precharging. A liquid crystal display device configured to be driven is provided.

  In these display signal processing devices and liquid crystal display devices, the output control unit temporarily sets a plurality of gradation reference voltages to precharge intermediate voltage values that are the same in the pixel voltage range for each conversion operation of the signal conversion circuit. . In this state, no voltage difference is generated between the voltage output terminals of the gradation reference voltage generation circuit. Therefore, the signal conversion circuit can select any of the gradation voltages obtained from the resistor group as the pixel voltage. A pixel voltage having an intermediate charging voltage value is output. When the load capacitance at the pixel voltage output terminal of the signal conversion circuit is precharged by this pixel voltage, the pixel voltage transitions to a voltage value reflecting the display signal in a shorter time. Therefore, it is possible to shorten the pixel driving period without requiring an increase in driving capability.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 schematically shows a circuit configuration of the liquid crystal display device 1. The liquid crystal display device 1 includes a display panel DP having a plurality of liquid crystal pixels PX, and a control unit CNT that controls the display panel DP. The display panel DP has a structure in which the liquid crystal layer 4 is sandwiched between the array substrate 2 and the counter substrate 3.

  The array substrate 2 includes, for example, a plurality of pixel electrodes PE arranged in a matrix on a transparent insulating substrate such as glass, a plurality of gate lines Y (Y1 to Ym) arranged along a row of the plurality of pixel electrodes PE, A plurality of source lines X (X1 to Xn) disposed along a column of the plurality of pixel electrodes PE, a pixel switching element W disposed in the vicinity of the intersection position of the gate lines Y and the source lines X, and a plurality of gate lines It has a gate driver 10 that sequentially drives Y, and a source driver 20 that drives a plurality of source lines X while each gate line Y is driven. Each pixel switching element W is made of, for example, a polysilicon thin film transistor. In this case, the gate of the thin film transistor is connected to one gate line Y, and the source and drain paths are connected between one source line X and one pixel electrode PE, respectively. The gate driver 10 is configured using a polysilicon thin film transistor that is formed simultaneously in the same process as the pixel switching element W. The source driver 20 is an integrated circuit (IC) chip mounted on the array substrate 2 by COG (Chip On Glass) technology.

  The counter substrate 3 includes a color filter (not shown) disposed on a transparent insulating substrate such as glass, and a common electrode CE disposed on the color filter so as to face the plurality of pixel electrodes PE. Each pixel electrode PE and common electrode CE is made of a transparent electrode material such as ITO, for example, and is arranged between the pixel electrode PE and common electrode CE and is controlled by a liquid crystal molecular arrangement corresponding to the electric field from these electrodes PE and CE. The liquid crystal pixel PX is configured together with the four pixel regions. All the pixels PX have an auxiliary capacitor Cs. These auxiliary capacitances Cs are obtained by electrically connecting a plurality of auxiliary capacitance lines that are capacitively coupled to the plurality of rows of pixel electrodes PE on the array substrate 2 side to the common electrode CE.

  The control unit CNT includes a controller 5, a common voltage generation circuit 6, and a gradation reference voltage generation circuit 7. The controller 5 controls the common voltage generation circuit 6, the gradation reference voltage generation circuit 7, the gate driver 10, and the source driver 20 in order to display the externally supplied digital video signal VIDEO as an image on the display panel DP. The common voltage generation circuit 6 generates a common voltage Vcom for the common electrode CE on the counter substrate 3. The gradation reference voltage generation circuit 7 generates a plurality of gradation reference voltages VREF used for converting, for example, a 6-bit display signal DATA obtained from the video signal VIDEO for each pixel PX into a pixel voltage. The pixel voltage is a voltage applied to the pixel electrode PE with reference to the potential of the common electrode CE.

  The controller 5 controls the control signal CTY for sequentially selecting a plurality of gate lines Y every one vertical scanning period and one row (line) of pixels PX included in the video signal VIDEO every one horizontal scanning period (1H). A control signal CTX for assigning the display signal DATA to the plurality of source lines X is generated. The control signal CTY includes a vertical start signal STV that is a pulse generated every one vertical scanning period (1V) and a vertical clock signal CKV that is a pulse generated for the number of gate lines in one vertical scanning period. Here, the control signal CTX is a horizontal start signal STH which is a pulse generated every horizontal scanning period (1H), and a horizontal clock signal CKH which is a pulse generated by the number of source lines in each horizontal scanning period. A strobe which is a pulse generated with a predetermined time delay from the start signal STH every one horizontal scanning period (1H) in order to convert the display signal DATA to the pixels in parallel to a pixel voltage and output it to the source lines X1 to Xn. The signal STB includes a polarity signal POL for inverting the polarity of the pixel voltage every horizontal scanning period and every vertical scanning period. The control signal CTY is supplied from the controller 5 to the gate driver 10, and the control signal CTX is supplied from the controller 5 to the source driver 20 together with the display signal DATA.

  The gate driver 10 sequentially selects a plurality of gate lines Y under the control of the control signal CTY, and supplies a scanning signal for making the pixel switching element W conductive to the selection gate line Y. However, the gate driver 10 is configured to temporarily select two adjacent gate lines Y1, Y2, Y2, Y3, Y3, Y4... Together after the start of each horizontal scanning period.

  FIG. 2 schematically shows the configuration of the source driver 20 shown in FIG. The source driver 20 shifts the horizontal start signal STH in synchronization with the horizontal clock signal CKH, and controls the shift register 21 for controlling the timing of serial-to-parallel conversion of the digital video signal VIDEO. A sampling and load latch 22 that sequentially latches the display signal DATA for PX and outputs it in parallel, a digital / analog (D / A) conversion circuit 23 that converts the display signal DATA into an analog pixel voltage, and D / A conversion An output buffer circuit 24 that outputs an analog pixel voltage obtained from the circuit 23 to the source lines X1 to Xn is included. The D / A conversion circuit 23 is configured to refer to a plurality of gradation reference voltages VREF generated from the gradation reference voltage generation circuit 7.

  As shown in FIG. 3, the gradation reference voltage generating circuit 7 includes, for example, six voltage switching units VC1 to VC6, variable voltage generating units VG1 to VG6 controlled by these voltage switching units VC1 to VC6, and these variable voltages. A plurality of resistors R0 to R8 connected in series so as to divide the voltage between the output ends (output channels) CH6 to CH1 of the generating units VG1 to VG6.

  The voltage switching units VC1 to VC6 are a register RG1 for storing display numerical data, a register RG2 for storing precharge numerical data, and display numerical data and precharge numerical values for controlling the variable voltage generating units VG1 to VG6. A changeover switch S for selectively outputting one of the data is included. The display numerical data and the precharge numerical data are supplied from the controller 5 to the registers RG1 and RG2 of the plurality of voltage switching units 33 when the power is turned on. The changeover switch S of the voltage switching units VC1 to VC6 outputs the precharge numerical data in a predetermined precharge period in synchronization with the strobe signal STB in each horizontal scanning period, and outputs the display numerical data after the precharge period has elapsed. Control is performed by the controller 5 as described above. When one horizontal scanning period is 31.7 μs, the precharge period is about 8 μs. The display numerical data and the precharge numerical data are about 8 to 10 bits, and have a sufficiently high resolution with respect to the 6-bit display signal DATA.

  Each of variable voltage generators VG1 to VG6 includes a D / A converter 30 and an output buffer 31. The D / A converters 30 of the variable voltage generators VG1 to VG6 convert the numerical data output from the voltage switching units VC1 to VC6 into output voltages, respectively, and the output buffer 31 outputs this output voltage to the output terminals CH6 to CH1. To do.

  The plurality of resistors R0 to R8 divide the voltage between the output terminals CH6 to CH1 of the variable voltage generators VG1 to VG6 to obtain a plurality of gradation reference voltages VREF and to electrically connect the voltage output terminals of these gradation reference voltages VREF. Used for interconnection. In this embodiment, the gradation reference voltage VREF is, for example, gradation reference voltages V0 to V9 output from ten voltage output terminals. These gradation reference voltages V0 to V9 are set to be relatively high levels toward the gradation reference voltage V0 and relatively low levels toward the gradation reference voltage V9.

  The D / A conversion circuit 23 of the source driver 20 includes, for example, input resistors connected between the plurality of D / A conversion units 23 ′ and the voltage output terminals of the gradation reference voltage generation circuit 7 as shown in FIGS. It is composed of groups r0 to r8. The input resistance groups r0 to r8 are provided in common to the plurality of D / A converters 23 ′, and a predetermined number of gradation voltages obtained by dividing the voltage between the voltage output terminals are supplied to the plurality of D / A converters. To 23 '.

  Each D / A converter 23 'selects one of a predetermined number of gradation voltages corresponding to the digital display signal DATA output from the sampling & load latch 22, and uses this as an analog pixel voltage to output buffer circuit 24. Output to. The output buffer circuit 24 includes a plurality of buffer amplifiers 24 ′ that output analog pixel voltages from the plurality of D / A converters 23 ′ to the source lines X 1, X 2, X 3,.

  The above-described output switching units VC1 to VC6 have the same gradation reference voltages V0 to V9 in the pixel voltage range corresponding to the maximum gradation difference of the display signal for each conversion operation of the D / A conversion circuit 23. An output control unit is configured to temporarily set the voltage value and then set the gradation reference voltages V0 to V9 to different display voltage values in this pixel voltage range. The precharge intermediate voltage value is preferably approximately ½ of the pixel voltage range. Further, the D / A conversion circuit 23 and the output buffer circuit 24 have a predetermined number of levels obtained from the input resistance groups r0 to r8 connected in series so as to divide the voltage between the voltage output terminals of the gradation reference voltage generation circuit 7. A signal conversion circuit is configured to convert display signals DATA for one line into pixel voltages by selectively using the regulated voltage and output these pixel voltages to the source lines X1 to Xn.

  The pixel voltages on the source lines X1 to Xn are respectively supplied to the corresponding pixel electrodes PE via the pixel switching elements W for one line driven by the scanning signal. The common voltage Vcom is output from the common voltage generation circuit 6 to the common electrode CE in synchronization with the output timing of the pixel voltage. The common voltage generation circuit 6 is configured by using a D / A converter or the like that generates an output voltage corresponding to numerical data of about 8 to 10 bits set by the controller 5. For example, voltages of 0 V and 5.8 V are generated. Alternately output every horizontal scanning period. Therefore, on the source driver 20 side, each D / A converter 23 'reverses the polarity of the pixel voltage with reference to the center level of the common voltage Vcom. When the liquid crystal applied voltage is maximized, the pixel voltage is set to 5.8 V with respect to the common voltage Vcom of 0 V, and is set to 0 V with respect to the common voltage Vcom of 5.8 V. Incidentally, even if the pixel voltage is output from the source driver 20 at 5.8V, it is reduced to, for example, about 4.8V due to the field through voltage caused by the parasitic capacitance of the pixel switching element W, and is held in the pixel electrode PE. become. For this reason, the amplitude and center level of the common voltage Vcom output from the common voltage generation circuit 6 are adjusted in advance according to the pixel voltage actually held in the pixel electrode PE. The liquid crystal applied voltage of all the pixels PX is further inverted every frame (one vertical scanning period).

  In this liquid crystal display device 1, the gate driver 10 sequentially outputs scanning signals to the gate lines Y1, Y2, Y3,. Further, the scanning signal is also output to the gate lines Y2, Y3, Y4,... Following the gate lines Y1, Y2, Y3,... Only during the precharge period immediately after the start of each horizontal scanning period. That is, in the precharge period immediately after the start of each horizontal scanning period, the two gate lines Y1, Y2, Y2, Y3, Y3, Y4,... Are driven together.

  For example, when the gate lines Y1 and Y2 are driven together in the precharge period, the pixel switching elements W for two lines are simultaneously turned on, and the source lines X1, X2, X3,. The corresponding pixel electrode PE in one line and the corresponding pixel electrode PE in the second line are electrically connected. In the gradation reference voltage generation circuit 7, the changeover switches S of the voltage switching units VC1 to VC6 output the precharge numerical data to the variable voltage generation units VG1 to VG6 during the precharge period, and the variable voltage generation units VG1 to VG Converts precharge numerical data into output voltage. As a result, the plurality of gradation reference voltages V0 to V9 are temporarily set to the same precharge intermediate voltage value in the pixel voltage range corresponding to the maximum gradation difference of the display signal DATA. That is, no voltage difference is generated between the voltage output terminals of the gradation reference voltage generation circuit 7. Therefore, a predetermined number of gradation voltages obtained from the input resistance groups r0 to r8 connected between these voltage output terminals are all set to this intermediate voltage value and output to the plurality of D / A converters 23 ′. . When each D / A conversion unit 23 'selects one of these gradation voltages corresponding to the display signal DATA and outputs it as a pixel voltage from the pixel voltage output terminal, the source lines X1 to Xn are substantially connected to the display signal. Precharged to an intermediate voltage pixel voltage that does not reflect DATA.

  When the above-described precharge period elapses, the scanning signal is continuously output to only one gate line Y1, and is not output to the next gate line Y2. As a result, when the gate line Y1 is driven singly and only the pixel switching elements W for one line are made conductive, the source lines X1, X2, X3,. Electrically connected to PE. In the gradation reference voltage generation circuit 7, the changeover switches S of the voltage switching units VC1 to VC6 output display numerical data to the variable voltage generation units VG1 to VG6 after the precharge period has elapsed, and the variable voltage generation units VG1 to VG Convert numeric data for display to output voltage. As a result, the plurality of gradation reference voltages V0 to V9 are set to different display voltage values in the pixel voltage range corresponding to the maximum gradation difference of the display signal DATA. As a result, a voltage difference is generated between the voltage output terminals of the gradation reference voltage generation circuit 7, so that a predetermined number of gradation voltages obtained from the input resistance groups r0 to r8 connected between these voltage output terminals are different from each other. Is set to a voltage value for use and output to a plurality of D / A converters 23 '. When each D / A converter 23 'selects one of these gradation voltages corresponding to the display signal DATA and outputs it as a pixel voltage from the pixel voltage output terminal, the pixel voltages on the source lines X1 to Xn are displayed. Transitions to a voltage value reflecting the signal DATA.

  In the above-described embodiment, the combination of the gradation voltage generation circuit 7 and the source driver 20 constitutes a display signal processing device having excellent writing capability, and the source line X and the pixel are controlled by arbitrarily controlling the voltage value and time of the pixel voltage. PX can be precharged. Specifically, the output control unit (voltage switching units VC1 to VC6) sets the gradation reference voltages V0 to V9 at the maximum of the display signal DATA for each conversion operation of the signal conversion circuit (D / A conversion circuit 23 and output buffer 24). The precharge intermediate voltage values are temporarily set to be the same in the pixel voltage range corresponding to the gradation difference. In this state, no voltage difference is generated between the voltage output terminals of the gradation reference voltages V0 to V9. Therefore, the signal conversion circuit selects any gradation voltage obtained from the input resistance groups r0 to r8 as the pixel voltage. Also, the pixel voltage having the above intermediate voltage value is output. When the load capacitance (source lines X1 to Xn) at the pixel voltage output terminal of the signal conversion circuit is precharged by the intermediate voltage pixel voltage, the pixel voltage transitions to a voltage value reflecting the display signal DATA in a shorter time. To do. Therefore, it is possible to shorten the pixel driving period without requiring an increase in driving capability.

  In particular, as described above, when the drive type is such that the polarities of the liquid crystal applied voltages of all the pixels PX are inverted for every line and every frame, the buffer output of the source driver 20 is applied to the pixel electrode PE of each pixel PX. In order to set the pixel voltage, a very large transition must be made. For example, when an overall black (or white) image is continuously displayed in a plurality of frames, the buffer output of the source driver 20 has a timing as shown in FIG. 4 with respect to the strobe signal STB and the vertical clock signal CKV. Transition with. Although the D / A conversion start timing based on the display signal DATA may be after the source line X is set to the intermediate voltage value, the buffer output of the source driver 20 is reversed for the frame i and the next frame i + 1 as described above. In the case of polarity, even if the start timing of D / A conversion based on the display signal DATA is restricted before setting the source line X to the intermediate voltage value due to the specifications of the existing source driver IC, the following reason It is possible to shorten the transition time from 1 to the voltage value reflecting the display signal DATA. Here, for example, attention is paid to the pair of pixels PXk-1, PXk corresponding to the gate lines Yk-1, Yk and the source line X1. The pixels PXk-1 and PXk are electrically connected to the source line X1 through a pair of pixel switching elements Wk-1 and Wk that are turned on in the precharge period, respectively, and charge is equally distributed between the pixels PXk-1 and PXk. Thus, the same amount of charge is shared by the pair of pixels PXk-1 and PXk. When the source line X1 is precharged to an intermediate voltage value that is approximately ½ of the pixel voltage range by the buffer output of the source driver 20, the potential transition of the source line X1 is promoted in this precharge. Next, paying attention to the pair of pixels PXk and PXk + 1 corresponding to the gate lines Yk and Yk + 1 and the source line X1, the pixels PXk-1 and PXk are turned on in a precharge period after one horizontal scanning period (1H). The source line X1 is electrically connected via the switching elements Wk and Wk + 1, respectively, and the charge is equally distributed between the pixel PXk and the pixel PXk + 1 so that the same amount of charge is shared by the pair of pixels PXk-1 and PXk. The pixel PXk is set to an intermediate voltage value together with the source line X1 in the precharge period before one horizontal scanning period (1H). This also promotes the potential transition of the source line X1 performed by the buffer output of the source driver 20 after the precharge period, and as a result, the time for transitioning the pixel voltage of the pixel PXk to the voltage value reflecting the display signal DATA. Shorten.

It is a figure which shows schematically the circuit structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows schematically the structure of the source driver shown in FIG. FIG. 3 is a diagram illustrating a configuration of a gradation reference voltage generation circuit illustrated in FIG. 2. It is a wave form diagram which shows operation | movement of the liquid crystal display device shown in FIG. It is a wave form diagram which shows the H line inversion drive system known conventionally.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2 ... Array substrate, 3 ... Opposite substrate, 4 ... Liquid crystal layer, 5 ... Controller, 6 ... Common voltage generation circuit, 7 ... Tone reference voltage generation circuit, 10 ... Gate driver, 20 ... Source driver , 23 ... D / A conversion circuit, 23 '... D / A conversion unit, VC1 to VC6 ... Voltage switching units VC1 to VC6, VG1 to VB6 ... Variable voltage generation unit, 30 ... D / A converter, 31 ... Output buffer , PE ... pixel electrode, CE ... common electrode, PX ... liquid crystal pixel, DP ... display panel, CNT ... control unit, X ... source line, Y ... gate line, W ... pixel switching element.

Claims (8)

A predetermined number obtained from a gradation reference voltage generating circuit for generating a plurality of gradation reference voltages from a plurality of voltage output terminals, and a resistor group connected in series so as to divide voltages between the terminals of the plurality of voltage output terminals. And a signal conversion circuit that selectively converts a display signal into a pixel voltage by selectively using the grayscale voltage, and the grayscale reference voltage generation circuit outputs the plurality of grayscale reference voltages for each conversion operation of the signal conversion circuit. Temporarily set to a precharge intermediate voltage value that is the same in the pixel voltage range corresponding to the maximum gradation difference of the display signal, and then the plurality of gradation reference voltages for different display in the pixel voltage range A display signal processing apparatus comprising an output control unit for setting a voltage value. The gradation reference voltage generation circuit is configured to generate a plurality of variable voltage generation units that generate any one of the plurality of gradation reference voltages as an output voltage, and a plurality of voltages that respectively control the plurality of variable voltage generation units as the output control unit. The display signal processing apparatus according to claim 1, further comprising a switching unit. Each voltage switching unit includes a first register that holds numeric data representing the display voltage value, a second register that holds numeric data representing a precharge intermediate voltage value, and numeric data held in the first register; 3. The display signal processing apparatus according to claim 2, further comprising a changeover switch that selectively outputs the numerical data held in the second register to the corresponding variable voltage generator. 4. The display signal processing apparatus according to claim 3, wherein each variable voltage generator includes a digital-analog converter that converts numerical data output from the changeover switch of the corresponding voltage switching unit into an analog voltage. Each voltage switching unit is externally controlled with respect to numerical data held in the first register, numerical data held in the second register, and timing for outputting numerical data from the changeover switch. Item 4. The display signal processing device according to Item 3. 3. The display signal processing according to claim 2, wherein the gradation reference voltage generation circuit further includes a plurality of resistors connected in series so as to divide voltages between output terminals of the plurality of variable voltage generation units. apparatus. The display signal processing apparatus according to claim 1, wherein the precharge intermediate voltage value is approximately ½ of the pixel voltage range. A plurality of display pixels arranged in a substantially matrix, a plurality of gate lines arranged along a row of the plurality of display pixels, a plurality of source lines arranged along a column of the plurality of display pixels, and the A liquid crystal display panel including a plurality of pixel switching elements that are arranged in the vicinity of intersections of the plurality of gate lines and the plurality of source lines and electrically connect the corresponding display pixels to the corresponding source lines while the corresponding gate lines are driven. A gate driver circuit that sequentially drives the plurality of gate lines, and a source driver circuit that drives the plurality of source lines in response to a display signal for one row of display pixels. A gradation reference voltage generating circuit for generating a plurality of gradation reference voltages from a plurality of voltage output terminals, and a resistor connected in series so as to divide voltages between the terminals of the plurality of voltage output terminals. A signal conversion circuit that selectively converts a display signal into a pixel voltage by selectively using a predetermined number of gradation voltages obtained from a group, and wherein the plurality of gradation reference voltage generation circuits for each conversion operation of the signal conversion circuit Is temporarily set to a precharge intermediate voltage value that is the same in the pixel voltage range corresponding to the maximum gradation difference of the display signal, and then the plurality of gradation reference voltages are set to the pixel voltage. A display signal processing device including an output control unit for setting display voltage values different from each other in a range, wherein the output control unit sets the plurality of gradation reference voltages to precharge intermediate voltage values A liquid crystal display device configured to drive at least two adjacent gate lines together during a precharge period.

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