CN101162335A - Gate driver, electro-optical device, electronic instrument, and drive method - Google Patents

Gate driver, electro-optical device, electronic instrument, and drive method Download PDF

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Publication number
CN101162335A
CN101162335A CNA2007101631330A CN200710163133A CN101162335A CN 101162335 A CN101162335 A CN 101162335A CN A2007101631330 A CNA2007101631330 A CN A2007101631330A CN 200710163133 A CN200710163133 A CN 200710163133A CN 101162335 A CN101162335 A CN 101162335A
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grid
voltage
selection
output
line
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CN100570457C (en
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西村元章
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

A gate driver includes a first gate output circuit which outputs a select signal for selecting the first gate line, a second gate output circuit which outputs a select signal for selecting the second gate line in a select period subsequent to the select period of the first gate line, and a transistor as a first gate line short-circuiting circuit provided between outputs of the first and second gate output circuits. The transistor short-circuits the outputs of the first and second gate output circuits in a period between the select period of the first gate line and the select period of the second gate line.

Description

Gate drivers, electrooptical device, electronic equipment and driving method
Technical field
The present invention relates to gate drivers, electrooptical device, electronic equipment and driving method etc.
Background technology
In recent years, as liquid crystal display (Liquid Crystal Display:LCD) panel (the sensu lato display panel that carries on electronic equipments such as pocket telephone.More sensu lato electrooptical device), the known LCD panel that the LCD panel of simple matrix mode is arranged and used the active matrix mode of thin film transistor (TFT) on-off elements such as (Thin Film Transistor: be designated hereinafter simply as TFT).
The simple matrix mode is compared with the active matrix mode and is easy to realize low power consumption, but is difficult to but realize that multicolourization and live image show.On the other hand, the active matrix mode is suitable for multicolourization and live image shows, but is difficult to realize low power consumption.
In the LCD panel of the LCD of simple matrix mode panel or active matrix mode, drive so that the impressed voltage that puts on the liquid crystal (sensu lato photoelectric material) that constitutes pixel is interchange.As such AC driving method, be extensive use of line inversion driving or territory inversion driving (frame inversion driving).Drive in the online inversion driving so that corresponding one or more sweep trace of the polarity of the impressed voltage of liquid crystal reverses.In the inversion driving of territory, drive so that the polarity corresponding domain of the impressed voltage of liquid crystal (corresponding frame) is reversed.
At this moment, change by the opposed electrode voltage (common electric voltage) that offers opposite electrode (public electrode) according to inversion driving timing (timing, sequential), can reduce the outer voltage level that is added on pixel electrode, wherein, this opposite electrode is opposed with the pixel electrode that constitutes pixel.
When carrying out such AC driving, discharging and recharging of liquid crystal can cause amount of power consumption to increase.Following technology is for example disclosed in patent documentation 1: when inversion driving, make the electric charge initialization that is stored in the liquid crystal by making two electric pole short circuits across liquid crystal, and realize low power consumption by the medium voltage that changes the voltage before the electric pole short circuit into.
Patent documentation 1: TOHKEMY 2002-244622 communique
But there is following problem in patent documentation 1 disclosed technology: the reduction effect of amount of power consumption will exist with ... voltage given on source electrode line.Therefore, the reduction effect that has a quantity of electric charge is ideal situation so not, and wherein this quantity of electric charge is the quantity of electric charge that the opposite electrode to reversal of poles discharges and recharges.In addition, in patent documentation 1 disclosed technology, there is following problem: according to the relation between the polarity of voltage given on the source electrode line and opposed electrode voltage, make two electric pole short circuits across liquid crystal, thereby the quantity of electric charge that can cause discharging and recharging increases on the contrary, the situation of the effect reduction of low power consumption.
On the other hand, when driving the LCD panel, need the driving grid line.But, in patent documentation 1 disclosed technology, can not reduce gate line and drive the amount of power consumption that causes.Suppose,,, not only be difficult to obtain the effect of low power consumption, also can make the image quality deterioration with to make source electrode line different with the situation of opposite electrode short circuit even when making gate line and opposite electrode short circuit.
Like this, in order to obtain certain low power consumption effect, preferably can reduce gate line and drive the amount of power consumption that causes.
Summary of the invention
The present invention can provide gate drivers, electrooptical device, electronic equipment and the driving method of the amount of power consumption that the driving that can reduce gate line causes.
In order to solve the problems of the technologies described above, the present invention relates to a kind of gate drivers, this gate drivers is used for first and second gate line of scan light electric installation, comprising: the first grid output circuit, output is used to select the selection signal of described first grid polar curve; The second grid output circuit, during the next one during the selection of described first grid polar curve was selected, output was used to select the selection signal of described second grid line; First grid polar curve short circuit current, be arranged between the output of described first and second grid output circuit, wherein, described first grid polar curve short circuit current makes the output short-circuit of described first and second grid output circuit during the selection of described first grid polar curve and between during the selection of described second grid line.
According to the present invention, utilize electric charge again at the negative edge of the selection signal of first grid polar curve, the rising edge of second grid line, can not discharge and recharge from the outside under the situation of electric charge, make and select the level of signal to change.Therefore, can cut down the quantity of electric charge that discharge and recharge when the voltage that makes first and second gate line changes, drive the amount of power consumption that causes so can reduce gate line.Consequently when driving electrooptical device, must obtain the effect of certain low power consumption.
In addition, in the gate drivers that the present invention relates to, each grid output circuit of described first and second grid output circuit comprises: first on-off circuit is arranged between the output of non-selection voltage with power lead and this grid output circuit of the non-selection voltage that provides gate line; The second switch circuit, being arranged at the selection voltage that provides the selection of gate line voltage uses between power lead and this grid output circuit, wherein, described first and second on-off circuit be nonconducting state during after, one of them of described first and second on-off circuit is set at conducting state.
In addition, in the gate drivers that the present invention relates to, described first grid polar curve short circuit current is a transistor, during the non-selection of described first and second gate line, can carry out grid control so that described transistor is a conducting state.
According to above-mentioned each invention, can when the driving grid line, utilize electric charge again with simple structure, thereby realize low power consumption.
In addition, in the gate drivers that the present invention relates to, after during the short circuit of the output of described first and second grid output circuit, be the timing of low potential side voltage in the change in voltage of described first grid polar curve, in the selected pixel of described first grid polar curve, write the GTG signal.
According to the present invention, in the selected pixel of first grid polar curve, the timing (timing) that is changed to low potential side voltage in the selection voltage of signals of this first grid polar curve writes voltage, so, even, can not make the image quality deterioration because the short circuit of first and second gate line causes repeating during the pixel selection yet.
In addition, the present invention relates to a kind of electrooptical device, comprising: many gate lines; Many source electrode lines; A plurality of pixels, each pixel is specified by each gate line and each source electrode line; According to above-mentioned each described gate drivers, in described many gate lines, scan described first and second gate line at least.
In addition, the present invention relates to a kind of electrooptical device, comprising: many gate lines; Many source electrode lines; A plurality of pixels, each pixel is specified by each gate line and each source electrode line; First grid polar curve short circuit current, be arranged in described many gate lines first grid polar curve and then between the selecteed second grid line of this first grid polar curve, wherein, described first grid polar curve short circuit current, during the selection of described first grid polar curve and between during the selection of described second grid line, make described first and second gate line short circuit.
In addition, in the electrooptical device that the present invention relates to, described first grid polar curve short circuit current is a transistor, during the non-selection of described first and second gate line, carries out grid control so that described transistor is a conducting state.
In addition, in the electrooptical device that the present invention relates to, after during the short circuit of the output of described first and second grid output circuit, be the timing of low potential side voltage in the change in voltage of described first grid polar curve, in the selected pixel of described first grid polar curve, write the GTG signal.
After during the short circuit of the output of described first and second grid output circuit, be the timing of low potential side voltage in the change in voltage of described first grid polar curve, in the pixel of described first grid line options, write the GTG signal.
In addition, in the electrooptical device that the present invention relates to, can comprise: the first grid output circuit, output is used to select the selection signal of described first grid polar curve; The second grid output circuit, during the next one during the selection of described first grid polar curve was selected, output was used to select the selection signal of described second grid line.
In addition, in the electrooptical device that the present invention relates to, can comprise the source electrode driver that is used for providing the GTG signal of each pixel correspondence to described many source electrode lines.
In addition, the present invention relates to a kind of electrooptical device that comprises above-mentioned each described gate drivers.
According to above-mentioned each invention, utilize electric charge again at the negative edge of the selection signal of first grid polar curve, the rising edge of second grid line, can not discharge and recharge from the outside under the situation of electric charge, make and select the level of signal to change.Therefore, can cut down the quantity of electric charge that discharge and recharge when the voltage that makes first and second gate line changes, drive the amount of power consumption that causes so can reduce gate line.A kind of electrooptical device that must obtain certain low power consumption effect consequently can be provided.
In addition, the present invention relates to a kind of electronic equipment that comprises above-mentioned each described gate drivers.
In addition, the present invention relates to a kind of electronic equipment that comprises above-mentioned each described electrooptical device.
According to above-mentioned each invention, a kind of electrooptical device can be provided, this electrooptical device will inevitably obtain certain low power consumption effect by utilizing electric charge again when the driving grid line.
In addition, the present invention relates to a kind of driving method, this driving method is used for first and second gate line of scan light electric installation, during the selection of described first grid polar curve, output is used to select the selection signal of this first grid polar curve, during the selection of described first grid polar curve and between during the selection of described second grid line, make described first and second gate line short circuit, after making first and second gate line short circuit, end under the state of described first and second gate line at electricity, during the selection of described second grid line, output is used to select the selection signal of described second grid line.
In addition, in the driving method that the present invention relates to, after described first and second gate line short circuit, be the timing of low potential side voltage in the change in voltage of described first grid polar curve, in the pixel of described first grid line options, write the GTG signal.
Description of drawings
Fig. 1 is the structure example block diagram of the liquid-crystal apparatus of present embodiment.
Fig. 2 is the structure example block diagram of the gate drivers of Fig. 1.
Fig. 3 is the structure example block diagram of the source electrode driver of Fig. 1.
Fig. 4 is the structure example key diagram of reference voltage generating circuit, DAC and the source line driving circuit of Fig. 3.
Fig. 5 is the structure example block diagram of the power circuit of Fig. 1.
Fig. 6 shows the example of drive waveforms of the display panel of Fig. 1.
Fig. 7 is the key diagram that the reversal of poles of present embodiment drives.
Fig. 8 shows the structure of the gate drivers of present embodiment and wants an example of portion.
Fig. 9 is the sequential chart of an example of control signal of the output buffer of Fig. 8.
Figure 10 shows the example of drive waveforms of the gate drivers of present embodiment.
Figure 11 is other structure example block diagrams of liquid-crystal apparatus of the variation of present embodiment.
Figure 12 has been to use the structure example block diagram of electronic equipment of the gate drivers of present embodiment or this variation.
Embodiment
Accompanying drawing with reference to following is described in detail the preferred embodiments of the present invention.In addition, below the embodiment of explanation does not limit improperly to the content of putting down in writing in claims of the present invention.Below Shuo Ming all structures might not all be necessary constitutive requirements of the present invention.
1, liquid-crystal apparatus
Fig. 1 is the block diagram example of the liquid-crystal apparatus of present embodiment.
Liquid-crystal apparatus 10 (liquid crystal indicators.Sensu lato display device) comprises display panel 12 (sense stricto liquid crystal panel, LCD (Liquid Crystal Display) panel), source electrode driver 20 (sensu lato data line drive circuit), gate drivers 30 (sensu lato scan line drive circuit), display controller 40, power circuit 50.In addition, liquid-crystal apparatus 10 there is no need to comprise all these circuit modules, also can be the structure of omitting one partial circuit module.
Here, display panel 12 (sensu lato electrooptical device) comprises many gate lines (sensu lato sweep trace), many source electrode lines (sensu lato data line) and a plurality of pixels of being specified each pixel by each gate line and each source electrode line.At this moment, by thin film transistor (TFT) TFT (Thin Film Transistor, sensu lato on-off element) being connected in source electrode line, pixel electrode is connected in this TFT, thereby can constitutes the liquid-crystal apparatus of active array type in each pixel.
More particularly, display panel 12 is the amorphous silicon liquid crystal panels that are formed with amorphous silicon membrane on active-matrix substrate (for example glass substrate).On active-matrix substrate, dispose many gate lines G of arranging and extending to directions X respectively along the Y direction of Fig. 1 1～G M(M is the natural number more than or equal to 2), many gate line S that arrange and extend to the Y direction respectively along directions X 1～S N(N is the natural number more than or equal to 2).In addition, with gate lines G K(1≤K≤M, K are natural numbers) and source electrode line S LThe position of the point of crossing correspondence of (1≤L≤N, L are natural numbers) is provided with thin film transistor (TFT) TFT KL(sensu lato on-off element).
TFT KLGate electrode be connected in gate lines G K, TFT KLThe source electrode be connected in source electrode line S L, TFT KLDrain electrode be connected in pixel electrode PE KLAt this pixel electrode PE KLAnd formation liquid crystal capacitance CL between the opposite electrode CE (common electrode, public electrode) KL(liquid crystal cell) and auxiliary capacitor CS KL, wherein, this opposite electrode CE and pixel electrode PE KLOpposed across liquid crystal (sensu lato photoelectric material).In addition, be formed with TFT KL, pixel electrode PE KLDeng active-matrix substrate and be formed with between the counter substrate of opposite electrode CE and enclose liquid crystal, the penetrance of pixel is according to pixel electrode PE KLAnd the impressed voltage between the opposite electrode CE and changing.
The voltage level of the opposed electrode voltage VCOM of given opposite electrode CE (hot side voltage VCOMH, low potential side voltage VCOML) is to be generated by the opposed electrode voltage generative circuit that power circuit 50 is comprised.For example, opposite electrode CE forms one side on counter substrate.
Source electrode driver 20 drives the source electrode line S of display panel 12 based on luma data 1～S NOn the other hand, the gate lines G of gate drivers 30 scannings (driving successively) display panel 12 1～G M
Display controller 40 is according to content control source electrode driver 20, gate drivers 30 and the power circuit 50 of not shown central arithmetic processing apparatus host setting such as (CentralProcessing Unit:CPU).More particularly, display controller 40 carries out the setting of mode of operation for example or is provided at inner vertical synchronizing signal or the horizontal-drive signal that generates for source electrode driver 20 and gate drivers 30, for power circuit 50, the outer reversal of poles timing (timing) that is added on the voltage level of the opposed electrode voltage VCOM on the opposite electrode CE of control.
Power circuit 50 generates the voltage level of the opposed electrode voltage VCOM that drives display panel 12 necessary various voltage levels (gray scale voltage) or opposite electrode CE based on the reference voltage that provides from the outside.
The liquid-crystal apparatus 10 of this spline structure, under the control of display controller 40, based on the luma data that provides from the outside, source electrode driver 20, gate drivers 30 and power circuit 50 are coordinated mutually to drive display panel 12.
Among this external Fig. 1, source electrode driver 20, gate drivers 30 and power circuit 50 is integrated, can constitute display driver 60 as semiconductor device (integrated circuit, IC).
In addition, display driver 60 can be built-in with display controller 40 in Fig. 1.Perhaps in Fig. 1, display driver 60 also can be the semiconductor device that any one and power circuit in source electrode driver 20 and the gate drivers 30 50 is integrated.
1, gate drivers
Fig. 2 shows the structure example of the gate drivers 30 of Fig. 1.
Gate drivers 30 comprises shift register 32, level shifter 34, output buffer 36.
Shift register 32 comprises the corresponding a plurality of triggers that are provided with, connect successively with each gate line.Remain in the trigger if this shift register 32 will enable input/output signal EIO synchronously with clock signal clk, then will enable the trigger that input/output signal EIO is displaced to adjacency synchronously with clock signal clk successively.Here, the input/output signal EIO that enables that is imported is the vertical synchronizing signal that provides from display controller 40.
The voltage level that level shifter 34 will adapt for the transistor ability with the liquid crystal cell of display panel 12 and TFT from the voltage level shifting of shift register 32.Need high-voltage level as this voltage level, therefore, adopted the high withstand voltage operation different with other logical circuit portions.
Output buffer 36 cushions and outputs to gate line with the scanning voltage (selection signal) that level shifter 34 has been shifted, and the driving grid line.Scanning voltage is any one in non-selection voltage and the selection voltage.
The output buffer 36 of the data driver 30 in the present embodiment is at least in the gate lines G that drives as first and second gate line 1, G 2The utilization again of Shi Jinhang electric charge, thus the power consumption that the driving of gate line causes can be reduced.
In addition, in the present embodiment, thereby be to pass through shift enable input/output signal EIO raster polar curve, but not only be defined in this by shift register 32, for example also can be that gate drivers 30 comprises address decoder, select gate line based on the decoded result of this address decoder.
1, source electrode driver
Fig. 3 shows the structure example of the source electrode driver 20 of Fig. 1.
Source electrode driver 20 comprises shift register 22, line latch 24,26, reference voltage generating circuit 27, DAC 28 (Digital-to-Analog Converter) (sensu lato data voltage generative circuit), source line driving circuit 29.
Shift register 22 comprises the corresponding a plurality of triggers that are provided with, connect successively with each source electrode line.If this shift register 22 keeps enabling input/output signal EIO with clock signal clk synchronously, then will enable the trigger that input/output signal EIO is displaced to adjacency synchronously with clock signal clk successively.
Be that unit imports luma data (DIO) from display controller 40 to line latch 24 for example with 18 (6 (luma data) * 3 (RGB is of all kinds)).Line latch 24 latchs this luma data (DIO) synchronously with the input/output signal EIO that enables that each trigger by shift register 22 is shifted successively.
Line latch 26 is synchronous with the horizontal-drive signal LP that is provided by display controller 40, latchs the luma data of a horizontal scanning unit that is latched by line latch 24.
Reference voltage generating circuit 27 generates 64 (=2 6) reference voltage of planting.64 kinds of reference voltages that will be generated by reference voltage generating circuit 27 offer DAC 28.
DAC (data voltage generative circuit) 28 generates the data voltage of the simulation that offer each source electrode line.Specifically, DAC 28 selects from any one reference voltage in the reference voltage of reference voltage generating circuit 27 based on the luma data from the numeral of line latch 26, the data voltage of the luma data corresponding simulating of output numeral.
Source line driving circuit 29 cushions from the data voltage of DAC 28 and outputs to source electrode line, and the drive source polar curve.Specifically, source line driving circuit 29 comprises the operational amplifier OPC (sensu lato impedance inverter circuit) that connects in the voltage follower mode of corresponding each source electrode line setting, these each operational amplifier OPC will carry out impedance transformation from the data voltage of DAC 28, and output to each source electrode line.
In addition, in Fig. 3, adopted the luma data of numeral has been carried out the digital-to-analog conversion, output to the structure of source electrode line by source line driving circuit 29, but also can adopt, output to the structure of source electrode line by source line driving circuit 29 maintenance of taking a sample of the vision signal of simulation.
Fig. 4 shows the structure example of reference voltage generating circuit 27, DAC 28 and the source line driving circuit 29 of Fig. 3.In Fig. 4, luma data is data D0～D5 of six, and XD0～XD5 represents the reversal data of everybody data.In addition, in Fig. 4, the part identical with Fig. 3 marked identical symbol, and omitted the explanation to it.
Reference voltage generating circuit 27 carries out resistance with voltage VDDH, the VSSH at two ends to be cut apart, and generates 64 kinds of reference voltages.Represented each the GTG value of each reference voltage and 6 luma data is corresponding.Each reference voltage jointly offers source electrode line S 1～S NEach source electrode line.
DAC 28 comprises the demoder with the corresponding setting of each bar source electrode line, and each demoder outputs to operational amplifier OPC with the reference voltage of luma data correspondence.
1, power circuit
Fig. 5 shows the structure example of the power circuit of Fig. 1.
Power circuit 50 comprises positive dirction twice booster circuit 52, scanning voltage generative circuit 54, opposed electrode voltage generative circuit 56.Provide system earth supply voltage VSS and system power supply voltage VDD on this power circuit 50.
On positive dirction twice booster circuit 52, provide system earth supply voltage VSS and system power supply voltage VDD.In addition, positive dirction twice booster circuit 52 is a benchmark with system earth supply voltage VSS, generates the supply voltage VOUT that system power supply voltage VDD is boosted to twice on positive dirction.Be that positive dirction twice booster circuit 52 boosts to twice with the voltage difference between system earth supply voltage VSS and the system power supply voltage VDD.Such positive dirction twice booster circuit 52 can be made of the known charge pump circuit.Supply voltage VOUT is offered source electrode driver 20, scanning voltage generative circuit 54 or opposed electrode voltage generative circuit 56.In addition, preferred positive dirction twice booster circuit 52 is adjusted voltage level with after boosting more than or equal to the multiplying power of boosting of twice by voltage stabilizer, and output boosts to system power supply voltage VDD the supply voltage VOUT of twice on positive dirction.
Provide system earth supply voltage VSS and system power supply voltage VDD on the scanning voltage generative circuit 54.In addition, scanning voltage generative circuit 54 generates scanning voltage.Scanning voltage is the outer voltage that is added on the gate line that gate drivers 30 driven.The hot side voltage of this scanning voltage is VDDHG, and low potential side voltage is VEE.
Opposed electrode voltage generative circuit 56 generates opposed electrode voltage VCOM.Opposed electrode voltage generative circuit 56 is exported hot side voltage VCOMH or low potential side voltage VCOML based on polarity inversion signal POL as opposed electrode voltage VCOM.Polarity inversion signal POL is regularly generated by display controller 40 according to reversal of poles.
2. drive waveforms
Fig. 6 shows the example of drive waveforms of the display panel 12 of Fig. 1.
Be added with the gray scale voltage DLV of the GTG value of corresponding luma data outside on source electrode line.In Fig. 6, with system earth supply voltage VSS (=0V) be the gray scale voltage DLV of the benchmark amplitude that is added with 5V outward.
On gate line, be added with outward during non-select low potential side voltage VEE (=-10V) as non-selection voltage, (=15V) scanning voltage GLV is as selecting voltage to be added with hot side voltage VDDHG when selecting outward.
Be added with outside on opposite electrode CE hot side voltage VCOMH (=3V), low potential side voltage VCOML (=-2V) opposed electrode voltage VCOM.In addition, be that the polarity of voltage level of the opposed electrode voltage VCOM of benchmark is regularly reversed according to reversal of poles with default voltage.The waveform of opposed electrode voltage VCOM when figure 6 illustrates so-called sweep trace inversion driving.According to this reversal of poles regularly, the gray scale voltage DLV of source electrode line also is to be benchmark its polarity of reversing with default voltage.
But liquid crystal cell has the character that its quality of long-time impressed DC voltage will deterioration.Therefore, need add the type of drive of reversing every the regulated period chien shih in the polarity of voltage of liquid crystal cell.As such type of drive frame inversion driving, scanning (grid) line inversion driving, data (source electrode) line inversion driving, some inversion driving etc. are arranged.
Wherein, though frame inversion driving amount of power consumption is low, has the bad shortcoming of image quality.In addition, data line inversion driving, some inversion driving image quality are fine, need high-tension shortcoming but have the display panel of driving.
In the present embodiment, for example adopted the sweep trace inversion driving.In this sweep trace inversion driving, each scan period of voltage (corresponding every gate line) that is added on liquid crystal cell is outward all carried out reversal of poles.For example, in first scan period (sweep trace), be added on liquid crystal cell outside the voltage of positive polarity, in second scan period, be added on liquid crystal cell outside the voltage of negative polarity, in the 3rd scan period, be added on liquid crystal cell outside the voltage of positive polarity.On the other hand, in the middle of next frame, be to be added on liquid crystal cell outside the voltage of negative polarity in first scan period specifically, in second scan period, be added on liquid crystal cell outside the voltage of positive polarity, in the 3rd scan period, be added on liquid crystal cell outside the voltage of negative polarity.
In addition, in this sweep trace inversion driving, voltage level each scan period of the opposed electrode voltage VCOM of opposite electrode CE is all carried out reversal of poles.
More specifically as shown in Figure 7, among the T1 during positive pole (between the first phase), the voltage level of opposed electrode voltage VCOM is low potential side voltage VCOML, then is hot side voltage VCOMH among the T2 during negative pole (second phase).In addition, also reverse according to outer its polarity of gray scale voltage that is added on source electrode line of this timing.In addition, low potential side voltage VCOML is to be the reversed voltage level of polarity of hot side voltage VCOMH of benchmark with default voltage level.
Here, the voltage level of pixel electrode that T1 provides the gray scale voltage of source electrode line during anodal be higher than opposite electrode CE voltage level during.In this period T1, be added on liquid crystal cell outside the voltage of positive polarity.On the other hand, negative pole during the T2 voltage level of pixel electrode that provides the gray scale voltage of source electrode line be lower than opposite electrode CE voltage level during.In this period T2, be added on liquid crystal cell outside the voltage of negative polarity.
By reversal of poles opposed electrode voltage VCOM in this wise, can reduce driving the needed voltage of display panel.Thus, can reduce the withstand voltage of driving circuit, realize simplification, the cost degradation of driving circuit manufacturing process.
3. the explanation of present embodiment
In the present embodiment, gate drivers 30 is by carrying out the utilization again of electric charge, can reduce the amount of power consumption that the driving of gate line causes.Below, the portion that wants describes to the structure of such gate drivers 30.
Fig. 8 shows the structure of gate drivers 30 in the present embodiment and wants an example of portion.Fig. 8 shows the circuit diagram of structure example of the output buffer 36 of Fig. 2.
Output buffer 36 comprises the grid output circuit that corresponding each gate line is provided with.
To gate lines G 1The grid output circuit GO of output scanning voltage 1(first grid output circuit) comprising: as n type (second conductivity type) burning film semiconductor (Metal Oxide Semiconductor:MOS) the transistor SW1n of first on-off circuit; And as p type (first conductivity type) the MOS transistor SW1p of second switch circuit.Be connected with the non-selection voltage power lead on the source electrode of transistor SW1n, this non-selection voltage is with the voltage VEE that provides on the power lead as the non-selection voltage of gate line.Be connected with grid output circuit GO in the drain electrode of transistor SW1n 1Output node.Provide control signal G on the grid of transistor SW1 n 1CNT.Be connected with on the source electrode of transistor SW1p and select the voltage power lead, this selection voltage is with the voltage VDDHG that provides on the power lead as the selection voltage of gate line.Be connected with grid output circuit GO in the drain electrode of transistor SW1p 1Output node.Provide control signal XG on the grid of transistor SW1p 1CNT.Generate control signal G 1CNT, XG 1CNT is so that not conducting simultaneously of transistor SW1n, SW1p.And, provide control signal G to output buffer 36 from level shifter 34 1CNT, XG 1CNT perhaps generates control signal G in output buffer 36 1CNT, XG 1CNT.
Similarly, to gate lines G 2The grid output circuit GO of output scanning voltage 2(second grid output circuit) comprising: as the n type MOS transistor SW2n of first on-off circuit; And as the p type MOS transistor SW2p of second switch circuit.Be connected with the non-selection voltage power lead on the source electrode of transistor SW2n, this non-selection voltage is with the voltage VEE that provides on the power lead as the non-selection voltage of gate line.Be connected with grid output circuit GO in the drain electrode of transistor SW2n 2Output node.Provide control signal G on the grid of transistor SW2n 2CNT.Be connected with on the source electrode of transistor SW2p and select the voltage power lead, this selection voltage is with the voltage VDDHG that provides on the power lead as the selection voltage of gate line.Be connected with grid output circuit GO in the drain electrode of transistor SW2p 2Output node.Provide control signal XG on the grid of transistor SW2p 2CNT.Generate control signal G 2CNT, XG 2CNT is so that not conducting simultaneously of transistor SW2n, SW2p.And, provide control signal G to output buffer 36 from level shifter 34 2CNT, XG 2CNT perhaps generates control signal G in output buffer 36 2CNT, XG 2CNT.
Grid output circuit GO 3～GO MAlso have and grid output circuit GO 1Identical structure.
Such output buffer 36 also comprises the n type MOS transistor Q as the gate line short circuit current of the first～the (M-1) 1～Q M-1Transistor Q as first grid polar curve short circuit current 1Be arranged on grid output circuit GO 1Output and grid output short-circuit GO 2Output (output node) between.Transistor Q promptly, 1Source electrode (drain electrode) be connected in grid output circuit GO 1Output, transistor Q 1Drain electrode (source electrode) be connected in grid output short-circuit GO 2Output.Transistor Q 1Grid on provide control signal SWC 1Similarly, as the transistor Q of second grid line short circuit current 2Be arranged on grid output circuit GO 2Output and grid output short-circuit GO 3Output between.Transistor Q promptly, 2Source electrode (drain electrode) be connected in grid output circuit GO 2Output, transistor Q 2Drain electrode (source electrode) be connected in grid output short-circuit GO 3Output.Transistor Q 2Grid on provide control signal SWC 2Below, similarly for example as the transistor Q of the gate line short circuit current of (M-1) M-1Be arranged on grid output circuit GO M-1Output and grid output circuit GO MOutput between.
In addition, as the transistor Q of first grid polar curve short circuit current 1In gate lines G 1During the selection of (first grid polar curve) and gate lines G 2Between during the selection of (second grid line), make grid output circuit GO 1, GO 2Output short-circuit.Similarly, as the transistor Q of second grid line short circuit current 2In gate lines G 2Selection during and gate lines G 3Selection during between, make grid output circuit GO 2, GO 3Output short-circuit.Transistor Q promptly, j(1≤j≤M-1, j are integers) is in gate lines G jSelection during and gate lines G J+1Selection during between, make grid output circuit GO j, GO J+1Output short-circuit.
Fig. 9 is the sequential chart of an example of control signal of the output buffer 36 of Fig. 8.
If be conceived to grid output short-circuit GO 1, control signal G then 1When CNT is the H level, will output to gate lines G as the voltage VEE of non-selection voltage 1Afterwards, if control signal G 1CNT is the L level, then through after during the predetermined OFF-OFF, and control signal XG 1CNT is changed to the L level from the H level.Control signal XG 1When CNT is the L level, will output to gate lines G as the voltage VDDHG that selects voltage 1In addition, control signal XG 1After CNT is changed to the H level, after during the predetermined OFF-OFF, control signal G 1CNT is changed to the H level from the L level.Thus, will output to gate lines G as the voltage VEE of non-selection voltage 1Inner control signal SWC during this OFF-OFF 1Has pulse.Based on control signal G 1CNT, XG 1CNT is at for example output buffer 36 (grid output circuit GO 1) the middle control signal SWC that generates 1
Then, if be conceived to grid output circuit GO 2, then in gate lines G 1, G 2OFF-OFF during be about to begin before, control signal G 2CNT is changed to the L level from the H level.In addition, after during the above-mentioned OFF-OFF of process, control signal XG 2CNT is changed to the L level from the H level.Control signal XG 2When CNT is the L level, will output to gate lines G as the voltage VDDHG that selects voltage 2In fact by control signal SWC 1In gate lines G 1, G 2Between carry out electric charge and utilize again, therefore, in gate lines G 2Selection during before, gate lines G 2Voltage be voltage than voltage VEE hot side.Promptly, grid control is as the transistor Q of first grid polar curve short circuit current 1, so that in gate lines G as first and second gate line 1, G 2Non-selection during, transistor Q 1Be conducting state.In addition, make gate lines G 1, G 2After the short circuit, electricity is by gate lines G 1, G 2State under, in gate lines G 2Selection during, output is used to select gate lines G 2The selection signal.Like this, can cut down from the outside to gate lines G 2The quantity of electric charge that discharges and recharges.In addition, control signal XG 2After CNT is changed to the H level, after during the predetermined OFF-OFF of process, control signal G 2CNT is changed to the H level from the L level.Thus, will output to gate lines G as the voltage VEE of non-selection voltage 2Control signal SWC during this OFF-OFF 2Has pulse.Based on control signal G 2CHT, XG 2CNT is at for example output buffer 36 (grid output circuit GO 2) generation control signal SWC 2
Similarly, if be conceived to grid output circuit GO 3, then in gate lines G 2, G 3OFF-OFF during be about to begin before, control signal G 3CNT is changed to the L level from the H level.In addition, after during the above-mentioned OFF-OFF of process, control signal XG 3CNT is changed to the L level from the H level.Control signal XG 3When CNT is the L level, will output to gate lines G as the voltage VDDHG that selects voltage 3In fact by control signal SWC 2In gate lines G 2, G 3Between carry out electric charge and utilize again, therefore, in gate lines G 3Selection during before, gate lines G 3Voltage be voltage than voltage VEE hot side.Promptly, grid control is as the transistor Q of second grid line short circuit current 2, so that in gate lines G as second and third gate line 2, G3 non-selection during, transistor Q 2Be conducting state.In addition, make gate lines G 2, G 3After the short circuit, electricity is by gate lines G 2, G 3State under, in gate lines G 3Selection during, output is used to select gate lines G 3The selection signal.Like this, can cut down from the outside to gate lines G 3The quantity of electric charge that discharges and recharges.In addition, control signal XG 3After CNT is changed to the H level, after during the predetermined OFF-OFF of process, control signal G 3CNT is changed to the H level from the L level.Thus, will output to gate lines G as the voltage VEE of non-selection voltage 3Control signal SWC during this OFF-OFF 3Has pulse.Based on control signal G 3CHT, XG 3CNT is at for example output buffer 36 (grid output circuit GO 3) generation control signal SWC 3
Grid output circuit GO 4～GO MIt also is identical situation.
Figure 10 shows an example of the drive waveforms of the gate drivers 30 in the present embodiment.
At control signal SWC 1～SWC M-1Be the electric charge of H level again between period of use, by as based on control signal SWC 1～SWC M-1Each control signal and become the transistor Q of the gate line short circuit current of conducting state 1～Q M-1, two gate lines are set at same potential.
Promptly, work as gate lines G 1The selection signal be the H level after, control signal SWC 1Be the H level, and make gate lines G 1, G 2Short circuit.Gate lines G consequently 1And gate lines G 2Be same potential.Afterwards, control signal SWC 1Be the L level, and to gate lines G 2The selection signal of output H level.Thus, at electric charge again between period of use, gate lines G 1Can not discharge and recharge from the outside under the situation of electric charge, making voltage only change current potential from voltage VDDHG to gate lines G 1, G 2Short circuit after the voltage Δ VG1 of current potential.In addition, at this electric charge again between period of use, gate lines G 2Can not discharge and recharge from the outside under the situation of electric charge, making voltage only change current potential from voltage VEE to gate lines G 1, G 2Short circuit after the voltage Δ VG2 of current potential.Therefore, can cut down and make gate lines G 1, G 2The voltage quantity of electric charge that discharge and recharge when changing, so can cut down amount of power consumption.
Here, with gate lines G 1Be changed to the gate lines G that is timed to of voltage VDDHG from voltage VEE 1Get back to till the timing of voltage VEE during as gate lines G 1Pixel selection during.Gate lines G 1The timing of getting back to voltage VEE is a gate lines G 1, G 2Short circuit during finish the back, the timing after having passed through during the predetermined OFF-OFF.Because the voltage by gate line is set at conducting state with the TFT that pixel had, so, gate lines G 1, G 2Short circuit during the back, gate lines G 1The source electrode line voltage that is changed to the timing of voltage VEE (low potential side voltage) is written into by gate lines G 1The pixel electrode of the pixel of selecting.Promptly, by gate lines G 1Write gray scale voltage in the pixel electrode of the pixel of selecting, therefore, source electrode driver 20 is at least in gate lines G 1, G 2Short circuit during finish the back, to through till after during the predetermined OFF-OFF, need to keep luma data GD 1Pairing gray scale voltage.Like this, even if because gate lines G 1, G 2Short circuit cause repeating during the pixel selection, can not make the image quality deterioration yet.
Similarly, work as gate lines G 2The selection signal be the H level after, control signal SWC 2Be the H level, and make gate lines G 2, G 3Short circuit.Gate lines G consequently 2And gate lines G 3Be same potential.Afterwards, control signal SWC 2Be the L level, and to gate lines G 3The selection signal of output H level.Thus, at electric charge again between period of use, gate lines G 2Can not discharge and recharge from the outside under the situation of electric charge, making voltage only change current potential from voltage VDDHG to gate lines G 2, G 3Short circuit after the voltage Δ VG1 of current potential.In addition, at this electric charge again between period of use, gate lines G 3Can not discharge and recharge from the outside under the situation of electric charge, making voltage only change current potential from voltage VEE to gate lines G 2, G 3Short circuit after the voltage Δ VG2 of current potential.Therefore, can cut down and make gate lines G 2, G 3The voltage quantity of electric charge that discharge and recharge when changing, so can cut down amount of power consumption.
Here, with gate lines G 2Be changed to the gate lines G that is timed to of voltage VDDHG from voltage VEE 2Get back to till the timing of voltage VEE during as gate lines G 2Pixel selection during.Gate lines G 2The timing of getting back to voltage VEE is a gate lines G 2, G 3Short circuit during finish the back, the timing after having passed through during the predetermined OFF-OFF.Voltage by gate line is set at conducting state with the TFT that pixel had, so, gate lines G 2, G 3Short circuit during the back, gate lines G 2The source electrode line voltage that is changed in the timing of voltage VEE (low potential side voltage) is written into by gate lines G 2The pixel electrode of the pixel of selecting.Promptly, by gate lines G 2Write gray scale voltage in the pixel electrode of the pixel of selecting, therefore, source electrode driver 20 is at least in gate lines G 2, G 3Short circuit during finish the back, during the predetermined OFF-OFF through after till, need to keep the pairing gray scale voltage of luma data GD2.Like this, even if because gate lines G 2, G 3Short circuit cause repeating during the pixel selection, can not make the image quality deterioration yet.
Below, gate lines G 3～G MCarry out the utilization again of electric charge similarly.
As mentioned above, can be according to present embodiment in gate lines G 1Rising edge, the gate lines G of selection signal 2～G M-1The rising edge of selection signal and negative edge, gate lines G MThe rising edge of selection signal, utilize electric charge again, thereby do not discharging and recharging from the outside under the situation of electric charge, make and select the level of signal to change.Therefore, can cut down and make gate lines G 1～G MThe voltage quantity of electric charge that discharge and recharge when changing, cut down amount of power consumption.
4. variation
In the present embodiment, as shown in Figure 1, liquid-crystal apparatus 10 is the structure that comprises display controller 40, and still, display controller 40 also can be arranged at the outside of liquid-crystal apparatus 10.Perhaps, liquid-crystal apparatus 10 comprises display controller 40 and main frame together.In addition, part or all of source electrode driver 20, gate drivers 30, display controller 40, power circuit 50 is formed on the display panel 12.Perhaps, has only transistor Q 1～Q M-1Be formed on the display panel 12, other circuit of the output buffer 36 of gate drivers 30 are arranged at the outside of display panel 12, wherein, and transistor Q 1～Q M-1Gate line circuit as the first～the (M-1) of the output buffer 36 of gate drivers 30.
Figure 11 is the block diagram of other structure example of liquid-crystal apparatus in the variation of present embodiment.
In Figure 11, the part identical with Fig. 1 marked identical symbol, and suitably omitted the explanation to it.In this variation, (on the display panel substrate) is formed with the display driver 60 that comprises source electrode driver 20, gate drivers 30 and power circuit 50 on display panel 12.Like this, display panel 12 can constitute and comprise: many gate lines, many source electrode lines, a plurality of pixels (pixel electrode), the source electrode driver that is used to drive many source electrode lines that are connected with each source electrode line of each gate lines of many gate lines and many source electrode lines, the gate drivers that is used to scan many gate lines.Form zone 44 in the pixel of display panel 12 and be formed with a plurality of pixels.Each pixel can comprise and is connected with the TFT that is connected with gate line on source electrode line, the grid on the source electrode; And the pixel electrode that connects in the drain electrode of this TFT.
In addition, in Figure 11, also can be on display panel 12, to have omitted in gate drivers 30 and the power circuit 50 at least-individual structure.
2, electronic equipment
Figure 12 has been to use the structure example block diagram of the electronic equipment of the gate drivers in present embodiment or the variation.Here, show the structure example block diagram of pocket telephone as electronic equipment.
Pocket telephone 900 comprises camera module 910.Camera module 910 comprises ccd video camera, offers display controller 540 by the ccd video camera shot image data with yuv format.Display controller 540 has the function of the display controller 40 of Fig. 1 or Figure 11.
Pocket telephone 900 comprises display panel 512.Display panel 512 is driven by source electrode driver 520 and gate drivers 530.Display panel 512 comprises many gate lines, many source electrode lines, a plurality of pixel.Display panel 512 has the function of the display panel 12 of Fig. 1 or Figure 11.
Display controller 540 is connected in source electrode driver 520 and gate drivers 530, and the luma data of rgb format is provided to source electrode driver 520.
Power circuit 542 is connected in source electrode driver 520 and gate drivers 530, and the supply voltage that drives usefulness is provided to each driver.Power circuit 542 has the function of the power circuit 50 of Fig. 1 or Figure 11.Comprise source electrode driver 520, gate drivers 530 and power circuit 542 as display driver 544, this display driver 544 can drive display panel 512.
Main frame 940 is connected in display controller 540.Main frame 940 control display controllers 540.In addition, main frame 940 offers display controller 540 after the luma data that receives by antenna 960 can being carried out demodulation by modulator-demodular unit 950.Display controller 540 is shown on display panel 512 by source electrode driver 520 and gate drivers 530 based on this luma data.Source electrode driver 520 has the function of the source electrode driver 20 of Fig. 1 or Figure 11.Gate drivers 530 has the function of the gate drivers 30 of Fig. 1 or Figure 11.
The luma data that main frame 940 can be generated camera module 910 sends to other communicators by antenna 960 indications after department of modulation and demodulation 950 is modulated.
Main frame 940 carries out the transmission-reception processing of luma data, the shooting of camera module 910, the display process of display panel 512 based on the operation information from operation inputting part 970.
And the present invention is not limited to the foregoing description, can various modification in invention aim scope of the present invention.For example, the present invention not merely is applicable to the driving of above-mentioned display panels, also goes for the driving of electroluminescence, plasma display system.
In addition, in the related technical scheme of dependent claims, can be the structure of omitting the structure important document part of the claim of being quoted in the present invention.In addition, the portion that of the related technical scheme of independent claims of the present invention 1 also can be subordinated to other independent claims.
Description of reference numerals
10 liquid-crystal apparatus, 12 display floaters
20 source electrode drivers 22,32 shift registers
24,26 line latch, 27 reference voltage generating circuits
28DAC 29 source electrode line drive circuits
30 grid drivers, 32 shift registers
34 level shifters, 36 output buffers
40 display controllers, 50 power circuits
52 positive direction twice booster circuits, 54 scanning voltage generative circuits
56 opposed electrode voltage generative circuits, 60 display floaters
CE opposite electrode G1～GM gate line
G1CNT～GMCNT、SWC1～SWCM-1、XG1CNT～XGMCNT
Control signal
GO1～GOM grid output circuit S1～SN source electrode line
SW1p～SWMp p type MOS transistor
Q1～QM-1, SW1n～SWMn n type MOS transistor

Claims (15)

1. gate drivers is used for first and second gate line of scan light electric installation, it is characterized in that, comprising:
The first grid output circuit, output is used to select the selection signal of described first grid polar curve;
The second grid output circuit, during the next one during the selection of described first grid polar curve was selected, output was used to select the selection signal of described second grid line; And
First grid polar curve short circuit current is arranged between the output of described first and second grid output circuit,
Wherein, described first grid polar curve short circuit current makes the output short-circuit of described first and second grid output circuit during the selection of described first grid polar curve and between during the selection of described second grid line.
2. gate drivers according to claim 1 is characterized in that, each grid output circuit of described first and second grid output circuit comprises:
First on-off circuit is arranged between the output of non-selection voltage with power lead and this grid output circuit of the non-selection voltage that provides gate line; And the second switch circuit, be arranged at the selection voltage that provides the selection of gate line voltage and use between power lead and this grid output circuit,
Wherein, described first and second on-off circuit be nonconducting state during after, one of them of described first and second on-off circuit is set at conducting state.
3. gate drivers according to claim 1 and 2 is characterized in that:
Described first grid polar curve short circuit current is a transistor,
During the non-selection of described first and second gate line, carry out grid control so that described transistor is a conducting state.
4. according to each described gate drivers in the claim 1 to 3, it is characterized in that: after during the short circuit of the output of described first and second grid output circuit, change in voltage at described first grid polar curve is the timing of low potential side voltage, writes the GTG signal in the selected pixel of described first grid polar curve.
5. an electrooptical device is characterized in that, comprising: many gate lines;
Many source electrode lines;
A plurality of pixels, each pixel is specified by each gate line and each source electrode line;
According to each described gate drivers in the claim 1 to 4, be used for scanning described at least first and second gate line of described many gate lines.
6. an electrooptical device is characterized in that, comprising:
Many gate lines;
Many source electrode lines;
A plurality of pixels, each pixel is specified by each gate line and each source electrode line;
First grid polar curve short circuit current, be arranged in described many gate lines first grid polar curve and then between the selecteed second grid line of this first grid polar curve,
Wherein, described first grid polar curve short circuit current during the selection of described first grid polar curve and between during the selection of described second grid line, makes described first and second gate line short circuit.
7. electrooptical device according to claim 6 is characterized in that,
Described first grid polar curve short circuit current is a transistor,
During the non-selection of described first and second gate line, carry out grid control so that described transistor is a conducting state.
8. according to claim 6 or 7 described electrooptical devices, it is characterized in that,
After during the short circuit of the output of described first and second grid output circuit, be the timing of low potential side voltage in the change in voltage of described first grid polar curve, in the selected pixel of described first grid polar curve, write the GTG signal.
9. according to each described electrooptical device in the claim 5 to 8, it is characterized in that, also comprise:
The first grid output circuit, output is used to select the selection signal of described first grid polar curve; And
The second grid output circuit, during the next one during the selection of described first grid polar curve was selected, output was used to select the selection signal of described second grid line.
10. according to each described electrooptical device in the claim 5 to 9, it is characterized in that, also comprise:
Source electrode driver is used for providing the GTG signal corresponding with each pixel to described many source electrode lines.
11. an electrooptical device is characterized in that, comprising:
According to each described gate drivers in the claim 1 to 4.
12. an electronic equipment is characterized in that, comprising:
According to each described gate drivers in the claim 1 to 4.
13. an electronic equipment is characterized in that: comprise according to each described electrooptical device in the claim 5 to 10.
14. a driving method is used for first and second gate line of scan light electric installation, it is characterized in that:
During the selection of described first grid polar curve, output is used to select the selection signal of this first grid polar curve,
During the selection of described first grid polar curve and between during the selection of described second grid line, make described first and second gate line short circuit,
Under the state of described first and second gate line, during the selection of described second grid line, output is used to select the selection signal of described second grid line after making first and second gate line short circuit, at electricity.
15. driving method according to claim 14, it is characterized in that: after described first and second gate line short circuit, change in voltage at described first grid polar curve is the timing of low potential side voltage, writes the GTG signal in the pixel of described first grid line options.
CNB2007101631330A 2006-10-10 2007-10-10 Gate drivers, electrooptical device, electronic equipment and driving method Expired - Fee Related CN100570457C (en)

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JP2006276049 2006-10-10
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102568409A (en) * 2010-12-15 2012-07-11 联咏科技股份有限公司 Gate driving method and device of liquid crystal display
US8896586B2 (en) 2010-12-15 2014-11-25 Novatek Microelectronics Corp. Gate driving method for controlling display apparatus and gate driver using the same
CN111681600A (en) * 2020-01-09 2020-09-18 友达光电股份有限公司 Display device
CN114550659A (en) * 2022-03-24 2022-05-27 京东方科技集团股份有限公司 Data voltage supply circuit, module, data driver and display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102568409A (en) * 2010-12-15 2012-07-11 联咏科技股份有限公司 Gate driving method and device of liquid crystal display
US8896586B2 (en) 2010-12-15 2014-11-25 Novatek Microelectronics Corp. Gate driving method for controlling display apparatus and gate driver using the same
CN111681600A (en) * 2020-01-09 2020-09-18 友达光电股份有限公司 Display device
CN114550659A (en) * 2022-03-24 2022-05-27 京东方科技集团股份有限公司 Data voltage supply circuit, module, data driver and display device
CN114550659B (en) * 2022-03-24 2023-10-24 京东方科技集团股份有限公司 Data voltage supply circuit, module, data driver and display device

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