CN111681600A

CN111681600A - Display device

Info

Publication number: CN111681600A
Application number: CN202010469842.7A
Authority: CN
Inventors: 陈冠勋; 黄郁升
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-01-09
Filing date: 2020-05-28
Publication date: 2020-09-18
Anticipated expiration: 2040-05-28
Also published as: TWI712022B; CN111681600B; TW202127418A

Abstract

The invention discloses a display device. The display device comprises a display array and a driving array. The display array has a plurality of pixel blocks, each including a receiving antenna for receiving a corresponding driving electromagnetic signal. The driving array is provided with a plurality of driving circuits, and each driving circuit comprises a transmitting antenna and a plurality of first impedance circuits. The transmit antenna is coupled to the receive antenna. The first impedance circuits are connected in parallel between the transmitting antenna and the first alternating current signal and respectively have different impedance values. At least one of the first impedance circuits is enabled to carry out amplitude adjustment on the first alternating current signal according to the impedance value and then transmit the first alternating current signal to the transmitting antenna.

Description

Display device

Technical Field

The present invention relates to a display device, and more particularly, to a display device for driving an electromagnetic signal through wireless signal transmission.

Background

At present, a wireless driving type display is developed, which divides a high-resolution passive matrix self-luminous display module into a plurality of low-resolution passive matrix self-luminous modules, each of which is called a block. All sub-pixels in the same block receive signals through the same data coil, and the head end and the tail end of the coil are respectively connected into the passive matrix through switches in the X direction or the Y direction.

Due to the time limitation, the number of gray scales that can be extracted within one pixel scan time (line time) is insufficient, resulting in a decrease in contrast. In other words, since each frame update frequency is at least 60 hertz (Hz), and one scan of all the sub-pixels in each block needs to be completed within a limited time, the 1Y-direction switching time is about 1/(nX × mY × T) second, where n is the number of X-direction switches, m is the number of Y-direction switches, and T is the scan time of each pixel. Moreover, the higher the update frequency and the higher the resolution controlled by each block, the limited number of pulses received by the data coil in each scanning time, so that the number of gray scales is insufficient.

Disclosure of Invention

The invention provides a display device, which can increase the order of a driving electromagnetic signal between a pixel block and a driving circuit.

The display device comprises a display array and a driving array. The display array has a plurality of pixel blocks, each including a receiving antenna for receiving a corresponding driving electromagnetic signal. The driving array is provided with a plurality of driving circuits, and each driving circuit comprises a transmitting antenna and a plurality of first impedance circuits. The transmit antenna is coupled to the receive antenna. The first impedance circuits are connected in parallel between the transmitting antenna and the first alternating current signal and respectively have different impedance values. At least one of the first impedance circuits is enabled to carry out amplitude adjustment on the first alternating current signal according to the impedance value and then transmit the first alternating current signal to the transmitting antenna.

Based on the above, the display device according to the embodiment of the invention can have more stages of driving electromagnetic signals generated by the transmitting antenna by adjusting the amplitude, that is, the contrast of the pixels in each pixel block can be improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a system diagram of a display device according to an embodiment of the invention.

Fig. 2 is a circuit diagram of a pixel block and a driving circuit according to an embodiment of the invention.

Fig. 3A to 3C are schematic diagrams of output waveforms of a driving circuit according to an embodiment of the invention.

Fig. 4 is a circuit diagram of a pixel block and a driving circuit according to another embodiment of the invention.

Fig. 5 is a circuit diagram of a pixel block according to an embodiment of the invention.

Wherein, the reference numbers:

10: display device

20: display array

21: pixel block

21 a: pixel

100: driving array

110. 110 a: driving circuit

111. 111 a: drive signal generating circuit

113. 113 a: control signal generating circuit

ARX: receiving antenna

ATX: transmission antenna

B1: first bit part

B2: second bit portion

CMR 11-CMR 13, CMR 21-CMR 23: impedance matching circuit

CPX: pixel capacitance

CTR 11-CTR 13: first impedance circuit

CTR 21-CTR 23: second impedance circuit

DDX: displaying data

Even _ CK: the second clock signal

M11, M21, M31, M41, M51, M61: first switch

M12, M22, M32, M42, M52, M62: second switch

Odd _ CK: a first clock signal

OLD: light emitting element

SAC1, XSAC 1: a first AC signal

SAC2, XSAC 2: second alternating current signal

SC 11-SC 13: a first control signal

SC 21-SC 23: the second control signal

And (3) SDM: driving electromagnetic signals

T1, T3: transistor with a metal gate electrode

T2, T4: time pulse switch

TX1 TX4, TX: first axial switch

TY 1-TY 4, TY: second axial switch

VCOM: common voltage

X1-X4, Xm: first axial control signal

Y1-Y4, Yn: second axial control signal

Detailed Description

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a system diagram of a display device according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, a display device 10 includes a display array 20 and a driving array 100. The display array 20 includes a plurality of pixel blocks 21 arranged in an array, and the driving array 100 includes a plurality of driving circuits 110 arranged in an array.

Fig. 2 is a circuit diagram of a pixel block and a driving circuit according to an embodiment of the invention. Referring to fig. 1 and fig. 2, in the present embodiment, each pixel block 21 includes a receiving antenna ARX, a plurality of light emitting elements OLD (e.g., organic light emitting diodes, micro light emitting diodes, sub-millimeter light emitting diodes), a plurality of first axial switches (e.g., TX 1-TX 4), and a plurality of second axial switches (e.g., TY 1-TY 4). The receiving antenna ARX is arranged to receive the corresponding driving electromagnetic signal SDM. First ends of the first axial switches (e.g., TX 1-TX 4) are coupled to a first end of the receiving antenna ARX, second ends of the first axial switches (e.g., TX 1-TX 4) are coupled to a cathode end of the corresponding light emitting element OLD, and the first axial switches (e.g., TX 1-TX 4) are controlled by corresponding first axial control signals (e.g., X1-X4) to be turned on or off. The first terminals of the second axial switches (e.g., TY 1-TY 4) are commonly coupled to the second terminal of the receiving antenna ARX, the second terminals of the second axial switches (e.g., TY 1-TY 4) are coupled to the cathode terminal of the corresponding light emitting element OLD, and the second axial switches (e.g., TY 1-TY 4) are controlled by corresponding second axial control signals (e.g., Y1-Y4) to be turned on or off.

Each of the driving circuits 110 includes a transmission antenna ATX, a plurality of first impedance circuits CTR11 to CTR13, a driving signal generating circuit 111, and a control signal generating circuit 113. The driving signal generating circuit 111 receives the display data DDX to generate a first ac signal SAC 1. The control signal generating circuit 113 receives the display data DDX to generate first control signals SC 11-SC 13.

The transmitting antenna ATX is used to couple with the receiving antenna ARX, i.e. to generate the driving electromagnetic signal SDM. The first impedance circuits CTR 11-CTR 13 are connected in parallel between a first terminal of the transmitting antenna ATX and the first ac signal SAC1, and have different impedance values, respectively, wherein the first terminal of the transmitting antenna ATX is coupled to a reference voltage (e.g., a ground voltage).

The first impedance circuits CTR 11-CTR 13 respectively receive the first control signals SC 11-SC 13 to be enabled in response to the corresponding first control signals SC 11-SC 13. In other words, at least one of the first impedance circuits CTR 11-CTR 13 is enabled to transmit the first ac signal SAC1 to the transmitting antenna ATX after amplitude adjustment according to the impedance value. Therefore, through the adjustment of the amplitude, the driving electromagnetic signals generated by the transmitting antenna can have more steps, namely, the contrast of the pixels in each pixel block can be improved.

In the embodiment of the invention, only one of the first impedance circuits CTR 11-CTR 13 may be enabled, so that the first ac signal SAC1 is amplitude-adjusted according to the impedance value and then transmitted to the transmitting antenna ATX. Alternatively, one, two, …, or all of the first impedance circuits CTR 11-CTR 13 may be enabled to amplitude-adjust the first ac signal SAC1 according to the impedance value thereof and transmit the adjusted first ac signal to the transmitting antenna ATX.

In the embodiment of the present invention, the driving signal generating circuit 111 may generate the first ac signal SAC1 with reference to the first bit portion B1 of the display data DDX, and the control signal generating circuit 113 generates the first control signals SC 11-SC 13 with reference to the second bit portion B2 of the display data DDX. The first bit portion B1 is, for example, an upper bit portion, and the second bit portion B2 is, for example, a lower bit portion. In the embodiment of the present invention, the first bit-portion B1 may not overlap the second bit-portion B2, or the first bit-portion B1 may overlap the second bit-portion B2, which may depend on the circuit design.

The first impedance circuits CTR 11-CTR 13 respectively include impedance matching circuits (e.g., CMR 11-CMR 13), first switches (e.g., M11, M21, M31), and second switches (e.g., M12, M22, M32), wherein the impedance matching circuits CMR 11-CMR 13 have corresponding impedance values (i.e., have different impedance values). Taking the first impedance circuit CTR11 as an example, the first switch M11 is disposed between the first ac signal SAC1 and the impedance matching circuits CMR11 to CMR13, and is controlled to be turned on by the corresponding first control signals SC11 to SC 13; the second switch M12 is disposed between the impedance matching circuits CMR 11-CMR 13 and the first end of the transmitting antenna ATX, and is controlled to be turned on by the corresponding first control signals SC 11-SC 13.

With the present embodiment, the impedance matching circuits CMR 11-CMR 13 may be purely resistive, purely capacitive, purely inductive, or any combination thereof. In other words, the impedance matching circuits CMR 11-CMR 13 may be a resistance-inductance-capacitance circuit (i.e., including at least one resistor, at least one capacitor, and at least one inductor), a resistance circuit (i.e., including at least one resistor), a capacitance circuit (i.e., including at least one capacitor), or an inductance circuit (i.e., including at least one inductor), but the embodiments of the invention are not limited thereto. The resistor, the capacitor and/or the inductor are used for forming corresponding impedance values.

Fig. 3A to 3C are schematic diagrams of output waveforms of a driving circuit according to an embodiment of the invention. Referring to fig. 2 and fig. 3A to fig. 3C, in the embodiment, the first ac signal SAC1 is a sine wave signal, but the embodiment of the invention is not limited thereto. The impedance value of the impedance matching circuit CMR11 is zero with respect to the frequency of the first ac signal SAC1, the impedance value of the impedance matching circuit CMR12 is higher than that of the impedance matching circuit CMR11, and the impedance value of the impedance matching circuit CMR13 is the highest.

As shown in fig. 3A, the first control signal SC11 is enabled, the first control signals SC12 and SC13 are disabled, that is, the first ac signal SAC1 is transmitted only to the impedance matching circuit CMR11 of the first impedance circuit CTR11, and the first ac signal XSAC1 with its amplitude adjusted by the impedance matching circuit CMR11 has a larger amplitude, that is, the first ac signal SAC1 overlaps with the waveform of the first ac signal XSAC 1.

As shown in fig. 3B, the first control signal SC12 is enabled, the first control signals SC11 and SC13 are disabled, that is, the first ac signal SAC1 is transmitted only to the impedance matching circuit CMR12 of the first impedance circuit CTR12, and the first ac signal XSAC1 with its amplitude adjusted by the impedance matching circuit CMR12 has a smaller amplitude, that is, the first ac signal SAC1 and the first ac signal XSAC1 do not have overlapping waveforms and the amplitude of the first ac signal XSAC1 is smaller than that of the first ac signal SAC1 (as shown by the dashed line).

As shown in fig. 3C, the first control signal SC13 is enabled, the first control signals SC11 and SC12 are disabled, that is, the first ac signal SAC1 is transmitted only to the impedance matching circuit CMR13 of the first impedance circuit CTR13, and the amplitude of the first ac signal XSAC1 adjusted by the impedance matching circuit CMR13 has the minimum amplitude, that is, the waveforms of the first ac signal SAC1 and the first ac signal XSAC1 are not overlapped and the amplitude of the first ac signal XSAC1 is smaller than the first ac signal SAC1 (shown by the dotted line) and the first ac signal XSAC1 shown in fig. 3B.

In the above embodiments, three first impedance circuits (e.g., CTR 11-CTR 13) are illustrated, but in other embodiments, any number of first impedance circuits may be provided. In addition, in the above embodiments, one of the first control signals SC 11-SC 13 is enabled, that is, the first ac signal SAC1 is only amplitude-adjusted by one of the impedance matching circuits CMR 11-CMR 13, but in other embodiments, any two or all of the first control signals SC 11-SC 13, that is, the first ac signal SAC1 is amplitude-adjusted by any two or all of the impedance matching circuits CMR 11-CMR 13, may be enabled.

Fig. 4 is a circuit diagram of a pixel block and a driving circuit according to another embodiment of the invention. Referring to fig. 2 and 4, the driving circuit 110a is substantially the same as the driving circuit 110, except that the driving circuit 110a further includes a plurality of second impedance circuits CTR 21-CTR 23. In the embodiment, the driving signal generating circuit 111a generates the second ac signal SAC2 in response to the first bit portion B1 of the display data DDX, and the control signal generating circuit 113a generates the plurality of second control signals SC 21-SC 23 in response to the second bit portion B2 of the display data DDX. The second impedance circuits CTR 21-CTR 23 respectively receive one of the second control signals SC 21-SC 23 and are enabled by being controlled by the corresponding second control signals SC 21-SC 23.

The second impedance circuits CTR 21-CTR 23 are connected in parallel between the first end of the transmitting antenna ATX and the second ac signal SAC2 and have different impedance values, i.e., the first impedance circuits CTR 11-CTR 13 and the second impedance circuits CTR 21-CTR 23 have different impedance values.

In the present embodiment, the driving signal generating circuit 111a generates the first ac signal SAC1 and/or the second ac signal SAC2 in response to the first bit portion B1 of the display data DDX, wherein the first ac signal SAC1 and the second ac signal SAC2 may have different frequencies or different time lengths. In addition, the control signal generating circuit 113a enables one, part or all of the first control signals SC11 SC13 and the second control signals SC21 SC23 in response to the second bit portion B2 of the display data DDX.

The enabled first impedance circuits (e.g., CTR 11-CTR 13) are configured to transmit the first ac signal SAC1 to the transmitting antenna ATX after amplitude adjustment according to the impedance value (i.e., the first ac signal XSAC1), and the enabled second impedance circuits (e.g., CTR 21-CTR 23) are configured to transmit the second ac signal SAC2 to the transmitting antenna ATX after amplitude adjustment according to the impedance value (i.e., the second ac signal XSAC 2). In the present embodiment, the second impedance circuits (e.g., CTR 21-CTR 23) may have the same structure as the first impedance circuits (e.g., CTR 11-CTR 13), i.e., the second impedance circuits (e.g., CTR 21-CTR 23) respectively include impedance matching circuits (e.g., CMR 21-CMR 23), first switches (e.g., M41, M51, M61), and second switches (e.g., M42, M52, M62), wherein the impedance matching circuits CMR 21-CMR 23 have corresponding impedance values (i.e., have different impedance values).

Fig. 5 is a circuit diagram of a pixel block according to an embodiment of the invention. Referring to fig. 1 and 5, in the present embodiment, the pixel block 21 includes a plurality of pixels 21 a. The pixel 21a includes a receiving antenna ARX, a plurality of diodes (e.g., diode-connected transistors T1 and T3), a plurality of clock switches (e.g., T2 and T4), a first axial switch TX, a second axial switch TY, and a pixel capacitor CPX. The receiving antenna ARX is used for receiving the corresponding driving electromagnetic signal.

A first terminal of the transistor T1 is coupled to a first terminal of the receiving antenna ARX. The first terminal of the clock switch T2 is coupled to the second terminal of the transistor T1, and the control terminal of the clock switch T2 receives the first clock signal Odd _ CK. The second terminal of the reception antenna ARX receives the common voltage VCOM. A first terminal of the transistor T3 is coupled to a first terminal of the receiving antenna ARX. The first terminal of the clock switch T4 is coupled to the second terminal of the transistor T3, the control terminal of the clock switch T4 receives the second clock signal Even _ CK, and the second terminal of the clock switch T4 is coupled to the second terminal of the clock switch T2, wherein the enabled period of the first clock signal Odd _ CK is not overlapped with the enabled period of the second clock signal Even _ CK, or the first clock signal Odd _ CK and the second clock signal Even _ CK are opposite in phase.

The first end of the first axial switch TX is coupled to the second end of the clock switch T2, and the first axial switch TX is controlled by the corresponding first axial control signal Xm to be turned on or off. A first terminal of the second axial switch TY is coupled to the second terminal of the first axial switch TX, a second terminal of the second axial switch TY is coupled to the first terminal of the pixel capacitor CPX, and the second axial switch TY is controlled by a corresponding second axial control signal Yn to be turned on or off. The second terminal of the pixel capacitor CPX receives the common voltage VCOM.

In one embodiment, the receiving antenna ARX, the diodes (e.g., diode-connected transistors T1 and T3) and the clock switches (e.g., T2 and T4) may be common to all of the pixels 21a at the pixel block 21, i.e., each pixel 21a may include only the first axial switch TX, the second axial switch TY and the pixel capacitor CPX.

In summary, the display device according to the embodiment of the invention, through the adjustment of the amplitude, the driving electromagnetic signal generated by the transmitting antenna can have more stages, that is, the contrast of the pixels in each pixel block can be improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising:

a display array having a plurality of pixel blocks, each of the pixel blocks including a receiving antenna for receiving a corresponding driving electromagnetic signal;

a driver array having a plurality of driver circuits, each of the driver circuits comprising:

a transmitting antenna coupled to the receiving antenna;

the first impedance circuits are connected in parallel between the transmitting antenna and the first alternating current signal and respectively have different impedance values, wherein at least one of the first impedance circuits is enabled to carry out amplitude adjustment on the first alternating current signal according to the impedance value and then transmit the first alternating current signal to the transmitting antenna.

2. The display device according to claim 1, wherein the first impedance circuits receive a plurality of first control signals to be enabled in response to the corresponding first control signals.

3. The display device according to claim 2, wherein the first impedance circuits respectively comprise:

an impedance matching circuit having a corresponding impedance value;

a first switch configured between the first alternating current signal and the impedance matching circuit and controlled by a corresponding first control signal to be conducted; and

and the second switch is configured between the impedance matching circuit and the transmitting antenna and is controlled by the corresponding first control signal to be conducted.

4. The display device of claim 3, wherein the impedance matching circuit is a resistor inductor capacitor circuit.

5. The display device according to claim 3, wherein the impedance matching circuit comprises a capacitor for forming the corresponding impedance value.

6. The display device of claim 3, further comprising:

a driving signal generating circuit for receiving a display data to generate the first AC signal; and

and the control signal generating circuit receives the display data to generate the first control signals.

7. The display device according to claim 6, wherein the driving signal generating circuit generates the first AC signal with reference to a first bit portion of the display data, and the control signal generating circuit generates the first control signals with reference to a second bit portion of the display data.

8. The display device of claim 7, wherein the first bit portion is a high bit portion and the second bit portion is a low bit portion.

9. The display device of claim 7, wherein the first bit portion and the second bit portion do not overlap.

10. The display device of claim 7, wherein the first bit portion partially overlaps the second bit portion.

11. The display device of claim 6, wherein the driving signal generating circuit further generates a second AC signal in response to the display data, and the control signal generating circuit further generates a plurality of second control signals in response to the display data,

wherein the display device further comprises a plurality of second impedance circuits, each of which is enabled by being controlled by a corresponding second control signal, is connected in parallel between the transmitting antenna and the second alternating current signal and has different impedance values,

at least one of the first impedance circuits and the second impedance circuits is enabled to transmit the first alternating current signal and the second alternating current signal to the transmitting antenna after amplitude adjustment is carried out on the first alternating current signal and the second alternating current signal according to the impedance value.

12. The display device of claim 11, wherein the first ac signal is a sine wave signal.

13. The display device according to claim 1, wherein one of the first impedance circuits is enabled to transmit the first ac signal to the transmitting antenna after performing amplitude adjustment according to the impedance value.

14. The display device according to claim 1, wherein the first ac signal is a sine wave signal.