CN111681600A - Display device - Google Patents

Abstract

The invention discloses a display device. The display device comprises a display array and a driving array. The display array has a plurality of pixel blocks, each including a receiving antenna for receiving a corresponding driving electromagnetic signal. The driving array is provided with a plurality of driving circuits, and each driving circuit comprises a transmitting antenna and a plurality of first impedance circuits. The transmit antenna is coupled to the receive antenna. The first impedance circuits are connected in parallel between the transmitting antenna and the first alternating current signal and respectively have different impedance values. At least one of the first impedance circuits is enabled to carry out amplitude adjustment on the first alternating current signal according to the impedance value and then transmit the first alternating current signal to the transmitting antenna.

Description

display device

technical field

The present invention relates to a display device, and more particularly, to a display device that transmits driving electromagnetic signals through wireless signals.

Background technique

At present, a wireless driving mode display has been developed, which splits the high-resolution passive matrix self-illuminating display module into many low-resolution passive matrix self-illuminating modules, and each low-resolution passive matrix self-illuminating module is called a zone. piece. All sub-pixels in the same block receive signals through the same data coil, and both ends of the coil are connected to the passive matrix through switches in the X or Y direction.

Due to the limitation of time, the number of gray scales that can be cut out within one pixel scan time (line time) is insufficient, resulting in a decrease in contrast. In other words, since the update frequency of each picture is at least 60 hertz (Hz), and one scan of all sub-pixels in each block needs to be completed within a limited time, the switching time of one Y direction is about 1/(nX* mY*T) seconds, where n is the number of switches in the X direction, m is the number of switches in the Y direction, and T is the scan time per pixel. In addition, the higher the update frequency and the higher the resolution controlled by each block, the limited number of pulse waves received by the data coil in each scan time, resulting in insufficient number of gray scales.

SUMMARY OF THE INVENTION

The present invention provides a display device capable of increasing the order of driving electromagnetic signals between the pixel block and the driving circuit.

The display device of the present invention includes a display array and a driving array. The display array has a plurality of pixel blocks, each of which includes a receiving antenna for receiving corresponding driving electromagnetic signals. The driving array has a plurality of driving circuits, and each driving circuit includes a transmission antenna and a plurality of first impedance circuits. The transmit antenna is coupled with the receive antenna. The first impedance circuit is connected in parallel between the transmission antenna and the first AC signal, and each has different impedance values. At least one of the first impedance circuits is enabled to adjust the amplitude of the first AC signal according to the impedance value it has, and then transmit the first AC signal to the transmission antenna.

Based on the above, in the display device according to the embodiment of the present invention, by adjusting the amplitude, the driving electromagnetic signal generated by the transmission antenna can have more orders, that is, the contrast ratio of the pixels in each pixel block can be improved.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a system schematic diagram of a display device according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a pixel block and a driving circuit according to an embodiment of the present invention.

3A to 3C are schematic diagrams of output waveforms of a driving circuit according to an embodiment of the present invention.

FIG. 4 is a schematic circuit diagram of a pixel block and a driving circuit according to another embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a pixel block according to an embodiment of the present invention.

Among them, reference numerals:

10: Display device

20: Display array

21: Pixel block

21a: Pixels

100: drive array

110, 110a: drive circuit

111, 111a: drive signal generating circuit

113, 113a: control signal generating circuit

ARX: Receive Antenna

ATX: transmit antenna

B1: The first element part

B2: Second bit part

CMR11～CMR13, CMR21～CMR23: Impedance matching circuit

CPX: pixel capacitance

CTR11 to CTR13: first impedance circuit

CTR21～CTR23: The second impedance circuit

DDX: Display data

Even_CK: the second clock signal

M11, M21, M31, M41, M51, M61: the first switch

M12, M22, M32, M42, M52, M62: Second switch

Odd_CK: the first clock signal

OLD: Light-emitting element

SAC1, XSAC1: the first AC signal

SAC2, XSAC2: Second AC signal

SC11～SC13: The first control signal

SC21～SC23: The second control signal

SDM: drive electromagnetic signal

T1, T3: transistors

T2, T4: clock switch

TX1～TX4, TX: The first axial switch

TY1～TY4, TY: The second axial switch

VCOM: common voltage

X1～X4, Xm: The first axis control signal

Y1～Y4, Yn: The second axis control signal

Detailed ways

The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprising" and/or "comprising" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but do not exclude one or more The presence or addition of other features, entireties of regions, steps, operations, elements, components, and/or combinations thereof.

FIG. 1 is a system schematic diagram of a display device according to an embodiment of the present invention. Referring to FIG. 1 , in this embodiment, the display device 10 includes a display array 20 and a driving array 100 . The display array 20 includes a plurality of pixel blocks 21 arranged in an array, and the driving array 100 includes a plurality of driving circuits 110 arranged in an array.

FIG. 2 is a schematic circuit diagram of a pixel block and a driving circuit according to an embodiment of the present invention. Referring to FIGS. 1 and 2 , in this embodiment, each pixel block 21 includes a receiving antenna ARX, a plurality of light-emitting elements OLD (eg, organic light-emitting diodes, micro-light-emitting diodes, sub-millimeter light-emitting diodes), a plurality of first axes direction switches (such as TX1 to TX4) and multiple second axial switches (such as TY1 to TY4). The receiving antenna ARX is used for receiving the corresponding driving electromagnetic signal SDM. The first ends of the first axial switches (such as TX1-TX4) are coupled to the first end of the receiving antenna ARX, and the second ends of the first axial switches (such as TX1-TX4) are coupled to the corresponding light-emitting elements The cathode terminal of OLD, and these first axial switches (eg, TX1 ˜ TX4 ) are controlled by the corresponding first axial control signals (eg, X1 ˜ X4 ) to be turned on or off. The first ends of these second axial switches (such as TY1-TY4) are commonly coupled to the second end of the receiving antenna ARX, and the second ends of each of the second axial switches (such as TY1-TY4) are coupled to the corresponding light-emitting device The cathode terminal of the element OLD, and these second axial switches (eg TY1 - TY4 ) are controlled by the corresponding second axial control signals (eg Y1 - Y4 ) to be turned on or off.

Each driving circuit 110 includes a transmission antenna ATX, a plurality of first impedance circuits CTR11 to CTR13 , a driving signal generating circuit 111 and a control signal generating circuit 113 . The driving signal generating circuit 111 receives the display data DDX to generate the first AC signal SAC1. The control signal generating circuit 113 receives the display data DDX to generate the first control signals SC11 ˜ SC13 .

The transmitting antenna ATX is used for coupling with the receiving antenna ARX, that is, for generating the driving electromagnetic signal SDM. The first impedance circuits CTR11-CTR13 are connected in parallel between the first end of the transmission antenna ATX and the first AC signal SAC1, and have different impedance values respectively, wherein the first end of the transmission antenna ATX is coupled to a reference voltage (eg, ground voltage) .

The first impedance circuits CTR11 - CTR13 respectively receive the first control signals SC11 - SC13 and are enabled in response to the corresponding first control signals SC11 - SC13 . In other words, at least one of the first impedance circuits CTR11 to CTR13 is enabled to adjust the amplitude of the first AC signal SAC1 according to the impedance value it has, and then transmit it to the transmission antenna ATX. Thereby, by adjusting the amplitude, the driving electromagnetic signal generated by the transmitting antenna can have more orders, that is, the contrast ratio of the pixels in each pixel block can be improved.

In the embodiment of the present invention, only one of the first impedance circuits CTR11 to CTR13 may be enabled to adjust the amplitude of the first AC signal SAC1 according to the impedance value it has, and then transmit it to the transmission antenna ATX. Alternatively, one, two, .

In the embodiment of the present invention, the driving signal generating circuit 111 may generate the first AC signal SAC1 with reference to the first bit portion B1 of the display data DDX, and the control signal generating circuit 113 may generate the first AC signal SAC1 with reference to the second bit portion B2 of the display data DDX The first control signals SC11 to SC13. The first bit portion B1 is, for example, an upper bit portion, and the second bit portion B2 is, for example, a lower bit portion. In the embodiment of the present invention, the first bit portion B1 and the second bit portion B2 may not overlap, or the first bit portion B1 and the second bit portion B2 may partially overlap, which may be determined according to circuit design.

The first impedance circuits CTR11 to CTR13 respectively include impedance matching circuits (eg CMR11 to CMR13 ), first switches (eg M11 , M21 , M31 ), and second switches (eg M12 , M22 , M32 ), wherein the impedance matching circuits CMR11 to The CMRs 13 have corresponding impedance values (ie, have different impedance values). Taking the first impedance circuit CTR11 as an example, the first switch M11 is disposed between the first AC signal SAC1 and the impedance matching circuits CMR11-CMR13, and is controlled by the corresponding first control signals SC11-SC13 to be turned on; the second switch M11 is The M12 is disposed between the impedance matching circuits CMR11 - CMR13 and the first end of the transmission antenna ATX, and is controlled to be turned on by the corresponding first control signals SC11 - SC13 .

In the embodiment of the present invention, the impedance matching circuits CMR11 to CMR13 may be purely resistive, purely capacitive, purely inductive, or any combination of the above. In other words, the impedance matching circuits CMR11 to CMR13 may be resistor, inductor, capacitor circuits (ie, including at least one resistor, at least one capacitor, and at least one inductor), resistor circuits (ie, including at least one resistor), and capacitor circuits (ie, including at least one capacitor), or an inductive circuit (that is, including at least one inductor), but the embodiment of the present invention is not limited thereto. The resistance, capacitance and/or inductance are used to form corresponding impedance values.

3A to 3C are schematic diagrams of output waveforms of a driving circuit according to an embodiment of the present invention. Referring to FIG. 2 and FIGS. 3A to 3C , in this embodiment, the first AC signal SAC1 is a sine wave signal as an example, but the embodiment of the present invention is not limited to this. In addition, with respect to the frequency of the first AC signal SAC1, the impedance value of the impedance matching circuit CMR11 is zero, the impedance value of the impedance matching circuit CMR12 is higher than that of the impedance matching circuit CMR11, and the impedance value of the impedance matching circuit CMR13 is the highest.

As shown in FIG. 3A , the first control signal SC11 is enabled, and the first control signals SC12 and SC13 are disabled, that is, the first AC signal SAC1 is only transmitted to the impedance matching circuit CMR11 of the first impedance circuit CTR11 , and is passed through the impedance matching circuit The first AC signal XSAC1 whose amplitude is adjusted by the CMR11 has a larger amplitude, that is, the waveforms of the first AC signal SAC1 and the first AC signal XSAC1 overlap.

As shown in FIG. 3B , the first control signal SC12 is enabled, and the first control signals SC11 and SC13 are disabled, that is, the first AC signal SAC1 is only transmitted to the impedance matching circuit CMR12 of the first impedance circuit CTR12, and is passed through the impedance matching circuit The first AC signal XSAC1 whose amplitude is adjusted by the CMR12 has a smaller amplitude, that is, the waveforms of the first AC signal SAC1 and the first AC signal XSAC1 do not overlap and the amplitude of the first AC signal XSAC1 is smaller than that of the first AC signal SAC1 (as indicated by the dotted line). Show).

As shown in FIG. 3C , the first control signal SC13 is enabled, and the first control signals SC11 and SC12 are disabled, that is, the first AC signal SAC1 is only transmitted to the impedance matching circuit CMR13 of the first impedance circuit CTR13, and is passed through the impedance matching circuit The first AC signal XSAC1 whose amplitude is adjusted by the CMR13 has the smallest amplitude, that is, the waveforms of the first AC signal SAC1 and the first AC signal XSAC1 do not overlap and the amplitude of the first AC signal XSAC1 is smaller than that of the first AC signal SAC1 (as shown by the dotted line). ) and the first AC signal XSAC1 shown in FIG. 3B .

In the above embodiment, three first impedance circuits (eg, CTR11 - CTR13 ) are used as an example, but in other embodiments, there may be any number of first impedance circuits. Moreover, in the above-mentioned embodiment, one of the first control signals SC11 ˜ SC13 is enabled, that is, the first AC signal SAC1 is only adjusted in amplitude through one of the impedance matching circuits CMR11 ˜ CMR13 , but in other implementations For example, any two or all of the first control signals SC11 ˜ SC13 may be enabled, that is, the amplitude of the first AC signal SAC1 may be adjusted through any two or all of the impedance matching circuits CMR11 ˜ CMR13 .

FIG. 4 is a schematic circuit diagram of a pixel block and a driving circuit according to another embodiment of the present invention. Please refer to FIG. 2 and FIG. 4 , the driving circuit 110 a is substantially the same as the driving circuit 110 , except that the driving circuit 110 a further includes a plurality of second impedance circuits CTR21 ˜ CTR23 . In this embodiment, the driving signal generating circuit 111a further responds to the first bit portion B1 of the display data DDX to generate the second AC signal SAC2, and the control signal generating circuit 113a further responds to the second bit portion B2 of the display data DDX A plurality of second control signals SC21 to SC23 are generated. The second impedance circuits CTR21 - CTR23 respectively receive one of the second control signals SC21 - SC23 , and are controlled and enabled by the corresponding second control signals SC21 - SC23 .

The second impedance circuits CTR21-CTR23 are connected in parallel between the first end of the transmitting antenna ATX and the second AC signal SAC2, and have different impedance values respectively, namely the first impedance circuits CTR11-CTR13 and the second impedance circuits CTR21-CTR23 with different impedance values.

In this embodiment, the driving signal generating circuit 111a generates the first AC signal SAC1 and/or the second AC signal SAC2 in response to the first cell portion B1 of the display data DDX, wherein the first AC signal SAC1 and the second AC signal SAC2 Can have different frequencies or have different lengths of time. In addition, the control signal generating circuit 113a enables one, part or all of the first control signals SC11-SC13 and the second control signals SC21-SC23 in response to the second bit portion B2 of the display data DDX.

The enabled first impedance circuits (eg CTR11 to CTR13 ) are used to transmit the first AC signal SAC1 after amplitude adjustment according to the impedance value it has (ie, the first AC signal XSAC1 ) to the transmission antenna ATX, and the enabled The second impedance circuits (eg, CTR21 - CTR23 ) are used to transmit the second AC signal SAC2 after the amplitude adjustment according to the impedance value it has (ie, the second AC signal XSAC2 ) to the transmission antenna ATX. In this embodiment, the structures of the second impedance circuits (eg, CTR21 - CTR23 ) may be the same as the first impedance circuits (eg, CTR11 - CTR13 ), that is, the second impedance circuits (eg, CTR21 - CTR23 ) individually include impedance matching circuits ( Such as CMR21 ~ CMR23), the first switch (such as M41, M51, M61), and the second switch (such as M42, M52, M62), wherein the impedance matching circuits CMR21 ~ CMR23 have corresponding impedance values (that is, have different impedances value).

FIG. 5 is a schematic circuit diagram of a pixel block according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 5 , in this embodiment, the pixel block 21 includes a plurality of pixels 21 a. The pixel 21a includes a receiving antenna ARX, a plurality of diodes (such as diode-connected transistors T1 and T3), a plurality of clock switches (such as T2 and T4), a first axial switch TX, a second axial switch TY, and pixels Capacitor CPX. The receiving antenna ARX is used for receiving the corresponding driving electromagnetic signal.

The first end of the transistor T1 is coupled to the first end of the receiving antenna ARX. The first terminal of the clock switch T2 is coupled to the second terminal of the transistor T1, and the control terminal of the clock switch T2 receives the first clock signal Odd_CK. The second end of the receiving antenna ARX receives the common voltage VCOM. The first end of the transistor T3 is coupled to the first end of the receiving antenna ARX. The first terminal of the clock switch T4 is coupled to the second terminal of the transistor T3, the control terminal of the clock switch T4 receives the second clock signal Even_CK, and the second terminal of the clock switch T4 is coupled to the second terminal of the clock switch T2 , wherein the enabling period of the first clock signal Odd_CK does not overlap with the enabling period of the second clock signal Even_CK, or the first clock signal Odd_CK and the second clock signal Even_CK are mutually inverse.

The first end of the first axis switch TX is coupled to the second end of the clock switch T2, and the first axis switch TX is controlled to be turned on or off by the corresponding first axis control signal Xm. The first end of the second axis switch TY is coupled to the second end of the first axis switch TX, the second end of the second axis switch TY is coupled to the first end of the pixel capacitor CPX, and the second axis The switch TY is controlled to be turned on or off according to the corresponding second axial control signal Yn. The second terminal of the pixel capacitor CPX receives the common voltage VCOM.

In an embodiment, the receiving antenna ARX, the diodes (such as diode-connected transistors T1 and T3 ) and the clock switches (such as T2 and T4 ) in the pixel block 21 may be shared by all the pixels 21 a , that is, each The pixel 21a may only include the first axial switch TX, the second axial switch TY and the pixel capacitor CPX.

To sum up, in the display device of the embodiment of the present invention, by adjusting the amplitude, the driving electromagnetic signal generated by the transmission antenna can have more orders, that is, the contrast ratio of the pixels in each pixel block can be improved.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Claims (14)

1. A display device, characterized in that, comprising: a display array having a plurality of pixel blocks, each of which includes a receiving antenna for receiving corresponding driving electromagnetic signals; A drive array with a plurality of drive circuits, each of which includes: a transmit antenna, coupled with the receive antenna; A plurality of first impedance circuits are connected in parallel between the transmission antenna and the first AC signal, and each have different impedance values, wherein at least one of the first impedance circuits is enabled to enable the first AC signal The amplitude is adjusted according to the impedance value and transmitted to the transmitting antenna. 2 . The display device of claim 1 , wherein the first impedance circuits receive a plurality of first control signals to be enabled in response to the corresponding first control signals. 3 . 3. The display device of claim 2, wherein the first impedance circuits individually comprise: an impedance matching circuit with corresponding impedance values; a first switch, disposed between the first AC signal and the impedance matching circuit, and controlled to be turned on by the corresponding first control signal; and A second switch is disposed between the impedance matching circuit and the transmission antenna, and is controlled to be turned on by the corresponding first control signal. 4 . The display device of claim 3 , wherein the impedance matching circuit is a resistor, inductor, capacitor circuit. 5 . 5. The display device of claim 3, wherein the impedance matching circuit comprises a capacitor for forming a corresponding impedance value. 6. The display device of claim 3, further comprising: a driving signal generating circuit, receiving a display data to generate the first AC signal; and A control signal generating circuit receives the display data to generate the first control signals. 7 . The display device of claim 6 , wherein the driving signal generating circuit generates the first AC signal with reference to a first element portion of the display data, and the control signal generating circuit refers to the display data. 8 . A second bit portion of the generates the first control signals. 8 . The display device of claim 7 , wherein the first bit portion is a high bit portion, and the second bit portion is a low bit portion. 9 . 9 . The display device of claim 7 , wherein the first bit portion and the second bit portion do not overlap. 10 . 10. The display device of claim 7, wherein the first bit portion partially overlaps the second bit portion. 11. The display device of claim 6, wherein the driving signal generating circuit further generates a second AC signal in response to the display data, and the control signal generating circuit further generates a plurality of first AC signals in response to the display data Two control signals, The display device further includes a plurality of second impedance circuits, each of which is enabled by a corresponding second control signal, is connected in parallel between the transmission antenna and the second AC signal, and each has different impedance values, Wherein, at least one of the first impedance circuits and the second impedance circuits is enabled to transmit the first AC signal and the second AC signal to the transmitting antenna after adjusting the amplitudes according to the impedance values they have. 12. The display device of claim 11, wherein the first AC signal is a sine wave signal. 13 . The display device of claim 1 , wherein one of the first impedance circuits is enabled to adjust the amplitude of the first AC signal according to the impedance value it has, and then transmit the first AC signal to the transmission. 14 . antenna. 14. The display device of claim 1, wherein the first AC signal is a sine wave signal.

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