CN112509528B - Gate drive circuit, display device and gate drive method of display panel - Google Patents
Gate drive circuit, display device and gate drive method of display panel Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The application discloses a grid driving circuit, a display device and a grid driving method of a display panel, wherein the grid driving circuit comprises an input module, a shift register module, a multi-level high-level signal generation module, a level conversion module and an output module; the multi-level high-level signal generation module receives the high-level selection signal and at least two preset level voltages respectively, and generates and outputs level voltage signals; the level conversion module performs level conversion according to the level voltage signals of the multi-level high-level signal generation module to generate gate drive signals; and outputting the data to each gate line corresponding to the display panel. The multi-level high-level signal generation module selectively generates level voltage signals of different high-level voltages, and the level conversion module takes the level voltage signals with a plurality of high-level voltages as the reference of level conversion, and can generate at least two grid driving signals with high-level levels for the same grid line.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a gate driving circuit, a display device, and a gate driving method of a display panel.
Background
A TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the major types of flat panel displays, and has become an important Display platform in modern IT and video products. In general, a liquid crystal display device controls transmittance of liquid crystal by an electric field, thereby displaying an image. The display device includes a display panel, and a source driving circuit and a gate driving circuit for driving the display panel. The source electrode driving circuit provides data driving signals for data lines of the display panel; the gate driving circuit provides gate driving signals to the gate lines of the display panel.
The conventional gate driving circuit generally includes an input buffer, a shift register, a level shift unit, and an output buffer, where the shift register receives a control signal such as a clock signal, shifts to generate a plurality of sequentially shifted logic signals, and then performs level shift on the logic signals to generate gate driving signals with a high level VGH and a low level VGL, which are respectively input to corresponding scan lines. However, the high level of the gate driving signal outputted by the gate driving circuit is single, and when the gate driving signals with different high levels are required in the display panel, the structure of the conventional gate driving circuit cannot support the high level.
Disclosure of Invention
The present application provides a gate driving circuit, a display device and a gate driving method for a display panel, which can output at least two high level gate driving signals for a same gate line.
The application discloses display panel's gate drive circuit includes: the device comprises an input module, a shift register module, a multi-level high-level signal generation module, a level conversion module and an output module, wherein the input module is used for receiving a first control signal input from the outside; the shift register module is connected with the input module and shifts the first control signal received by the input module to generate a second control signal; the multi-level high-level signal generation module receives the high-level selection signal and at least two preset level voltages respectively, and generates and outputs level voltage signals; the level conversion module is connected with the shift register module, and performs level conversion on the second control signal according to the level voltage signal of the multi-level high-level signal generation module to generate a gate drive signal; the output module outputs the gate driving signals to each gate line corresponding to the display panel respectively; wherein the level voltages include a first level voltage and a second level voltage, and the first level voltage is greater than the second level voltage; when the received high-level selection signal meets a first preset condition, the multi-level high-level signal generation module outputs a level voltage signal with a voltage of the first level voltage to be sent to the level conversion module; when the received high level selection signal meets a second preset condition, the voltage of the output level voltage signal is the second level voltage to be sent to the level conversion module; the number of the second control signals and the number of the gate driving signals correspond to the number of the gate lines of the display panel.
The application also discloses a display device, including display panel, gate drive circuit and source drive circuit, gate drive circuit, source drive circuit drive connection display panel.
The application also discloses a grid driving method, which comprises the following steps:
receiving a preset first control signal and a high level selection signal;
shifting the first control signal through a shift register to generate second control signals, wherein the number of the second control signals corresponds to the number of the gate lines of the display panel;
comparing the high level selection signal with a preset condition, and outputting a quasi-level voltage signal of a first quasi-level voltage when the first preset condition is met; when a second preset condition is met, outputting a level voltage signal with a voltage of a second level voltage; and
performing level conversion on the second control signal by using the quasi-level voltage signal to generate gate driving signals, and outputting the gate driving signals to each gate line corresponding to the display panel respectively; the number of the gate driving signals corresponds to the number of the gate lines of the display panel;
wherein the level voltages include a first level voltage and a second level voltage, and the first level voltage is greater than the second level voltage;
the data driving signals corresponding to the same gate line have the same polarity; when the data driving signal corresponding to the current gate line is positive, presetting the high level selection signal to meet a first preset condition; when the data driving signal corresponding to the current gate line is negative, the high-level selection signal is preset to meet a second preset condition.
The multi-level high level signal generation module is arranged in the grid driving circuit of the display panel, and is controlled to selectively generate level voltage signals of different high level voltages according to different high level selection signals, and the level conversion module takes the level voltage signals of a plurality of high level voltages as the reference of level conversion, so that at least two grid driving signals with high level levels can be generated for the same grid line. Therefore, by setting different waveforms of the high-level selection signals, the control of the grid driving signals can be conveniently realized, and brightness difference caused by different charging rates of liquid crystal capacitors when the positive and negative polarities are adjusted through the grid driving signals can be realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic structural diagram of a display panel according to the present application;
FIG. 2 is a schematic diagram of an equivalent circuit of a sub-pixel of a display panel according to the present application;
FIG. 3 is a waveform analysis diagram of nodes in the equivalent circuit of the pixel of FIG. 2;
fig. 4 is a schematic circuit structure diagram of a gate driving circuit according to an embodiment of the present application;
fig. 5 is a circuit block diagram of a bi-level high-level signal generating module according to an embodiment of the present application;
fig. 6 is a circuit diagram of a bi-level high-level signal generating module according to an embodiment of the present application;
FIG. 7 is a timing waveform diagram corresponding to the embodiment of FIG. 4;
FIG. 8 is a flow chart of a gate driving method according to the present application;
fig. 9 is a schematic circuit structure diagram of a gate driving circuit according to another embodiment of the present application;
FIG. 10 is a circuit diagram of a bi-level high-level signal generating module according to another embodiment of the present application;
FIG. 11 is a circuit diagram of a bi-level high-level signal generating module according to another embodiment of the present application;
FIG. 12 is a timing waveform diagram for a single channel mode corresponding to the embodiment of FIG. 9;
FIG. 13 is a timing waveform diagram for the dual channel mode corresponding to the embodiment of FIG. 9.
Wherein: 100. a display device; 200 of a carrier; a display panel; 210. a gate line; 220. a data line; 230. a TFT; 240. a sub-pixel; 300. a gate drive circuit; 310. an input module; 320. a shift register module; 330. a double-level high-level signal generation module; 331. a switch control circuit; 332. a first switch control module; 333. a second switch control module; 334. a third switch control module; 335. a fourth switch control module; 336. a first switch module; 337. a second switch module; 338. a third switch module; 339. a fourth switching module; 340. a level conversion module; 341. a first level conversion unit; 342. a second level conversion unit; 350. an output module; 400. and a source driving circuit.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly and encompass, for example, both fixed and removable coupling as well as integral coupling; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.
The present application is described in detail below with reference to the figures and alternative embodiments.
The TFT-LCD display device 100 includes a display panel 200, and a source driving circuit 400 and a gate driving circuit 300 which are drivingly connected to the display panel 200. Referring to fig. 1 and 2, the display panel 200 is provided with a plurality of gate lines 210 and a plurality of data lines 220 arranged to cross, respectively driving the corresponding pixels arranged in an array. The gate driving circuit 300 applies a corresponding gate driving signal to the corresponding gate line 210 to turn on the thin film transistor of the corresponding pixel, so that the pixel is connected to the data driving signal of the corresponding data line 220 to be charged according to a preset gray level.
As shown in fig. 2, each pixel is driven by a gate line 210 to turn on a corresponding TFT 230(NMOS transistor) driven by a high VGH, a data line 220 sends a data voltage to charge a liquid crystal capacitor Clc and a storage capacitor Cst, and a rotation angle of the liquid crystal is controlled by controlling a voltage difference between two ends of the liquid crystal, so as to control how much light passes through to control brightness.
In the TFT-LCD liquid crystal panel, in order to prevent the liquid crystal from being polarized, the positive and negative polarities of the voltage difference across the liquid crystal of each sub-pixel 240 are continuously switched (for example, one frame is switched once, and two frames are one period), and the data driving signal Vd applied to the data line is greater than the Vcom voltage in the positive polarity and less than the Vcom voltage in the negative polarity. However, for the TFT, the high level of the gate driving signal Vg applied to the gate line is usually fixed, and due to the difference of Vd in positive and negative polarities, the voltage difference Vgs between the gate G and the source S of the TFT will be different, which will cause the current (Ion) in the on state of the TFT in the positive and negative polarities to be different, that is, the charging rate of the liquid crystal capacitor in the positive and negative polarities is different, which will cause the brightness of the pixel corresponding to the display panel 200 to be different corresponding to the same gray scale when different frames are switched.
To solve this problem, the pixel with positive and negative polarities can be driven by giving different gate voltages, that is: when the corresponding data driving signal is positive, the gate of the TFT is turned on by using the gate driving signal with a higher voltage level (the gate-on voltage is VGONP), and when the corresponding data driving signal is negative, the gate of the TFT is turned on by using the gate driving signal with a lower voltage level (the gate-on voltage is VGONN), as shown in fig. 3. The data driving signals corresponding to the same gate line of the display panel are of the same polarity, and due to the polarity inversion, the polarities of the corresponding data driving signals of the same gate line in different frames are different, so as to provide the gate driving voltages of different voltage levels to improve the brightness difference, the application provides a gate driving circuit 300 capable of outputting the gate driving signals of at least two high level levels for the same gate line 210.
As shown in fig. 4, a gate driving circuit 300 of a display panel 200 includes an Input module 310 (e.g., an Input buffer), a Shift Register module 320 (e.g., a BI-directional Shift Register), a multi-Level high-Level signal generation module (VGH SEL module), a Level Shift module 340(Level Shift), and an Output module 350(Output buffer) connected to each other.
The GATE driving circuit 300 may be a GATE driving chip (GATE IC), the input module 310 receives a first control signal input from an external circuit such as a timing control chip (TCON), and the first control signal may include CKV (clock signal), STV (frame start signal), DIR (direction control signal), and the like; the shift register module 320 is connected to the input module, and is controlled by the DIR signal to shift from left to right or from right to left, so as to shift the first control signal received by the input module to generate a second control signal (this is a logic signal, and the high level VDD is 3.3V, and the low level is GND ground); the number of the second control signals corresponds to the number of the gate lines 210 of the display panel 200. The multi-level high-level signal generation module receives a high-level selection signal and at least two preset level voltages respectively, and generates and outputs level voltage signals; the level voltage comprises a first level voltage and a second level voltage, and the first level voltage is greater than the second level voltage. The level shift module 340 is connected to the shift register module 320, and performs level shift on the second control signal according to the level voltage signal of the multi-level high-level signal generation module to generate an analog VGH1/VGH2 with a high level being a corresponding level voltage and a gate driving signal with a low level being a negative analog level VGL; the number of the gate driving signals corresponds to the number of the gate lines 210 of the display panel 200. The output module 350 outputs the gate driving signals (out1, out2 …, outn) to the gate lines 210 corresponding to the display panel 200 respectively.
When the received high level selection signal satisfies a first predetermined condition (e.g., a high level), the multi-level high level signal generating module outputs a level voltage signal having a voltage equal to the first level voltage to be transmitted to the level converting module 340; when the received high-level selection signal satisfies a second predetermined condition (e.g., a low level), the multi-level high-level signal generating module outputs a level voltage signal having the voltage of the second level voltage to be transmitted to the level converting module 340.
By arranging a multi-level high-level signal generating module in the gate driving circuit 300, the multi-level high-level signal generating module is controlled to selectively generate level voltage signals of different high-level voltages according to different high-level selection signals, and the level converting module 340 can generate at least two gate driving signals of high-level levels for the same gate line 210 by taking the controllable level voltage signals with a plurality of high-level voltages as the reference of level conversion. Therefore, by setting different waveforms of the high-level selection signals, the control of the grid driving signals can be conveniently realized, and brightness difference caused by different charging rates of liquid crystal capacitors when the positive and negative polarities are adjusted through the grid driving signals can be realized.
Specifically, the multi-level high-level signal generating module may be a dual-level high-level signal generating module 330, which receives a preset first level voltage VGH1, a preset second level voltage VGH2 and a preset high-level selection signal VGH _ SEL, and selects and outputs level voltage signals of two high-level voltages. As shown in fig. 5 and 6, the bi-level high-level signal generating module 330 includes a first switch module 336, a second switch module 337 and a switch control circuit 331. The input terminal of the first switch module 336 receives a preset first level voltage VGH1, and the output terminal is connected to the level shifter module 340; the input end of the second switch module 337 receives a preset second level voltage VGH2, and the output end is connected to the level shifter module 340. The switch control circuit 331 receives a preset high level selection signal and controls to connect the first switch module 336 and the second switch module 337. When the high level selection signal VGH _ SEL is at a high level H, the switch control circuit controls the first switch module 336 to be turned on, the second switch module 337 to be turned off, and outputs a level voltage signal with a first level voltage VGH1 to the level shifter module 340; when the received high level selection signal VGH _ SEL is at the low level L, the switch control circuit controls the first switch module 336 to be turned off, the second switch module 337 is turned on, and a level voltage signal with a second level voltage VGH2 is output to the level shifter module 340.
Specifically, as shown in fig. 6, the switch control circuit 331 includes a first switch control module 332 and a second switch control module 333, which are respectively connected to the first switch module (Q1) and the second switch module (Q2). The second switch control module 333 includes a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a third switching tube Q3, which are sequentially connected in series between the first reference voltage VGH1 and the ground GND; the control end of the third switching tube is connected to the high-level selection signal VGH _ SEL; the output terminal of the second switch control module 333 is disposed between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and is controllably connected to the control terminal of the first switch module. The first switch module is a first switch Q1, the output terminal of the second switch control module 333 is connected to the gate of the first switch Q1, the source of the first switch is connected to the first level voltage VGH1, and the drain of the first switch is connected to the output terminal P1 of the bi-level high-level signal generation module 330. The R1 and the R2 are voltage dividing resistors, and the first switch module can be controlled and controlled by adjusting the resistance value of the R1 and/or the R2 and selecting a proper conducting voltage.
The second switch control module 333 comprises a third voltage dividing resistor R3, a fourth voltage dividing resistor R4 and a fourth switch Q4 which are sequentially connected in series between the second level voltage VGH2 and the ground GND; the control end of the fourth switching tube is connected to the high-level selection signal VGH _ SEL through an inverter; the output terminal of the second switch control module 333 is disposed between the third voltage dividing resistor R3 and the fourth voltage dividing resistor R4, and is controllably connected to the control terminal of the second switch module. The second switch module is a second switch tube Q2, an output end of the second switch control module 333 is connected to a gate of the second switch tube Q2, a source of the second switch tube is connected to the second level voltage VGH2, and a drain of the second switch tube is connected to the output end P1 of the dual-level high-level signal generating module 330.
When the VGH _ SEL signal is at a high level H, Q3 is turned on, at this time, R1 and R2 are turned on through Q3 to GND stroke path control Q1, VGH1 is output to the level shift module 340 through Q1, and Q4 controlled after VGH _ SEL is inverted cannot turn on Q2. When the VGH _ SEL signal is at a low level L, Q3 is cut off, and Q1 cannot be turned on at the moment; the controlled Q4 of the VGH _ SEL signal after being inverted by the inverter is turned on, at this time, the R3 and R4 are turned on through Q4 to the GND stroke path control Q2, and then the VGH2 is output to the level conversion module 340 through Q2.
The corresponding waveform timing diagram is shown in fig. 7. The polarity of the pixel electrodes of the display panel 200 is inverted once per Frame, and two frames (frames) are used as a switching period; correspondingly, the VGH _ SEL signal also takes two frames as a period, the level is switched from low level to high level or from high level to low level once per frame, the same grid line 210G (n) (n is a natural number) can be realized, and grid driving signals with two high level levels (VGH1/VGH2) are output, the grid of the pixel TFT is opened by using VGH1 with higher voltage level in positive polarity, and the grid of the pixel TFT is opened by using VGH2 with lower voltage level in negative polarity, so that the charging rates of liquid crystal capacitors are consistent when the positive polarity and the negative polarity of the pixel electrode are positive and negative, and the brightness difference of the pixel is reduced.
Correspondingly, as shown in fig. 8, the gate driving method of the display panel 200 includes the following steps:
s1: receiving a preset first control signal and a high level selection signal;
s2: shifting the first control signal through a shift register to generate second control signals, wherein the number of the second control signals corresponds to the number of the gate lines of the display panel;
s3: comparing the high level selection signal with a preset condition, and outputting a quasi-level voltage signal of a first quasi-level voltage when the first preset condition is met; when a second preset condition is met, outputting a level voltage signal with a voltage of a second level voltage;
s4: performing level conversion on the second control signal by using the quasi-level voltage signal to generate a gate driving signal, and outputting the gate driving signal to each gate line corresponding to the display panel respectively; the number of the gate driving signals corresponds to the number of the gate lines of the display panel.
The level voltages include a first level voltage VGH1 and a second level voltage VGH2, and the first level voltage is greater than the second level voltage. The data driving signals corresponding to the same gate line 210 have the same polarity, even the data driving signals of all pixels in the same frame have positive polarity, and the data driving signals in the next frame are inverted to negative polarity. When the data driving signal corresponding to the current gate line 210 is positive, the high-level selection signal is preset to satisfy a first preset condition (for example, a high level, the gate of the current pixel TFT is turned on by using a first level voltage VGH1 with a higher voltage level); when the data driving signal corresponding to the current gate line 210 is negative, the high-level selection signal is preset to satisfy a second preset condition (for example, if the high level is low, the gate of the current pixel TFT is turned on by using a second level voltage VGH2 with a lower voltage level).
In general, the data driving signals corresponding to the same gate line 210 on the display panel 200 are not of the same polarity, and include both positive sub-pixels and negative sub-pixels, and to implement that the positive and negative polarities are driven by different VGH voltages, the data driving signals corresponding to the same gate line 210 are still of the same polarity by connecting the upper and lower rows of the pixel electrodes of the same polarity to the same gate line 210, the sub-pixels controlled by odd gate lines 210 are of the same polarity, and the sub-pixels controlled by even gate lines 210 are of the other polarity.
Unlike the previous embodiment, as shown in fig. 9, the multi-level high-level signal generating module is a dual-level high-level signal generating module 330; the level shifting module 340 includes a first level shifting unit 341 and a second level shifting unit 342. The first level shifter 341, corresponding to the odd-numbered gate lines 210 of the display panel 200, receives the first level voltage signal sent by the dual-level high-level signal generator 330 as a power source, and generates the gate driving signal corresponding to the odd-numbered gate lines 210 of the display panel 200. The second level shifter 342 corresponds to the even-numbered gate lines 210 of the display panel 200, receives the second-level voltage signal sent by the dual-level high-level signal generator 330 as a power source, and generates the gate driving signals corresponding to the even-numbered gate lines 210 of the display panel 200.
In the same frame, the polarities of the data driving signals of the odd-numbered gate lines and the even-numbered gate lines of the display panel 200 are opposite. When the received high-level selection signal satisfies that the first preset condition is a high level, the dual-level high-level signal generating module 330 outputs a first level voltage signal with a first level voltage to the first level converting unit 341 and outputs a second level voltage signal with a second level voltage to the second level converting unit 342; when the received high-level selection signal satisfies that the second predetermined condition is a low level, the first level voltage signal with the second level voltage is output to the first level conversion unit 341, and the second level voltage signal with the first level voltage is output to the second level conversion unit 342.
As shown in fig. 10 and 11, the bi-level high-level signal generating module 330 includes a first switch module 336, a second switch module 337, a third switch module 338, a fourth switch module 339 and a switch control circuit 331. Wherein the input terminal of the first switch module 336 receives the preset first level voltage VGH1, and the output terminal P1 is connected to the first level shifter 341; the input terminal of the second switch module 337 receives the preset second level voltage VGH2, and the output terminal P1 is connected to the first level shifter 341; the input terminal of the third switching module 338 receives the preset first level voltage VGH1, and the output terminal P2 is connected to the second level shifter 342; the input terminal of the fourth switching module 339 receives the preset second level voltage VGH2, and the output terminal P2 is connected to the second level shifter 342.
The switch control circuit 331 receives the high level selection signal VGH _ SEL and controls to connect the first switch module 336, the second switch module 337, the third switch module 338 and the fourth switch module 339. When the high level selection signal VGH _ SEL is at a high level H, the switch control circuit controls the first switch module 336 and the fourth switch module 339 to be turned on, the second switch module 337 and the third switch module 338 to be turned off, outputs a first level voltage signal of the first level voltage VGH1 to the first level conversion unit 341, and outputs a second level voltage signal of the second level voltage VGH2 to the second level conversion unit 342; when the received high-level selection signal VGH _ SEL is at the low level L, the switch control circuit controls the first switch module 336 and the fourth switch module 339 to be turned off, the second switch module 337 and the third switch module 338 to be turned on, outputs the first level voltage signal of the second level voltage VGH2 to the first level conversion unit 341, and outputs the second level voltage signal of the first level voltage VGH1 to the second level conversion unit 342.
Specifically, as shown in fig. 11, the switch control circuit 331 includes a second switch control module 333, a third switch control module 334, and a fourth switch control module 335, which are respectively connected to the first switch module (Q1), the second switch module (Q2), the third switch module (Q5), and the fourth switch module (Q6).
The first switch control module 332 and the second switch control module 333 have the same structure as the previous embodiment; the drains of the first and second switching tubes are connected to the first output end P1 of the bi-level high level signal generating module 330, and the first output end P1 outputs a first level voltage signal to the first level shifter 341.
The third switch control module 334 comprises a fifth voltage-dividing resistor R5, a sixth voltage-dividing resistor R6 and a seventh switch tube Q7 which are sequentially connected in series between the first reference voltage VGH1 and the ground GND; the control end of the seventh switch tube Q7 is connected to the high level selection signal VGH _ SEL through an inverter; the output end of the third switching control module 334 is disposed between the fifth voltage-dividing resistor R5 and the sixth voltage-dividing resistor R6, and is controllably connected to the control end of the third switching module. The third switching module is a fifth switching tube Q5, the output terminal of the third switching control module 334 is connected to the gate of the fifth switching tube Q5, the source of the third switching tube is connected to the first level voltage VGH1, and the drain of the third switching tube is connected to the second output terminal P2 of the dual-level high-level signal generating module 330.
The fourth switch control module 335 comprises a seventh voltage-dividing resistor R7, an eighth voltage-dividing resistor R8 and an eighth switching tube Q8, which are sequentially connected in series between the second level voltage VGH2 and the ground GND; the control end of the eighth switching tube is connected to the high-level selection signal VGH _ SEL; the output terminal of the fourth switch control module 335 is disposed between the seventh voltage dividing resistor R7 and the eighth voltage dividing resistor R8, and is controllably connected to the control terminal of the fourth switch module. The fourth switch module is a sixth switch Q6, the output terminal of the fourth switch control module 335 is connected to the gate of the sixth switch Q6, the source of the sixth switch is connected to the second level voltage VGH2, and the drain of the sixth switch is connected to the second output terminal P2 of the dual-level high-level signal generation module 330. The second output terminal P2 outputs a second level voltage signal to the second level shifter unit 342.
When the VGH _ SEL signal is at a high level H, Q3 and Q8 are turned on, at this time, R1 and R2 are opened through a Q3-GND stroke path control Q1, and R7 and R8 are opened through a Q8-GND formation path control Q6, so that VGH1 is output to the first level conversion unit 341(odd level shifter module) through Q1, and VGH2 is output to the second level conversion unit 342(even level shifter module) through Q6; q4 and Q7 controlled by the inverted VGH _ SEL are cut off, and Q2 and Q5 cannot be turned on.
When the VGH _ SEL signal is at low level L, Q3 and Q8 are turned off, and Q1 and Q6 cannot be turned on; meanwhile, Q4 and Q7 controlled by the VGH _ SEL signal after being inverted by the inverter are opened, at this time, R3 and R4 are opened through Q4 to GND stroke path control Q2, and R5 and R6 are opened through Q7 to GND forming path control Q5, so that VGH2 is output to the first level conversion unit 341(odd level shifter module) of the level conversion module 340 through Q2, and VGH1 is output to the second level conversion unit 342(even level shifter module) through Q5.
Set up four mutually independent switch control modules, every switch control module independently judges whether the switch module that corresponds switches on or breaks off for can design every switch control module's the requirement of switching on alone according to the actual conditions of concrete circuit, it is also easier relatively to carry out the maintenance of trouble and detect. The multi-level high-level signal generating circuit can be used as a single circuit module, or can be integrated with a gate driving chip such as the level shifting module 340.
The grid driving chip is provided with a double-channel control pin for receiving a preset double-channel control signal (Dual signal). The shift register module 320 receives the dual-channel control signal, when the dual-channel control signal is a first level (e.g., L), the gate driver chip enters a single-channel mode, the shift register module 320 generates a second control signal for shifting row by row, and the gate line 210 is opened row by the control of a scan drive signal (gate driver). Fig. 12 shows a timing diagram of the single channel mode, where P1 is the waveform of the first level voltage signal output by the first output terminal to the first level shifter 341, and P2 is the waveform of the second level voltage signal output by the second output terminal to the second level shifter 342. When the first frame VGH _ SEL is L, the odd channel output high level is VGH2, and the even channel output high level is VGH 1; when the second frame VGH _ SEL is H, the odd channel output high level is VGH1, and the even channel output high level is VGH 2.
When the dual-channel control signal is at a second level (e.g., H), the gate driver chip enters a dual-channel mode, and the shift register module 320 generates a second control signal that every two rows of gate lines 210 are turned on at the same time for one channel group and shifted every two rows; and the second control signal carries out level conversion to generate a grid driving signal. As shown in fig. 13, when the first frame VGH _ SEL is L, the odd channel output high level is VGH2, and the even channel output high level is VGH 1; when the second frame VGH _ SEL is H, the odd channel output high level is VGH1, and the even channel output high level is VGH 2.
Of course, the display panel 200 is not limited to the odd-numbered gate lines and the even-numbered gate lines corresponding to the data driving signals having opposite polarities, as long as the data driving signals corresponding to the same gate line 210 have the same polarity, and the gate lines 210 having opposite polarities respectively correspond to the first level shifter 341 and the second level shifter 342 in the same frame, so that a more complicated polarity inversion situation can be supported.
It should be noted that, the limitations of each step involved in the present solution are not considered to limit the order of the steps on the premise of not affecting the implementation of the specific solution, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present solution can be implemented, all the steps should be considered as belonging to the protection scope of the present application; in addition, in the technical solutions of the embodiments of the present application, other technical features besides the mutually conflicting technical features may be combined and applied.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For example, the multi-level high-level signal generating circuit may conveniently implement control of the gate driving signal by setting waveforms of different high-level selection signals, and generate more than 2 scanning driving signals of different high-level VGH voltages for the same gate line 210, and high-level levels of the scanning driving signals of different gate lines 210 may also be different, and are not limited to the application of adjusting the luminance difference caused by different charging rates of the liquid crystal capacitors when the polarities are positive and negative by the gate driving signal in this embodiment.
Claims (8)
1. A gate driving circuit of a display panel, comprising:
the input module receives a first control signal input from the outside;
the shift register module is connected with the input module and shifts the first control signal received by the input module to generate a second control signal;
the multi-level high-level signal generation module is used for respectively receiving the high-level selection signal and at least two preset level voltages, and generating and outputting level voltage signals;
the level conversion module is connected with the shift register module and is used for carrying out level conversion on the second control signal according to the level voltage signal of the multi-level high-level signal generation module to generate a grid driving signal; and
the output module outputs the gate driving signals to the gate lines corresponding to the display panel respectively;
wherein the level voltages include a first level voltage and a second level voltage, and the first level voltage is greater than the second level voltage; when the received high-level selection signal meets a first preset condition, the multi-level high-level signal generation module outputs a level voltage signal with a voltage of the first level voltage; when the received high-level selection signal meets a second preset condition, the voltage of the output level voltage signal is the second level voltage;
the number of the second control signals and the number of the gate driving signals correspond to the number of the gate lines of the display panel;
the multi-level high-level signal generation module is a double-level high-level signal generation module; the dual-level high-level signal generating module comprises:
the input end of the first switch module receives the preset first reference voltage, and the output end of the first switch module is connected to the level conversion module;
the input end of the second switch module receives the preset second level voltage, and the output end of the second switch module is connected to the level conversion module; and
the switch control circuit receives the high level selection signal and controls and connects the first switch module and the second switch module;
when the high level selection signal meets the first preset condition of high level, the switch control circuit controls the first switch module to be switched on and controls the second switch module to be switched off, and a quasi-position voltage signal with the voltage being the first quasi-position voltage is output to the level conversion module;
when the high level selection signal meets the second preset condition of low level, the switch control circuit controls the first switch module to be switched off and controls the second switch module to be switched on, and outputs a level voltage signal with the voltage of the second level voltage to the level conversion module;
the switch control circuit comprises a first switch control module and a second switch control module, wherein the first switch control module comprises a first voltage dividing resistor R1, a second voltage dividing resistor R2 and a third switching tube Q3 which are sequentially connected in series between the first reference voltage and the ground wire; the control end of the third switching tube is connected to the high-level selection signal; the output end of the first switch control module is arranged between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 and is in control connection with the control end of the first switch module; the first switch module is a first switch tube Q1, an output end of the first switch control module is connected with a gate of the first switch tube Q1 in a control manner, a source electrode of the first switch tube is connected to the first reference voltage, and a drain electrode of the first switch tube is connected to an output end of the dual-reference high-level signal generation module;
the second switch control module comprises a third voltage dividing resistor R3, a fourth voltage dividing resistor R4 and a fourth switching tube Q4 which are sequentially connected in series between the second level voltage and the ground wire; the control end of the fourth switching tube is connected to the high-level selection signal through an inverter; the output end of the second switch control module is arranged between the third voltage dividing resistor R3 and the fourth voltage dividing resistor R4 and is connected to the control end of the second switch module in a control mode; the second switch module is a second switch tube Q2, the output end of the second switch control module is connected with the gate of the second switch tube Q1 in a control manner, the source of the second switch tube is connected to the second level voltage, and the drain of the second switch tube is connected to the output end of the double-level high-level signal generation module.
2. The gate driving circuit of claim 1, wherein the multi-level high-level signal generating module is a bi-level high-level signal generating module; the level conversion module includes:
the first level conversion unit corresponds to a first group of grid lines of the display panel and receives a first level voltage signal sent by the double-level high-level signal generation module; and
the second level conversion unit corresponds to a second group of grid lines of the display panel and receives a second level voltage signal sent by the double-level high-level signal generation module;
when the received high-level selection signal meets the first preset condition of being at a high level, the double-level high-level signal generation module outputs a first level voltage signal with a first level voltage to the first level conversion unit and outputs a second level voltage signal with a second level voltage to the second level conversion unit; when the received high-level selection signal meets the second preset condition of low level, a first level voltage signal with the voltage of a second level voltage is output to the first level conversion unit, and a second level voltage signal with the voltage of the first level voltage is output to the second level conversion unit.
3. The gate driving circuit of claim 2, wherein the first level shifter generates the gate driving signals corresponding to the gate lines of the odd rows of the display panel;
the second level conversion unit generates a gate driving signal corresponding to an even-numbered row of gate lines of the display panel;
correspondingly, in the same frame, the polarities of the data driving signals of the odd-numbered gate lines and the even-numbered gate lines of the display panel are opposite.
4. The gate driving circuit of claim 2, wherein the bi-level high signal generating module comprises:
the input end of the first switch module receives the preset first level voltage, and the output end of the first switch module is connected to the first level conversion unit;
the input end of the second switch module receives the preset second level voltage, and the output end of the second switch module is connected to the first level conversion unit;
the input end of the third switch module receives the preset first level voltage, and the output end of the third switch module is connected to the second level conversion unit;
the input end of the fourth switch module receives the preset second level voltage, and the output end of the fourth switch module is connected to the second level conversion unit; and
the switch control circuit receives the high level selection signal and is connected with the first switch module, the second switch module, the third switch module and the fourth switch module in a control mode;
when the high level selection signal is at a high level, the switch control circuit controls the first switch module and the fourth switch module to be switched on and controls the second switch module and the third switch module to be switched off, outputs a first quasi-level voltage signal of a first quasi-level voltage to the first level conversion unit, and outputs a second quasi-level voltage signal of a second quasi-level voltage to the second level conversion unit;
when the high level selection signal is at a low level, the switch control circuit controls the first switch module and the fourth switch module to be switched off, controls the second switch module and the third switch module to be switched on, outputs a first level voltage signal of a second level voltage to the first level conversion unit, and outputs a second level voltage signal of the first level voltage to the second level conversion unit.
5. The gate driving circuit of claim 1, wherein the gate driving circuit is a gate driving chip, and the gate driving chip is provided with a dual channel control pin for receiving a predetermined dual channel control signal;
the shift register module receives the two-channel control signal, when the two-channel control signal is at a first level, the grid drive chip enters a single-channel mode, and the shift register module generates a second control signal for shifting line by line;
when the dual-channel control signal is at a second level, the grid driving chip enters a dual-channel mode, and the shift register module generates a second control signal which is turned on at the same time every two rows of grid lines as a channel group and shifted at intervals of two rows; the second control signal carries out level conversion to generate a gate driving signal, wherein in the dual-channel mode, the turn-on time of the gate driving signal corresponding to two gate lines in one channel group is the same, and the quasi-level voltages are different.
6. The gate driving circuit of claim 4, wherein the third switch control module comprises a fifth voltage-dividing resistor R5, a sixth voltage-dividing resistor R6, and a seventh switch tube Q7 connected in series in sequence between the first level voltage and the ground line GND; the control end of the seventh switch tube Q7 is connected to the high level selection signal VGH _ SEL through an inverter; the output end of the third switch control module is arranged between the fifth voltage-dividing resistor R5 and the sixth voltage-dividing resistor R6 and is connected to the control end of the third switch module in a control mode; the third switching module is a fifth switching tube Q5, an output end of the third switching control module is connected to a gate of the fifth switching tube Q5, a source of the third switching tube is connected to the first level voltage VGH1, and a drain of the third switching tube is connected to the second output end P2 of the dual-level high-level signal generating module.
7. A display device comprising a display panel, a gate driver circuit according to any one of claims 1 to 6, and a source driver circuit, the gate driver circuit and the source driver circuit being in driving connection with the display panel.
8. The display device according to claim 7, wherein the source driving circuit outputs a data driving signal to each data line corresponding to the display panel;
the data driving signals corresponding to the same gate line are of the same polarity;
when the data driving signal corresponding to the current gate line is positive, presetting a high level selection signal of the gate driving circuit to meet a first preset condition; when the data driving signal corresponding to the current gate line is negative, the high-level selection signal of the gate driving circuit is preset to meet a second preset condition.
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| TWI433088B (en) * | 2010-10-27 | 2014-04-01 | Chunghwa Picture Tubes Ltd | Display and driving method |
| TWI453724B (en) * | 2011-08-22 | 2014-09-21 | Chunghwa Picture Tubes Ltd | Liquid crystal display which can compensate gate voltages and method thereof |
| CN102254538A (en) * | 2011-09-01 | 2011-11-23 | 南京中电熊猫液晶显示科技有限公司 | Method for reducing unbalance of liquid crystal positive and negative voltages |
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