CN112509529B

CN112509529B - Display panel and display device

Info

Publication number: CN112509529B
Application number: CN202011214636.8A
Authority: CN
Inventors: 纪飞林; 郑浩旋
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2020-11-04
Filing date: 2020-11-04
Publication date: 2022-10-21
Anticipated expiration: 2040-11-04
Also published as: CN112509529A

Abstract

The application discloses display panel and display device, display panel includes drive circuit, drive circuit includes: a plurality of data lines; a plurality of gate lines, the gate lines and the data lines being interleaved with each other; a plurality of pixels respectively driven by the corresponding data lines and gate lines; the time-sharing control circuit controls the charging time of different pixels in the same row of pixels; the source electrode driving chip comprises a plurality of source electrode output ends, and each source electrode output end is connected with the two data lines through the time-sharing control circuit; in the on period of one gate line, the same source output end outputs data signals to the two data lines in a time-sharing mode through the time-sharing control circuit respectively so as to charge the pixels corresponding to the two data lines in a time-sharing mode, and the number of the gate lines and the cost of a gate driving chip are saved compared with that of a conventional model if the number of the gate lines and the cost of the gate driving chip are kept unchanged relative to that of the dual-gate framework.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

In general, there are two architectures in the array substrate of the TFT-LCD, one is a conventional (normal) architecture, i.e. the number of data lines is 4096, and the number of gate lines is 768; the other is a Dual gate (Dual gate) architecture, which increases the number of gate lines and data lines, and further decreases the number of source driver chips for transmitting pixel data to the data lines and increases the number of gate driver chips, compared to the conventional architecture, because the source driver chips are more expensive than the gate driver chips in the market, the Dual gate architecture has a lower cost.

Another Dual gate (Dual gate) architecture is usually adopted in high-definition liquid crystal displays, two gate driver chips with 768 channels are required, the cost is still higher, and reducing the output channels of the gate chips is an urgent problem to be solved on the premise of ensuring the charging time.

Disclosure of Invention

An object of the present application is to provide a display panel and a display device in which gate lines and gate driving chips are not doubled while source driving chips are halved.

The application discloses display panel, include display panel includes drive circuit, drive circuit: a plurality of data lines; a plurality of gate lines, the gate lines and the data lines being interlaced with each other to be arranged in a matrix; a plurality of pixels respectively driven by the corresponding data lines and gate lines; a time-sharing control circuit; the grid driving chip comprises a plurality of grid output ends, and each grid output end is connected with one grid line; the source electrode driving chip comprises a plurality of source electrode output ends, and each source electrode output end is connected with the two data lines through the time-sharing control circuit; in the open period of one gate line, the same source output end outputs data signals to the two data lines in a time-sharing mode through the time-sharing control circuit, and the two data lines charge corresponding pixels in a time-sharing mode.

Optionally, the time-sharing control circuit includes a first switch circuit, a second switch circuit, and a plurality of switch tubes; the nth source output end is respectively connected with the 2n-1 th data line and the 2 nth data line, and the nth source output end respectively outputs data signals to the 2n-1 th data line and the 2 nth data line through the switch tube; the control ends of the switching tubes corresponding to all the 2n-1 th data lines are connected to the first switching circuit, and the control ends of the switching tubes corresponding to all the 2n-1 th data lines are connected to the second switching circuit; in an on period of one gate line, a corresponding one of the source output terminals respectively outputs a data signal output by the nth source output terminal to the 2n-1 th data line and the 2 nth data line through the corresponding switching tubes in a time-sharing manner through the first switching circuit and the second switching circuit; n is a natural number of 1 or more.

Optionally, each of the pixels includes a plurality of sub-pixels arranged in the same row; the same data line is connected with all the sub-pixels in the corresponding pixels in the same column; the same gate line is connected with all the sub-pixels in the same corresponding row.

Optionally, the first switch circuit receives a first control signal, the second switch circuit receives a second control signal, and both the first control signal and the second control signal are pulse control signals; the first control signal and the second control signal each have a high level period during an on period of one of the gate lines; when the first control signal is in a high level period, the second control signal is in a low level period, and when the second control signal is in a high level period, the first control signal is in a low level period.

Optionally, the sum of the on-time durations of the first switch circuit and the second switch circuit is less than the on-time of one row of scanning lines; each gate line is opened in a period comprising a first time period, a second time period, a third time period and a fourth time period which are continuously connected; the first control signal is at a high level in a second time period; the second control signal is at a high level during a fourth time period.

Optionally, the gate driver chip receives a frame start signal and a clock signal, and the source driver chip receives a polarity inversion signal, a low voltage differential signal, and a data latch signal; the first switch circuit and the second switch circuit determine the turn-on time according to the rising edge of the data latch signal.

Optionally, the driving circuit further includes a timing control circuit and a level shifter, the timing control circuit is coupled to the level shifter, the timing control circuit outputs a first preliminary control signal and a second preliminary control signal to the level shifter, and the level shifter converts the first preliminary control signal and the second preliminary control signal into the first control signal and the second control signal, which are correspondingly output to the first switch circuit and the second switch circuit of the time-sharing control circuit.

Optionally, the display panel is divided into a display area and a non-display area, and the time-sharing control circuit is disposed in the non-display area.

The application also discloses a display panel divides into display area and non-display area, display panel includes drive circuit, drive circuit includes: a plurality of data lines; a plurality of gate lines, the gate lines and the data lines being interleaved with each other; a plurality of pixels respectively driven by the corresponding data lines and gate lines; the time-sharing control circuit controls the charging time of different pixels in the same row of pixels; the grid driving chip comprises a plurality of grid output ends, and each grid output end is connected with one grid line; the source electrode driving chip comprises a plurality of source electrode output ends, and each source electrode output end is connected with the two data lines through the time-sharing control circuit; each pixel comprises a plurality of R sub-pixels, B sub-pixels and G sub-pixels which are arranged in the same row; the same data line is correspondingly connected with all the R sub-pixels, the B sub-pixels or the G sub-pixels in the same column of pixels;

the time-sharing control circuit is arranged in the non-display area and comprises a first switch circuit for receiving a first control signal, a second switch circuit for receiving a second control signal and a plurality of switch tubes; the first control signal and the second control signal are both pulse control signals; the output end of each switching tube is correspondingly connected to the input end of each data line, and the input ends of the switching tubes corresponding to the 2 nth data line and the 2n-1 th data line in the data lines corresponding to the R sub-pixel, the B sub-pixel and the G sub-pixel are simultaneously connected to the same source output end;

the first control signal and the second control signal both have only one high level period, the high level period of the first control signal and the high level period of the second control signal are in different time periods, and in the opening period of one gate line, the first switch circuit and the second switch circuit conduct the corresponding switch tubes in a time-sharing manner so as to output the data signals of the source driving chip to two data lines in a time-sharing manner to charge the pixels corresponding to the data lines; n is a natural number of 1 or more.

The application also discloses a display device, which comprises the display panel.

Compared with the scheme of respectively charging the pixels in the same row by using the double-gate lines, the gate line number and the gate driving chips are kept unchanged relative to the conventional model while the source driving chips are halved, only one gate driving chip with 768 channels is used, and the pixels corresponding to the gate lines in the same row are separately charged by arranging the time-sharing control circuit, so that the number of the gate driving chips, the number of the gate lines and the manufacturing cost of a panel are reduced relative to a double-gate framework, and the light transmittance of the whole display panel can be increased by reducing the number of the gate lines.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a time sharing control circuit according to an embodiment of the present application;

FIG. 4 is a diagram illustrating a driving system architecture of a display panel according to an embodiment of the present application;

fig. 5 is a schematic diagram of a driving timing sequence of a display panel according to an embodiment of the present application.

100, a display panel; 110. a display area; 120. a non-display area; 200. a drive circuit; 210. a data line; 220. a gate line; 230. a pixel; 240. a time-sharing control circuit; 241. a first switching circuit; 242. a second switching circuit; 243. a switching tube; 250. a gate driver chip; 260. a source driver chip; 270. a timing control circuit; 280. a level shifter; 300. a display device; SW1, a first control signal; SW2, a second control signal; t _ SW1, a first preliminary control signal; t _ SW1, second preliminary control signal.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.

Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.

Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly and encompass, for example, both fixed and removable coupling as well as integral coupling; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.

The present application is described in detail below with reference to the figures and alternative embodiments.

As shown in fig. 1 to 2, as an embodiment of the present application, a display device is disclosed, which includes a display panel 100; the display panel 100 includes a driving circuit 200, the driving circuit 200 includes a plurality of data lines 210, a plurality of gate lines 220 and a plurality of pixels 230, the gate lines 220 and the data lines 210 are interlaced, each of the pixels 230 is driven by the corresponding data line 210 and gate line 220, respectively, the pixels 230 are arranged in a plurality of rows and columns on the display panel 100; the driving circuit 200 further includes a time-sharing control circuit 240 for controlling the charging time of different pixels 230 in the same row of pixels 230; a gate driving chip 250 including a plurality of gate output terminals, each of the gate output terminals being connected to one of the gate lines 220; the source driving chip 260 includes a plurality of source output terminals, and each of the source output terminals is connected to the two data lines 210 through the time-sharing control circuit 240; in the on period of one gate line 220, the same source output terminal outputs a data signal to two data lines 210 in a time-sharing manner through the time-sharing control circuit 240, so as to charge the pixels 230 corresponding to the two data lines 210 in a time-sharing manner, and in the on period of one gate line 220, all the pixels 230 connected to one row of the gate line 220 are charged in a time-sharing manner through the time-sharing control circuit 240.

In the effective charging time, all the pixels 230 corresponding to one row of the gate lines 220 are charged twice, so that the gate lines 220 do not need to be arranged in a double manner, and the gate driving chips 250 only need to be arranged one by one, thereby reducing the number of the gate lines 220, increasing the transmittance of the display panel 100, reducing the number of the gate driving chips 250, and further reducing the manufacturing cost of the panel.

As shown in fig. 3, in order to conveniently control the charging on time of the pixels 230 corresponding to the same row of scanning lines, the time-sharing control circuit 240 includes a first switch circuit 241, a second switch circuit 242, and a plurality of switch tubes 243; the nth source output end is respectively connected to the 2n-1 th data line 210 and the 2 nth data line 210, and the nth source output end outputs data signals to the 2n-1 th data line 210 and the 2 nth data line 210 through the switching tube 243; the control ends of the switch tubes 243 corresponding to all the 2n-1 th data lines 210 are connected to the first switch circuit 241, and the control ends of the switch tubes 243 corresponding to all the 2n-1 th data lines 210 are connected to the second switch circuit 242; in an on period of one gate line 220, a corresponding one of the source output terminals respectively passes through the first switch circuit 241 and the second switch circuit 242, and a data signal output from the nth source output terminal is time-divisionally output to the 2n-1 th data line 210 and the 2 nth data line 210 through the corresponding switch tube 243; n is a natural number greater than or equal to 1; the time-sharing control circuit 240 is arranged in the non-display area 120 on the glass, each 1 output channel of the source driving chip 260 is connected to 2 adjacent data lines through 2 NMOS, and then the Gate electrodes of the NMOS on the odd number of data lines are connected together and controlled through SW 1; connecting the Gate electrodes of the NMOS on the even number of data lines together, and controlling through SW 2;

certainly, not only the odd-numbered rows and the even-numbered rows are limited to be distinguished, the data lines 210 corresponding to all the pixels 230 corresponding to one gate line 220 may also be connected to the same source output end through N-MOS transistors in any pairs, and any data line of the data lines that have been connected in any pair cannot be connected in any pair with other data lines.

Further, each of the pixels 230 includes a plurality of sub-pixels 230 arranged in the same row, and the sub-pixels 230 include an R sub-pixel 230, a G sub-pixel 230, and a B sub-pixel 230; the 2n-1 th data line 210 is connected to all the sub-pixels 230 in the 2n-1 th column of sub-pixels 230, and the 2n th row of data lines 210 is connected to all the sub-pixels 230 in the 2n th column of sub-pixels 230; the nth row gate line 220 is connected to all the sub-pixels 230 in the nth row of sub-pixels 230, after each row gate line 220 is turned on, the sub-pixels 230 corresponding to the row gate line 220 are charged through the time-sharing control circuit 240, for example, during the turn-on time of the first row gate line G1, the time-sharing control circuit 240 first charges the sub-pixels 230 in the 2n-1 th column, and then charges the sub-pixels 230 in the 2n th column.

As shown in fig. 4, the gate driving chip 250 receives a frame start signal and a clock signal, and the source driving chip 260 receives a polarity inversion signal (POL), a Low Voltage Differential Signal (LVDS) and a data latch signal (TP); the rising edge of the data latch control signal latches data input to the S-IC, and the falling edge controls the latched data to be released to the panel; the driving circuit 200 includes a timing control circuit 270 and a level shifter 280, wherein the timing control circuit 270 outputs a first preliminary control signal and a second preliminary control signal, and the first control signal and the second control signal are converted by the level shifter 280.

Specifically, the timing control circuit 270 receives the LVDS signal, converts the LVDS signal and outputs the converted LVDS signal to the source driver chip 260 in a mini-LVDS signal format, and also outputs timing control signals such as TP and POL to the source driver chip 260, and the source driver chip 260 outputs the converted LVDS signal to the data lines 210 in the display panel after passing through the time-sharing control circuit 240; the timing control circuit 270 also outputs control signals such as STV and CKV to the gate driving chip 250, and the source driving chip 260 outputs scanning signals for gradually opening the gate lines 220 to the display panel.

In addition, the timing control circuit 270 also outputs T _ SW1 and T _ SW2 to the Level shifter 280 (Level shifter), so as to convert the SW1 and SW2 signals with higher voltage Level, and to turn on the NMOS transistors on the data lines 210 in the odd and even rows of the time-sharing control circuit 240 in a time-sharing manner, and the output terminal of the source driver chip 260 correspondingly charges the sub-pixels 230 on the data lines 210 in the odd and even rows in a time-sharing manner.

The first switch circuit 241 receives a first control signal, the second switch circuit 242 receives a second control signal, and both the first control signal and the second control signal are pulse control signals; in an on period of one of the gate lines 220, the first control signal and the second control signal each have a high level period; when the first control signal is in a high level period, the second control signal is in a low level period, and when the second control signal is in a high level period, the first control signal is in a low level period; in the case of ensuring the pixel charging time, the duration of the period of the high level of the first control signal is equal to the duration of the period of the high level of the second control signal, which may be adjusted to be unequal according to the specific display condition of the display panel, for example, when there is a display unevenness condition somewhere on the display panel, the charging time of the darker part may be extended, and if there is a display unevenness condition corresponding to the first control signal, the duration of the period of the high level of the first control signal may be extended appropriately.

It should be noted that the sum of the on time durations of the first switch circuit 241 and the second switch circuit 242 is less than the on time of one row of scan lines; each row of the gate lines 220 includes a first period, a second period, a third period and a fourth period in an on period; the first control signal is at a high level in a second time period; the second control signal is at a high level in a fourth time period; the rising edge time of the first switch circuit 241 and the second switch circuit 242 and the rising edge time of the data latch signal are the same time; the duration of the first time period is equal to the duration of the third time period, the duration of the second time period is equal to the duration of the fourth time period, and buffering time is given to the first switch circuit and the second switch circuit when the first switch circuit and the second switch circuit are turned on each time.

Specifically, as shown in fig. 5, the time for each row of gate lines 220 to be turned on is about 20.67uS, and since the actual signal sent to the data line 210 to charge the sub-pixels 230 is controlled by the SW1 and SW2 signals, the actual effective charging time for each sub-pixel 230 is the time from the TP1 falling edge to the SW1 or SW2 turning off after the SW1 or SW2 signal is turned on, i.e., the time T1 in fig. 5. As can be seen from the figure, the T1 time is less than 1/2 of the gate opening time, and for the HD model, the effective charging time of about 8uS is still available, which is close to the charging time of the dual gate line structure, and is enough to fill the liquid crystal capacitor.

Taking the opening period of the first gate line G1 as an example, when STV is H and CKV is H, the STV keeps H continuously, the first gate line G1 is opened, in a first time period, SW1 and SW2 are both L, and CKV is H; within a second time period, SW1 and CKV are H, and SW2 is L; in the third time period, SW1, SW2 and CKV are all L; in the fourth time period, SW1 and CKV are L, and SW2 is H; it should be noted that the STV holds H for a first period of time, and continues to hold L after the first period of time; and TP is L in the first time period and the third time period, a rising edge exists in the second time period and the fourth time period, namely when the first switch circuit and the second switch circuit are started, and the duration of the H holding time is less than the duration of the second time period and the fourth time period.

When the STV is H and CKV is H, the gates are turned on row by row starting from G1. During each row on period (1H time is 20.67 uS), SW1 and SW2 are turned on in a time-sharing manner; since the output terminal of the source driver ic 260 charges the sub pixels 230 of the 2 data lines 210 through 1 output channel, the 3 data lines 210 charge the 2 pixels 230 in time division when the same gate line 220 is turned on.

Taking the minimum unit of 3 data lines 210 as an example, when G1 is turned on, SW1 is turned on first, and then when the TP signal falls, S1 outputs R (R11) of the first sub-pixel 230 in the first row, S2 outputs B (B11) of the first sub-pixel 230 in the first row, and S3 outputs G (G12) of the second sub-pixel 230 in the first row; SW2 is then turned on, and at the falling edge of the TP signal, S1 outputs G (G11) of the first sub-pixel 230 in the first row, S2 outputs R (B12) of the second sub-pixel 230 in the first row, and S3 outputs B (B12) of the second sub-pixel 230 in the first row.

Of course, the time for turning on the first switch circuit and the second switch circuit may also be adjusted by the timing control circuit 270, and in the on period of one gate line 220, the time for turning on all the corresponding switch tubes 243 by the first switch circuit may not be equal to the time for turning on all the corresponding switch tubes 243 by the second switch circuit, and may be adjusted according to the actual display condition of the panel.

Referring to fig. 2 to 4, as another embodiment of the present application, a display panel 100 is disclosed, the display panel 100 is divided into a display area 110 and a non-display area 120, the display panel 100 includes a driving circuit 200, the driving circuit 200 includes a plurality of data lines 210 and a plurality of gate lines 220, the plurality of data lines 210 and the plurality of gate lines 220 are interlaced with each other; the data lines 210 and the gate lines 220 respectively drive a plurality of corresponding pixels; the time-sharing control circuit 240 in the driving circuit 200 controls the charging time of different pixels in the same row of the pixels 230; the gate driving chip 250 includes a plurality of gate output terminals, each of which is connected to one of the gate lines 220; and the source electrode driving chip comprises a plurality of source electrode output ends, and each source electrode output end is respectively connected with the two data lines through the time-sharing control circuit.

Each of the pixels 230 includes a plurality of R, B, and G sub-pixels arranged in the same row; the same data line is correspondingly connected with all the R sub-pixels, the B sub-pixels or the G sub-pixels in the same column of pixels; the time-sharing control circuit 240 is disposed in the non-display area 120, and the time-sharing control circuit 240 includes a first switch circuit 241 for receiving a first control signal, a second switch circuit 242 for receiving a second control signal, and a plurality of switch tubes 243; the first control signal and the second control signal are both pulse control signals; the output end of each switching tube is correspondingly connected to the input end of each data line, and the input ends of the switching tubes corresponding to the 2 nth data line and the 2n-1 th data line in the data lines corresponding to the R sub-pixel, the B sub-pixel and the G sub-pixel are simultaneously connected to the same source output end; n is a natural number of 1 or more.

It should be noted that the first control signal and the second control signal both have only one high level period, the high level period of the first control signal and the high level period of the second control signal are in different time periods, and in an on period of one gate line, the first switch circuit and the second switch circuit turn on the corresponding switch tube in a time-sharing manner, so as to output a data signal of the source driver chip to two data lines in a time-sharing manner, and charge the pixel corresponding to the data line.

The technical solution of the present application can be widely applied to various display panels, such as a Tn (Twisted nematic) display panel, an IPS (In-Plane Switching) display panel, a VA (Vertical Alignment) display panel, and an MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as an OLED (Organic Light-Emitting Diode) display panel, can also be applied to the above solution.

The foregoing is a further detailed description of the present application in connection with specific alternative embodiments and it is not intended that the present application be limited to these specific details. For those skilled in the art to which the present application pertains, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be considered as belonging to the protection scope of the present application.

Claims

1. A display panel, comprising a driver circuit, the driver circuit comprising:

a plurality of data lines;

a plurality of gate lines, the gate lines and the data lines being interlaced with each other to form a matrix arrangement;

a plurality of pixels respectively driven by the corresponding data lines and gate lines;

a time-sharing control circuit;

the grid driving chip comprises a plurality of grid output ends, and each grid output end is connected with one grid line; and

the source electrode driving chip comprises a plurality of source electrode output ends, and each source electrode output end is connected with the two data lines through the time-sharing control circuit;

in an opening period of one gate line, the same source output end outputs a data signal to two data lines in a time-sharing manner through the time-sharing control circuit, and the two data lines charge corresponding pixels in a time-sharing manner;

the time-sharing control circuit comprises a first switch circuit, a second switch circuit and a plurality of switch tubes;

the nth source output end is respectively connected with the 2n-1 th data line and the 2 nth data line, and outputs data signals to the 2n-1 th data line and the 2 nth data line through the switch tube; the control ends of the switching tubes corresponding to all the 2n-1 th data lines are connected to the first switching circuit, and the control ends of the switching tubes corresponding to all the 2n-1 th data lines are connected to the second switching circuit;

in an on period of one gate line, a corresponding one of the source output terminals respectively outputs a data signal output by the nth source output terminal to the 2n-1 th data line and the 2n th data line in a time-sharing manner through the corresponding switching tubes by the first switching circuit and the second switching circuit;

n is a natural number greater than or equal to 1;

the closing time of the first switch circuit is different from the opening time of the second switch circuit;

the turn-on time of each data line corresponding to the first switch circuit or the second switch circuit is the turn-on time of the rising edge of the data latch signal corresponding to each data line corresponding to the first switch circuit or the second switch circuit, and the turn-off time of the second switch circuit is the same as the turn-off time of the gate line;

the first switch circuit simultaneously controls all odd-numbered column data to be communicated with the corresponding source electrode output ends; the second switch circuit simultaneously controls all even-numbered columns of data to be communicated with the corresponding source electrode output ends;

and in a line scanning time, the first switch circuit controls all odd-numbered columns of data lines to be communicated with the corresponding source output ends according to the corresponding latch signals, and the latch signals corresponding to the second switch circuit control all even-numbered columns of data lines to be communicated with the corresponding source output ends.

2. A display panel as claimed in claim 1 characterized in that each of said pixels comprises a plurality of sub-pixels arranged in a row;

the same data line is connected with all the sub-pixels in the corresponding same column of pixels; the same gate line is connected with all the sub-pixels in the same corresponding row.

3. The display panel according to claim 1, wherein the first switch circuit receives a first control signal, the second switch circuit receives a second control signal, and the first control signal and the second control signal are both pulse control signals;

the first control signal and the second control signal each have a high level period in an on period of one of the gate lines;

when the first control signal is in a high level period, the second control signal is in a low level period; and when the second control signal is in a high level period, the first control signal is in a low level period.

4. A display panel according to claim 3, wherein the sum of the on times of the first switch circuit and the second switch circuit is less than the on time of one row of gate lines;

each gate line is opened in a cycle which comprises a first time period, a second time period, a third time period and a fourth time period which are continuously connected;

the first control signal is at a high level in the second time period; the second control signal is at a high level during the fourth period.

5. The display panel according to claim 3, wherein the gate driving chip receives a frame on signal and a clock signal, and the source driving chip receives a polarity inversion signal, a low voltage differential signal, and a data latch signal;

the first switch circuit and the second switch circuit determine the turn-on time according to the rising edge of the data latch signal.

6. A display panel as claimed in claim 3 wherein the driving circuit further comprises a timing control circuit and a level shifter, the timing control circuit being coupled to the level shifter, the timing control circuit outputting a first preliminary control signal and a second preliminary control signal to the level shifter, the level shifter converting the first preliminary control signal and the second preliminary control signal into the first control signal and the second control signal for output to the first switch circuit and the second switch circuit of the time-sharing control circuit, respectively.

7. The display panel according to claim 1, wherein the display panel is divided into a display area and a non-display area, and the time division control circuit is provided in the non-display area.

8. The display panel according to claim 1, wherein the first switch circuit and the second switch circuit are not turned on for equal time periods.

9. A display panel divided into a display area and a non-display area, the display panel comprising a driving circuit, the driving circuit comprising:

a plurality of data lines;

a plurality of gate lines, the gate lines and the data lines being interleaved with each other;

the time-sharing control circuit controls the charging time of different pixels in the same row of pixels;

each pixel comprises a plurality of R sub-pixels, B sub-pixels and G sub-pixels which are arranged in the same row; the same data line is correspondingly connected with all the R sub-pixels, the B sub-pixels or the G sub-pixels in the same column of pixels;

the first control signal and the second control signal both have only one high level period, the high level period of the first control signal and the high level period of the second control signal are in different time periods, and in the opening period of one gate line, the first switch circuit and the second switch circuit conduct the corresponding switch tubes in a time-sharing manner so as to output the data signals of the source electrode driving chip to the two data lines in a time-sharing manner and charge the pixels corresponding to the data lines;

n is a natural number greater than or equal to 1;

the closing time of the first switch circuit and the opening time of the second switch circuit are different;

the starting time of each data line corresponding to the first switch circuit or the second switch circuit is the opening time of the rising edge of the data latching signal corresponding to each data line, and the closing time of the second switch circuit is the same as the closing time of the gate line;

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.