KR100965587B1 - The liquid crystal display device and the method for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a method of driving the same, which can reduce power consumption during dot inversion driving and can reduce manufacturing costs by reducing the number of gate ICs of a gate driver. And a liquid crystal panel defined by a plurality of pixel regions defined by a plurality of data lines. The pixel area of each odd line of the liquid crystal panel corresponding to the odd-numbered gate line is driven by the column inversion method for the first 1/2 frame time, and corresponds to the even-numbered gate line during the second 1/2 frame time. And a driving circuit unit for driving the pixel areas of each even line of the liquid crystal panel by the column inversion method.

LCD, Line Inversion Drive, Column Inversion Drive, Dot Inversion Drive, Pixel Voltage Signal, Power Consumption

Description

The liquid crystal display device and the method for driving the same}

1 is a block diagram of a driving circuit of a conventional liquid crystal display device according to the related art.

2A and 2B are views for explaining a line inversion driving method of a conventional liquid crystal display device.

3A and 3B illustrate a column inversion driving method of a conventional liquid crystal display device.

4A and 4B are diagrams for describing a dot inversion driving method of a conventional liquid crystal display device.

5 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

6A is a plan view of a liquid crystal panel for explaining polarities of pixel voltages applied to pixel areas of odd lines during a first 1/2 frame time;

6B is a plan view of a liquid crystal panel for explaining polarities of pixel voltages applied to pixel areas of even lines during a second half frame time;

7 is a signal waveform diagram of an odd line and an even line, and an end gate line and a gate line;

8A-8D are waveform diagrams of data signals applied to any one data line during first and second frame times.

9 is a waveform diagram of a data signal applied to a first first data line during a first to fourth frame time during dot inversion driving and a waveform diagram of a data signal applied to a first data line of the present invention;

＊ Description of symbols for main parts of drawings

100a: liquid crystal panel 100b: drive circuit

111a: Gate Driver 111b: Data Driver

120: timing controller 300a: the odd line

300b: Even line D: Data line

G: gate line G1, G3: odd-numbered gate line

G2, G4: Even-numbered gate line D: Data line

L: termination gate line S1: first switching element

L1: first termination gate line L2: second termination gate line

S2: second switching element T: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof, which can reduce power consumption during dot inversion driving and can reduce manufacturing costs by reducing the number of gate ICs of a gate driver.                         

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways such as a monitor of a television and a computer for receiving and displaying broadcast signals.

Such a liquid crystal display may be classified into a liquid crystal panel displaying a video signal and a driving circuit applying a driving signal to the liquid crystal panel from the outside.

Although not shown in the figure, the liquid crystal panel includes two transparent substrates (glass substrates) bonded to each other with a predetermined space and a liquid crystal layer formed between the two substrates.

Lower gates of the two transparent substrates include a plurality of gate lines arranged at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate line to define a pixel region, and the gate lines And a plurality of pixel electrodes formed in each pixel region having a matrix form defined by a data line and an intersection portion of the gate line and the data line, and are switched in accordance with a scan signal of the gate line to switch the data signal of the data line. A plurality of thin film transistors are applied to each pixel electrode.

On the other upper substrate, a black matrix layer for blocking light in portions other than the pixel regions, a color filter layer for implementing color in each pixel region, and a common electrode for applying a common voltage are formed. do.

Therefore, when the turn-on signal is sequentially applied to the gate line, an image is displayed because the data signal is applied to the pixel electrode of the corresponding line.

A general liquid crystal display device having a liquid crystal panel configured as described above and a data driving circuit for applying data to the liquid crystal panel will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a driving circuit of a conventional liquid crystal display.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 21 having a plurality of gate lines G and data lines D arranged in a direction perpendicular to each other and having a pixel region in a matrix form. The driving circuit unit 22 is configured to supply driving signals and data signals to the liquid crystal panel 21, and a backlight 28 providing a constant light source to the liquid crystal panel 21.

Here, the driving circuit unit 22 may include a data driver 21b for inputting a data signal to each data line D of the liquid crystal panel 21, and a gate line G of the liquid crystal panel 21. A gate driver 21a for applying a gate driving pulse, display data R, G, and B input from the drive system 27 of the liquid crystal panel, vertical and horizontal synchronization signals Vsync, Hsync, and a clock signal DCLK. Receives a control signal DTEN and the like and formats each display data, clock, and control signal at a timing suitable for the data driver 21b and the gate driver 21a of the liquid crystal panel 21 to reproduce the screen. A timing controller 23, a power supply unit 24 for supplying a voltage required to the liquid crystal panel 21 and each unit, and a digital input from the data driver 21b by receiving power from the power supply unit 24. Data ah A constant voltage (Vdd) and a gate high voltage used in the liquid crystal panel 21 by using the gamma reference voltage unit 25 for supplying a reference voltage required for conversion into analog data, and the voltage output from the power supply unit 24. And a DC / DC converter 16 for outputting a VGH, a gate low voltage VGL, a reference voltage Vref, a common voltage Vcom, and the like, and an inverter 29 for driving the backlight 28. It is configured by.

The operation of the driving circuit of the general liquid crystal display device configured as described above is as follows.

That is, the timing controller 23 controls the display data R, G, and B inputted from the driving system 27 of the liquid crystal panel, the control signals DTEN such as the vertical and horizontal synchronization signals Vsync and Hsync, and the clock signal DCLK. ), The data driver 21b and the gate driver 21a of the liquid crystal panel 21 provide each display data, a clock, and a control signal at a timing suitable for reproducing the screen, and thus, the gate driver 21a. Applies a gate driving pulse to each gate line G of the liquid crystal panel 21, and in synchronization therewith, the data driver 21b inputs a data signal to each data line D of the liquid crystal panel 21. Displays the input video signal.

The liquid crystal display device configured as described above deteriorates the liquid crystal layer when the pixel voltage signal in the same direction is continuously applied to the liquid crystal layer. Thus, in order to prevent deterioration of the liquid crystal layer, the pixel electrode from the data line D is prevented. The pixel voltage applied to the driving unit is inverted so as to be positive (+) or negative (-) with respect to the common voltage applied to the common electrode.

As such a polarity inversion driving method, an inversion driving method such as a line inversion system, a column inversion system, or a dot inversion system is used.

2A and 2B are views for explaining a line inversion driving method of a conventional liquid crystal display, and FIGS. 3A and 3B are views for explaining a column inversion driving method of a conventional liquid crystal display, and FIG. 4A. 4B is a view for explaining a dot inversion driving method of a conventional liquid crystal display device.

In the line inversion driving method, as illustrated in FIG. 2A, the pixel regions adjacent to each pixel region in the vertical direction for one frame time have different polarities, and then, as shown in 2b, the next 1 During the frame time, the pixel areas vertically adjacent to each of the pixel areas are inverted to have polarities opposite to the polarities maintained for the first frame time.

However, this line inversion driving method has a problem in that flicker such as a stripe pattern occurs between horizontal lines due to crosstalk between horizontal pixel areas.

In the column inversion driving scheme, as illustrated in FIG. 3A, the pixel regions adjacent to each pixel region in the horizontal direction for the first one frame time have different polarities, and then as shown in 2b. During the next one frame time, the pixel areas horizontally adjacent to each of the pixel areas are inverted so as to have polarities opposite to those maintained for the first one frame time.

However, this column inversion driving method has a problem in that flicker such as a stripe pattern occurs between vertical lines due to crosstalk between vertical pixel areas.

Therefore, in order to solve the problems of the line inversion driving and the column inversion driving, a dot inversion driving method is proposed in which each pixel region and the adjacent pixel regions in the vertical and horizontal directions have different polarities.

In the dot inversion driving scheme, as illustrated in FIG. 4A, the pixel regions adjacent to each pixel region in the horizontal and vertical directions have different polarities during the first one frame time, and as shown in 4b. During the next one frame time, the pixel areas adjacent to each pixel area in the horizontal and vertical directions are inverted so as to have the opposite polarity that was maintained for the first one frame time.

The dot inversion driving method cancels the flicker generated between the adjacent pixel areas in the vertical and horizontal directions, thereby providing an image having excellent image quality compared to other inversion methods.

However, in the dot inversion driving method, the polarity of the pixel voltage signal applied to each pixel area through the data line D in the data driver 21b must be inverted every frame in the horizontal and vertical directions. Compared to the methods, the polarity variation of the data signal applied to each pixel area is increased, thereby increasing power consumption.

The present invention has been made to solve the above problems, and divides a plurality of gate lines into odd-numbered and even-numbered gate lines, and gate signals only on odd-numbered gate lines during the first 1/2 frame time of the first frame. Is applied so that only pixel areas of odd-numbered lines corresponding to the odd-numbered gate lines are provided with a data signal to drive the column inversion method, and only the even-numbered gate lines are provided during the second half frame time of the first frame. By applying a gate signal, the data signal is provided only to pixel areas of even lines corresponding to the even-numbered gate lines, and driven in a column inversion manner so as to be opposite to the polarity of the pixel areas of odd-numbered lines. Reduced power consumption by reducing the amount of variation in the data signal applied to each pixel area To provide a liquid crystal display device and its driving method skill that it is an object.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel defined by a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines perpendicular to each other; The pixel area of each odd line of the liquid crystal panel corresponding to the odd-numbered gate line is driven by the column inversion method for the first 1/2 frame time, and corresponds to the even-numbered gate line during the second 1/2 frame time. It characterized in that it comprises a driving circuit unit for driving the pixel area of each even line of the liquid crystal panel by the column inversion method.

The driving circuit unit may drive the pixel areas of even lines in a column inversion manner to have polarities opposite to those of the odd lines.

The driving circuit unit drives the pixel area of the odd line to have a different polarity during the first 1/2 frame time of the first frame and the first half frame time of the second frame. The pixel areas of the even-numbered lines may be driven in a column inversion manner so as to have different polarities during the second half frame time of the first frame and the second half frame time of the second frame.

The driving circuit unit may include: a plurality of termination gate lines connecting end portions of odd-numbered gate lines and even-numbered gate lines to each other; A gate driver for applying a gate signal to each of the termination gate lines; A plurality of first switching elements for switching gate signals applied to the odd-numbered gate lines; A plurality of second switching elements for switching gate signals applied to the even-numbered gate lines; A timing controller configured to alternately apply a turn-on signal to the first switching element and the second switching element; And a data driver for applying data signals to the plurality of data lines.

The timing controller may alternately apply a turn-on signal to the first switching device and the second switching device in a half frame period.

The data signal may be inverted in polarity every 1/2 frame time.

The data signal during the first half frame time of the odd-numbered frame and the data signal during the first half frame time of the even-numbered frame have different polarities.

In addition, the driving method of the liquid crystal display device according to the embodiment of the present invention configured as described above, in the liquid crystal display device having a plurality of gate lines and data lines perpendicularly intersecting with each other, is an odd number during the first 1/2 frame time. Applying a data signal to a pixel area of an odd line corresponding to the gate line by a column inversion method; And applying a data signal to the pixel areas of the even lines corresponding to the even-numbered gate lines by the column inversion method during the second 1/2 frame time.

The pixel area of the even line may be driven in a column inversion manner to have a polarity opposite to that of the odd line of the pixel area.

The data signal is applied in a column inversion manner to have a polarity opposite polarity applied to the pixel area of each odd-numbered line during the first half frame time of the second frame during the first half frame time of the first frame. Applying; A data signal in a column inversion manner so as to have an opposite polarity of the polarity applied during the second half frame time of the first frame to the pixel area of each even line during the second half frame time of the second frame. Characterized in that further comprises the step of applying.

The data signal may be inverted in polarity every 1/2 frame time period.

In the pixel area corresponding to the same gate line, the polarity of the data signal is reversed at one frame time period.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a schematic configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6A is a diagram of a liquid crystal panel for explaining polarities of pixel voltages applied to pixel areas of odd lines during a first 1/2 frame time. 6B is a plan view of the liquid crystal panel for explaining the polarity of the pixel voltage applied to the pixel areas of the even lines during the second 1/2 frame time.

7 is a signal waveform diagram of an odd line, an even line, and an end gate line and a gate line.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a plurality of gate lines G arranged in a line; A plurality of data lines (D) arranged in a line so as to vertically cross each of the gate lines (G); A plurality of pixel regions defined by the gate lines G and each data line D; A liquid crystal panel (100a) including a thin film transistor (T) formed in each pixel area at a portion where the gate lines (G) and each data line (D) cross each other; The pixel area of each odd line of the liquid crystal panel 100a corresponding to the odd-numbered gate lines G1 and G3 among the plurality of gate lines G is driven by the column inversion method during the first 1/2 frame time. A pixel area of each even line of the liquid crystal panel 100a corresponding to even-numbered gate lines G2 and G4 among the plurality of gate lines G during the second 1/2 frame time period; The driving circuit unit 100b is configured to be driven in a column inversion manner so as to have a polarity opposite to that of the region.

Here, the driving circuit unit 100b will be described in more detail as follows.

The driving circuit unit 100b includes: a plurality of terminal gate lines L connected to one end of an odd-numbered gate line G and an even-numbered gate line G formed in the liquid crystal panel 100a; A gate driver (111a) having a plurality of gate ICs (not shown) for applying a gate signal to each of the termination gate lines (L); First switching elements S1 provided at ends of the odd-numbered gate lines G1 and G3 to switch gate signals transmitted from the first-ended gate lines L1 to the odd-numbered gate lines G1 and G3, respectively. )Wow; A second switching element S2 provided at each end of the even-numbered gate lines G2 and G4 and switching a gate signal transmitted from the second-ended gate line L2 to each of the even-numbered gate lines G; ; A turn-on signal connected to the first switching element S1 at the ends of the odd-numbered gate lines G1 and G3 and arranged perpendicular to the gate lines G, and receiving a turn-on signal applied from the timing controller 120. An odd line 300a for transferring to the first switching element S1; A turn-on signal connected to the second switching element S2 at the ends of the even-numbered gate lines G2 and G4 and arranged perpendicular to the gate lines G, and applied from the timing controller 120. An even line (300b) for transmitting a to the second switching device (S2); And a data driver 111b provided with a plurality of data ICs (not shown) for applying a data signal to the data line D.

Here, the odd line 300a and the even line 300b transfer the turn-on signals applied from the timing controller 120 to the first and second switching devices S1 and S2 as described above. Each of the switching elements S1 and S2 serves to turn on.

At this time, the timing controller 120 alternately sends the turn-on signal to the odd line 300a or even line 300b.

That is, the timing controller 120 applies a turn-on signal only to the odd line 300a during the first 1/2 frame time, and then turns only on the even line 300b during the second 1/2 frame time. The ON signal is applied alternately.

Of course, this is one example, applying a turn-on signal only to the even line 300b during a first half frame time, and then turn-on only to the odd line 300a during a second half frame time. It is also possible to apply a signal.

In the present invention, for convenience of explanation, a turn-on signal is applied only to the odd line 300a during the first 1/2 frame time, and then only to the even line 300b during the second 1/2 frame time. The on signal is to be applied.                     

In addition, the thin film transistor T and the first and second switching devices S1 and S3 may use PMOS or NMOS transistors, and for convenience of description, the present invention will be described using PMOS transistors.

Hereinafter, the operation of the liquid crystal display device configured as described above will be described in detail.

First, as shown in FIGS. 6A and 7, when the turn-on signal output from the timing controller 120 is applied to the odd line 300a for the first 1/2 frame time of the first frame, the odd line The turn-on signal transmitted along 300a turns on the first switching device S1 connected to the ends of the odd-numbered gate lines G1 and G3.

Of course, since the second switching device S2 is connected to the even line 300b and the turn-on signal is not applied to the even line 300b, the second switching device S2 is turned on. -It is kept off.

At the same time, as shown in FIGS. 6A and 7, the gate signal output from the gate driver 111a starts from a first termination gate line L1 and includes a plurality of terminations including the second termination gate line L2. It is sequentially input to the gate line (L).

The gate signals sequentially input to the respective termination gate lines L are branched from the respective termination gate lines L to odd-numbered gate lines G1 and G3 and even-numbered gate lines G2 and G4, respectively. Delivered.

In this case, the gate signal is applied only to the odd-numbered gate lines G1 and G3 to which the turned-on first switching device S1 is connected, and is connected to the second switching device S2 which is in the remaining turn-off state. The gate signal is not applied to even-numbered gate lines G2 and G4.

Accordingly, the thin film transistor T formed in the pixel area of the odd-numbered lines corresponding to the odd-numbered gate lines G1 and G3 is turned on, and is output from the data driver 111b to the data line D. The transmitted data signal is applied to the pixel areas of the odd lines in a column inversion manner, so that the pixel areas of the odd lines have pixel voltages in the order of +,-, +, ...,-.

In summary, the pixel areas of the entire odd-numbered lines are driven in a column inversion method having pixel voltages of +,-, +, ...,-during the first 1/2 frame time of the first frame.

6B and 7, when the turn-on signal output from the timing controller 120 is applied to the even line 300b for a second 1/2 frame time, the even line 300b. The turn-on signal transmitted along) turns on the second switching element S2 connected to the ends of the even-numbered gate lines G2 and G4.

In this case, the gate signal is applied only to each even-numbered gate line G2 and G4 to which the turned-on second switching element S2 is connected, and is connected to the first switching element S1 that is in the remaining turn-off state. The gate signal is not applied to the odd-numbered gate lines G1 and G3.

Accordingly, the thin film transistor T formed in the pixel region of the even line corresponding to the even-numbered gate lines G2 and G4 is turned on, and is output from the data driver 111b to output the data line D. The data signal transmitted to is applied to the pixel areas of each even line in a column inversion method.

Here, the data signal having the opposite polarity of the data signal applied to the pixel area of each odd line is applied to the pixel area of each even line by the column inversion method.

Therefore, the pixel areas of each even line have pixel voltages in the order of-, +,-, ..., +.

In summary, the pixel areas of the entire even lines during the first 1/2 frame time of the first frame are driven in a column inversion method having pixel voltages of-, +,-, ..., +.

As a result, during the first frame time in which the first half frame time and the second half frame time are combined, the entire pixel area in which the pixel areas of the odd and even lines are combined is driven by a dot inversion method.

Subsequently, a turn-on signal output from the timing controller 120 is applied to the order line 300a during the first 1/2 frame time of the second frame, and is transmitted along the order line 300a. The ON signal turns on the first switching device S1 connected to the ends of the odd-numbered gate lines G1 and G3.

In this case, the gate signal is applied only to the odd-numbered gate lines G1 and G3 to which the turned-on first switching device S1 is connected, and is connected to the second switching device S2 which is in the remaining turn-off state. The gate signal is not applied to even-numbered gate lines G2 and G4.                     

Therefore, the pixel area of the odd line, which has pixel voltages of +,-, +, ...,-during the first 1/2 frame time of the first frame, is the first 1/2 frame of the second frame. During the time, a data signal opposite to the polarity is applied and driven in a column inversion manner to have pixel voltages of-, +,-, ..., +.

Subsequently, a turn-on signal output from the timing controller 120 is applied to the even line 300b and is transmitted along the even line 300b during the second 1/2 frame time of the second frame. The ON signal turns on the second switching device S2 connected to the ends of the even-numbered gate lines G2 and G4.

In this case, the gate signal is applied only to each even-numbered gate line G2 and G4 to which the turned-on second switching element S2 is connected, and is connected to the first switching element S1 that is in the remaining turn-off state. The gate signal is not applied to the odd-numbered gate lines G1 and G3.

Therefore, the pixel areas of the even lines, which had pixel voltages of-, +,-, ..., + during the second 1/2 frame time of the first frame, are the second 1/2 frames of the second frame. During the time, a data signal opposite to the polarity is applied and driven in a column inversion manner to have pixel voltages of +,-, +, ...,-.

As a result, when looking at the pixel voltage applied to the entire pixel area of the liquid crystal panel 100a during the first and second frame times, the pixel voltage is driven in a dot inversion method having polarities inverted in the vertical, horizontal and diagonal directions of each pixel area. do.

Here, the waveform of the data signal applied to any one data line D1 in order to compare the power consumption in the liquid crystal display device according to the present invention and the conventional liquid crystal table value during dot inversion driving is as follows. .

8A-8D are waveform diagrams of data signals applied to any one data line during the first and second frame times.

First, as shown in FIG. 8A, when the gate signal is applied only to the odd-numbered gate line G during the first 1/2 frame time of the first frame, the gate signal corresponding to the odd-numbered gate lines G1 and G3 may be applied. The pixel area of each odd line is driven in a column inversion manner by a data signal applied from each data line D. FIG.

In this case, referring to the pixel area (dotted line) to which the data signal output from the first data line D1 is applied, the pixel area of the odd line of one row and one column and the odd line of the third row and one column according to the column inversion driving method Since the pixel region of U must have the same polarity pixel voltage, the waveform of the data signal applied to the first data line D1 during the first 1/2 frame time is + polarity, as shown in FIG. 8A. Will have

As illustrated in FIG. 8B, a gate signal is applied to the even-numbered gate lines G2 and G4 during the second 1/2 frame time of the first frame, and corresponds to the even-numbered gate lines G2 and G4. The pixel region of each even line is driven in a column inversion manner by a data signal applied from each data line (D).

In this case, referring to the pixel region (dotted line portion) to which the data signal output from the first data line D1 is applied, the pixel region of the even lines of the second row and the first column and the fourth row of the first column according to the column inversion driving method Since the pixel areas of the even lines should have the same polarity, the waveform of the data signal applied to the first data line D1 during the second half frame time has a polarity as shown in FIG. 8B. To have.

In this way, the waveform of the data signal applied to the first data line D1 during the first frame time has two polarity changes.

Subsequently, as shown in FIG. 8C, a gate signal is applied to the odd-numbered gate lines G1 and G3 during the first 1 / 2-frame time of the second frame, and the pixel region of each odd-numbered line is formed in the first frame. It is driven in a column inversion manner to have a polarity opposite to that which was formed during the first half frame time (FIG. 8A).

In this case, referring to the pixel area (dotted line) to which the data signal output from the first data line D1 is applied, the pixel area of the odd line of one row and the first column and the odd number of the third row of one column according to the column inversion driving method Since the pixel areas of the lines must have the same polarity, the waveform of the data signal applied to the first data line D1 during the first 1/2 frame time of the second frame is as shown in FIG. -It has polarity.

Subsequently, as shown in FIG. 8D, when the gate signal is applied only to the even-numbered gate lines G2 and G4 during the second half-frame time of the second frame, the pixel region of each even line is the first frame time. It is driven in a column inversion manner so as to have a polarity opposite to that which was formed during the second half frame time of FIG. 8B.

In this case, referring to the pixel area (dotted line) to which the data signal output from the first data line D1 is applied, the pixel area of the even line of 2 rows and 1 column and the even number of 4 rows and 1 column according to the column inversion driving method will be described. Since the pixel areas of the lines must have the same polarity, the waveform of the data signal applied to the pixel areas of each even line corresponding to the first data line D1 during the second 1/2 frame time of the second frame is , As shown in FIG. 8D, it has a + polarity.

By repeating this process, the waveform of the data signal applied to the first data line D1 and the data applied to the conventional first data line during the first, second, third and fourth time frames which are consecutive in time. The waveforms of the signals are compared as follows.

FIG. 9 is a waveform diagram of a data signal applied to a first first data line during a first to fourth frame time during dot inversion driving, and a waveform diagram of a data signal applied to a first data line of the present invention.

As shown in Fig. 9A, the data signal of the present invention has a much smaller amount of change in polarity at the same frame time than in the conventional data signal.

That is, within any one frame time, the data signal of the present invention performs two polarity inversions, as shown in Fig. 9A, and the conventional data signal is shown in Fig. 9B. As shown, there are four polarity inversions.

Therefore, even when the same dot inversion driving, the liquid crystal display according to the present invention has the advantage that the power consumption is reduced more than the conventional liquid crystal display.

Further, in the liquid crystal display according to the present invention, each of the odd-numbered gate lines G1 and G3 and the even-numbered gate lines G2 and G4 are connected to the terminal gate line L in pairs.

Therefore, in order for the gate driver 111a to apply a gate signal to each of the gate lines G, the gate driver 111a may apply to the terminal gate lines L connecting the gate lines G in pairs. The number of gate ICs of the driver 111a can be reduced.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display device and the driving method thereof according to the present invention have the following effects.

First, the odd-numbered and even-numbered gate lines are separated from each other by using the odd line and the even line to drive them in the column inversion method, and then driven in the same manner as the dot inversion drive for one frame time. By doing so, power consumption can be reduced.

Second, each odd-numbered gate line and each even-numbered gate line are connected to one end gate line, and the end gate line is connected to a gate driver, so that the number of gate ICs for outputting a gate signal to each gate line is determined. Can be reduced.

Claims (12)

A liquid crystal panel defined by a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines perpendicular to each other; The pixel area of each odd line of the liquid crystal panel corresponding to the odd-numbered gate line is driven by the column inversion method for the first 1/2 frame time, and corresponds to the even-numbered gate line during the second 1/2 frame time. A driving circuit unit for driving the pixel areas of each even line of the liquid crystal panel by a column inversion method; The drive circuit unit, A plurality of termination gate lines connecting the ends of the odd-numbered gate lines and the even-numbered gate lines to each other; A gate driver for applying a gate signal to each of the termination gate lines; A plurality of first switching elements for switching gate signals applied to the odd-numbered gate lines; A plurality of second switching elements for switching gate signals applied to the even-numbered gate lines; A timing controller configured to alternately apply a turn-on signal to the first switching element and the second switching element; And a data driver for applying data signals to the plurality of data lines. The method of claim 1, And the driving circuit unit drives the pixel areas of even lines to have a polarity opposite to the pixel areas of odd lines. The method of claim 1, The driving circuit unit drives the pixel area of the odd line to have a different polarity during the first 1/2 frame time of the first frame and the first half frame time of the second frame. The pixel area of the even line is driven in a column inversion manner so as to have different polarities during the second half frame time of the first frame and the second half frame time of the second frame. LCD display device. delete The method of claim 1, And the timing controller alternately applies a turn-on signal to the first switching element and the second switching element in a half frame period. The method of claim 3, wherein And the polarity of the data signal is reversed every 1/2 frame time. The method of claim 5, And a data signal during a first half frame time of an odd frame and a data signal during a first half frame time of an even frame have different polarities. In a driving method of a liquid crystal display device comprising a liquid crystal panel having a plurality of gate lines and data lines perpendicular to each other and a driving circuit unit for driving the liquid crystal panel, The operation process of the drive circuit unit, Applying a data signal to a pixel area of an odd line corresponding to an odd gate line during a first 1/2 frame time by a column inversion method; Applying a data signal in a column inversion manner to the pixel areas of the even lines corresponding to the even-numbered gate lines during the second half frame time; The driving circuit unit, A plurality of termination gate lines connecting the ends of the odd-numbered gate lines and the even-numbered gate lines to each other; A gate driver for applying a gate signal to each of the termination gate lines; A plurality of first switching elements for switching gate signals applied to the odd-numbered gate lines; A plurality of second switching elements for switching gate signals applied to the even-numbered gate lines; A timing controller configured to alternately apply a turn-on signal to the first switching element and the second switching element; And a data driver for applying data signals to the plurality of data lines. The method of claim 8, And driving the pixel areas of the even lines in a column inversion manner to have polarities opposite to those of the odd lines. The method of claim 8, The data signal is applied to the pixel area of each odd-numbered line during the first half frame time of the second frame in a column inversion manner so as to have the opposite polarity of the polarity applied during the first half frame time of the first frame. To; A data signal in a column inversion manner so as to have an opposite polarity of the polarity applied during the second half frame time of the first frame to the pixel area of each even line during the second half frame time of the second frame. Method of driving a liquid crystal display device, characterized in that for applying. The method of claim 8, And wherein the polarity of the data signal is reversed every 1/2 frame time period. The method of claim 8, And a polarity of the data signal is reversed in one pixel time period in the pixel region corresponding to the same gate line.

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