KR100486998B1 - Method For Driving Liquid Crystal Panel And Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a driving method and apparatus for driving a liquid crystal panel having five color dots in one pixel and reducing flicker.

According to an exemplary embodiment of the present invention, a method of driving a liquid crystal panel includes shorting a subpixel of a first color disposed in a central portion of a pixel, and shorting the subpixels of the first color spaced apart from the subpixels of the first color by a predetermined interval. Applying data of a first color to subpixels of a first color; Applying data of a second color to a plurality of sub-pixels of a second color arranged at one edge of the one pixel based on the sub-pixel of the first color; And applying data of a third color to subpixels of a plurality of third colors disposed at the other edge of the first pixel, based on the subpixel of the first color.

Description

Liquid crystal panel driving method and liquid crystal display device {Method For Driving Liquid Crystal Panel And Liquid Crystal Display}

The present invention relates to a liquid crystal panel, and more particularly, to a method and apparatus for driving a liquid crystal panel capable of driving a liquid crystal panel having five color dots in one pixel and reducing flicker.

In general, a liquid crystal display (LCD) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. An active matrix liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

1 is a block diagram illustrating a general liquid crystal display device.

Referring to FIG. 1, a driving device of a liquid crystal display device is to supply video data to a digital video card 1 for converting analog video data into digital video data and data lines DL of a liquid crystal panel 6. A data driver 3, a gate driver 5 for sequentially driving the gate lines GL of the liquid crystal panel 6, and a timing controller for controlling the data driver 3 and the gate driver 5. (2) is provided.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 6 is formed such that the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the TFT has a gate terminal connected to the gate line GL, and a source terminal connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The digital video card 1 converts an analog input video signal into a digital video signal suitable for the liquid crystal panel 6 and detects a synchronization signal included in the video signal.

The timing controller 2 supplies the digital video data of red (R), green (G) and blue (B) from the digital video card 1 to the data driver 3. In addition, the timing controller 2 uses the horizontal and vertical synchronization signals H and V input from the digital video card 1 to output data such as a dot clock Dclk and a gate start pulse Gsp and a gate control signal. It generates and timing-controls the data driver 3 and the gate driver 5. A data control signal such as a dot clock Dclk is supplied to the data driver 3, and a gate control signal such as a gate start pulse Gsp is supplied to the gate driver 5.

The gate driver 5 includes a shift register (not shown) that sequentially generates scan pulses in response to a gate start pulse Gsp input from the timing controller 2, and a voltage of the scan pulses of the liquid crystal cell Clc. And a level shifter (not shown) for shifting to a level suitable for driving. In response to the scan pulse input from the gate driver 5, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The dot clock Dclk is input to the data driver 3 together with the red (R), green (G), and blue (B) digital video data from the timing controller 2. The data driver 3 latches the red (R), green (G), and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 3 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

FIG. 2 is a diagram illustrating in detail a relationship between a pixel and a TFT structure of the liquid crystal display of FIG.

Referring to FIG. 2, a pixel of a liquid crystal display includes a region partitioned by four data lines DL1 to DL4 and two gate lines GL1 and GL2. In addition, one pixel electrode 12a is disposed in an area surrounded by the gate lines GL1 and GL2 and the data lines DL1 and DL2 so that the region becomes one pixel, and the gate lines GL1 and GL2. ) And one pixel electrode 12b is provided in an area surrounded by the data lines DL2 and DL3, and this area becomes one pixel. The gate lines GL1 and GL2 and the data lines DL3 and DL4 are provided. 1 pixel electrode 12c is provided in the area surrounded by the dot), and this area becomes one pixel. One pixel 16 is comprised by these three pixels, and the TFT 14 as a switch element is comprised in the side part of each pixel electrode 12, respectively.

In addition, color filters R, G, and B are provided on another substrate where the pixel electrodes face the transparent substrate. In this form, the color filter of R is arrange | positioned at the position which opposes the pixel electrode 12a of the left end among the one pixel shown in FIG. 2, and G is located in the position which opposes the pixel electrode 12b of the middle part as shown in FIG. Color filters are arranged, and B color filters are arranged at positions opposite to the pixel electrode 12c at the right end.

In this form, since 640 data lines DL and 480 gate lines GL are provided to display the VGA specification, 307200 pixels are formed on one screen.

FIG. 3 is a view showing an RGB color filter arrangement state and a connection state of the gate driver 5 and the data driver 3 according to the liquid crystal display of the prior art shown in FIG.

Referring to FIG. 3, the LCD receives 6-bus input signals Re, Ge, Be, Ro, Go, and Bo, and inputs input signals from 1 to nth data lines DL1 to DLn in synchronization with the data clock. Through)

The R signal is output to the first data line DL1 through the data driver 3, the G signal is output to the second data line DL2 through the data driver 3, and the B signal is output to the data driver 3. The third data line DL3 is output through the third data line DL3. The R, G, and B signals have three outputs formed in one pair and are outputted by repeating this one pair.

In this case, the B signal is output to the first data line DL1 through the data driver 3, and the G signal is output to the second data line DL2 through the data driver 3 according to the line arrangement through the data driver 3. ) And the R signal is output to the third data line DL3 through the data driver 3.

The liquid crystal panel driven by the conventional liquid crystal display device adopts a dot inversion method as shown in Figs. 4A and 4B. In the method of driving a dot inversion type liquid crystal panel, as shown in FIGS. 4A and 4B, data signals having opposite polarities are supplied to adjacent liquid crystal cells for each column line and row line on the liquid crystal panel, and each frame is arranged on the liquid crystal panel. The polarities of the data signals supplied to all liquid crystal cells are reversed. In other words, when the video signal of one frame is displayed in the dot inversion method, the process proceeds from the upper left liquid crystal cell to the right liquid crystal cell and to the lower liquid crystal cells as shown in FIG. 4A. The data signals are supplied to the liquid crystal cells on the liquid crystal panel so that the polarity (+) and the negative polarity (−) appear alternately. When the video signal of the next frame is displayed, as shown in FIG.

However, the conventional method of driving a liquid crystal panel having a stripe pixel has a limitation in improving image quality, and there is a problem in that a flicker phenomenon occurs when the liquid crystal panel is driven by a dot inversion method.

Accordingly, an object of the present invention is to provide a method for driving a liquid crystal panel and a driving device for driving the liquid crystal display device having five color dots in one pixel.

In order to achieve the above object, a method of driving a liquid crystal panel according to the present invention includes a subpixel of a first color disposed at a central portion of a pixel, and a subpixel of a first color spaced apart from the subpixels of the first color at predetermined intervals. Shorting subpixels to apply data of a first color to subpixels of the adjacent first color; Applying data of a second color to a plurality of sub-pixels of a second color arranged at one edge of the one pixel based on the sub-pixel of the first color; And applying data of a third color to subpixels of a plurality of third colors disposed at the other edge of the first pixel, based on the subpixel of the first color.

In this case, the applying of the data of the second color may include applying the data to the subpixels of the second color arranged correspondingly in the diagonal direction with respect to the subfield of the first color in the pixel. It is done.

In addition, applying the data of the third color may include applying data to the subpixels of the third color arranged in the pixel in a diagonal direction with respect to the subfield of the first color. do.

The driving apparatus of the liquid crystal panel according to the present invention includes a subpixel of a first color disposed at the center of a pixel, and a plurality of second colors disposed at one edge of the one pixel based on the subpixel of the first color. In a driving apparatus of a liquid crystal panel in which subpixels and pixels including subpixels of a plurality of third colors arranged on the other edge of the first pixel in the one pixel are arranged in a matrix form. And signal selection means for selectively selecting the sub-pixels to input red, green, and blue data, and generating a control signal for controlling the signal selection means by using a vertical synchronous signal and a dot clock input from the outside. And a liquid crystal panel for applying control data generating means and data output by the signal selecting means to the sub-pixels to display an image. Gong.

The signal selecting means in the present invention comprises first signal selecting means for alternately supplying red data and green data first by the control signal when the liquid crystal panel is driven, and a first means for supplying blue data at predetermined intervals. And two signal selecting means.

The control signal generating means in the present invention comprises a first control signal generating means for applying a control signal for supplying the green data at predetermined intervals using a dot clock, and the signal selecting means using a vertical synchronous signal; And second control signal generating means for applying a control signal to the first control signal generating means.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 13.

5 is a block diagram illustrating a general liquid crystal display device.

Referring to FIG. 5, a driving device of a liquid crystal display device is to supply video data to a digital video card 21 for converting analog video data into digital video data and to data lines DL of the liquid crystal panel 26. The data driver 23, the gate driver 25 for sequentially driving the gate lines GL of the liquid crystal panel 26, and the timing controller for controlling the data driver 23 and the gate driver 25. (22) is provided.

In the liquid crystal panel 26, liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the TFT has a gate terminal connected to the gate line GL, and a source terminal connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The digital video card 21 converts an analog input video signal into a digital video signal suitable for the liquid crystal panel 26 and detects a synchronization signal included in the video signal.

The timing controller 22 supplies the red (R), green (G), and blue (B) digital video data from the digital video card 21 to the data driver 23. In addition, the timing controller 22 uses the horizontal / vertical synchronization signals H and V input from the digital video card 21 to control data and gate control such as dot clock Dclk and gate start pulse Gsp. The signal is generated to timing control the data driver 23 and the gate driver 25. A data control signal such as a dot clock Dclk is supplied to the data driver 23, and a gate control signal such as a gate start pulse Gsp is supplied to the gate driver 25.

The gate driver 25 is adapted to drive the liquid crystal cell with a shift register that sequentially generates scan pulses in response to a gate control signal such as a gate start pulse Gsp input from the timing controller 22, and a scan pulse voltage. Level shifter and the like for shifting to the level. In response to the scan pulse input from the gate driver 25, the video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The data driver 23 receives data control signals such as dot clock Dclk together with digital video data of red (R), green (G), and blue (B) from the timing controller 22. The data driver 23 latches the red (R), green (G), and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 23 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

6A and 6B are diagrams illustrating pixel structures of a liquid crystal panel and data input to pixels according to the first and second exemplary embodiments of the present invention.

6A and 6B, a pixel of the liquid crystal panel is composed of five different color dots in one pixel.

The pixel 27 has a square shape, and the pixel 27 has a dot 30 having a rhombic B color filter and an upper left corner of the dot 30 having a B color filter so as to be inscribed to the square pixel. Dots 28a and 28b each having an R color filter at the lower right edge and dots 29a and 29b each having a G color filter at the upper right and lower left edges with respect to the dot 30 having the B color filter, respectively. do.

FIG. 6A illustrates a structure in which B dots 30 among five dots are alternately connected to each of the lower data line DL and the upper data line DL every two pixels by being positioned between two data lines. The dot 31 is disposed between two data lines and alternately connected to the lower data line DL and the upper data line DL every pixel. As a result, the B dot 30 displays colors only in two pixels based on four pixels.

In addition, the method of driving a liquid crystal panel having five color dots in one pixel is different from the conventional method in which the data enable signal is periodically applied to the R, G, and B data signals. It is characterized by inputting alternating G data signal once every R data signal once every GL.

For this driving, another driving method of a liquid crystal panel and a new data driver are proposed.

7A and 7B are diagrams schematically showing a connection state of a data driver for driving the liquid crystal panel of the pixel structure and wiring shown in FIG. 6A.

Referring to FIGS. 7A and 7B, the data driver 23 of the liquid crystal display receives the six-bus input signals Re, Ge, Be, Ro, Go, and Bo in order to synchronize with the data clock to the 1st to Nth times. The data signal is output to the data lines DL1 to DLN.

In the present invention, in the output terminal connected to the data driver 23, the second and fifth output terminals of every 12 output terminals are disconnected from the data line DL.

Subsequently, the eighth and eleventh output terminals from the data driver 23 are normally connected to the data line DL to output and drive B dot data.

This connection method applies to all N-th output terminals.

8 is a diagram illustrating in detail a data pulse generator for generating data in a pixel as in FIG. 7.

Referring to FIG. 8, the data pulse generator may include multiplexers (hereinafter referred to as “MUXs”) and timing controllers 22 that control color data R, G, and B to be selectively input through the timing controller 22. D-flip flops 31, 32 and 33 in response to a control signal from

The MUXs include: a first multiplexer (MUX1) for allowing R data to be input when driving odd data and G data to be input when driving even data; A second multiplexer MUX2 for inputting G data when driving odd data and for inputting R data when driving even data; A third multiplexer MUX3 for selectively inputting B data when the odd data and the even data are driven; A fourth multiplexer MUX4 is connected to the third multiplexer MUX3 and supplies a control signal for controlling the third multiplexer MUX3. The fourth multiplexer MUX4 may be replaced with a tri-state buffer or a control switch.

The D-flip flops 31, 32, and 33 are a series connection of the first and second flip-flops 31, 32 and the timing controller 22 to cause the input dot clock Dclk to be output as a four-divided control pulse. And a third D-flip-flop 33 which is controlled by the horizontal synchronization signal from and supplies a control signal to the first, second and fourth multiplexers MUX1, MUX2 and MUX4. The dot clock Dclk from the timing controller 22 is input to the clock terminal CLK of the first D flip-flop 31. Among the output terminals Q and Q 'of the first D-flip flop 31, an output signal from the inverted output terminal Q' is input to the input terminal D of the first D-flip flop 31. . The output signal from the non-inverting output terminal Q among the output terminals Q and Q 'of the first D flip-flop 31 is input to the clock terminal CLK of the second D flip-flop 32. . Among the output terminals Q and Q 'of the second D-flop flop 32, an output signal from the inverted output terminal Q' is input to the input terminal D of the second D-flop flop 32. . The output signal from the non-inverting output terminal Q among the output terminals Q and Q 'of the second D flip-flop 32 is input to the fourth multiplexer MUX4. When the dot clock Dclk is input from the timing controller 22, the first and second D-flip flops 31 and 32 connected in series are divided into four divided control pulses of the second D-flip flop 32. Output to the non-inverting output terminal (Q). The four-divided control pulse output to the non-inverting output terminal Q of the second D flip-flop 32 has a frequency corresponding to one quarter of the dot clock Dclk. The four divided control pulses are input to the fourth multiplexer MUX4. The horizontal synchronization signal Hsync from the timing controller 22 is input to the clock terminal CLK of the third D flip-flop 33, and the output terminals Q, of the third D flip-flop 33 are provided. The output signal from the inverting output terminal Q 'of Q') is input to the input terminal D of the third D-flop flop 33. The output signal from the inverting output terminal Q of the third D flip-flop 33 is input to the first, second and fourth multiplexers MUX1, MUX2, and MUX4. When the dot clock Dclk is input to the third D-flop flop 33 from the timing controller 22, the third flip-flop 33 receives the first, second, and fourth multiplexers in which the control pulse of the divided frequency is divided into two. It is input to (MUX1, MUX2, MUX4). The two divided control pulses have a frequency corresponding to one half of the horizontal synchronization signal.

Further, the first multiplexer MUX1 receives the R and G data and selects and outputs the color signal by the control signal output by the third D-flip-flop 33. The second multiplexer MUX2 receives input of G and R data, and selects and outputs the color signal by the control signal output by the third D-flip-flop 33. The third multiplexer MUX3 receives the B data and selectively outputs the B data signal according to a control signal of the fourth multiplexer MUX4 controlled by the third D-flip-flop 33. . The control signal from the fourth multiplexer MUX4 has a control pulse divided into four periods in any one of the periods of the odd and even horizontal sync signals. Preferably, the control signal from the fourth multiplexer MUX4 has a control pulse divided by four in the period of the odd-numbered horizontal synchronization signal.

9A and 9B are diagrams for explaining that odd and even color data are output to a data line through the driving apparatus in FIG.

9A and 9B, the driving method of the liquid crystal display according to the first exemplary embodiment of the present invention includes an R data bus and a G data bus to drive the liquid crystal panel 26 having five color dots in one pixel. In each scan line, the R data signal is input one time and the G data signal is alternately input once.

The B data signal is driven as in the prior art, but as shown in FIG. 8, the R data is driven by the D-flip flop 33 and the connection between the output terminal of the data driver 23 and the data line DL. While the G data signal is input four times, respectively, two times as shown in FIGS. 9A and 9B are input. That is, when the R data signal is input first, the B data signal generates the third and fourth data signals B3 and B4, and when the G data signal is input first, the first and second data signals B1 and B2 are generated. Will be.

10A and 10B are diagrams schematically showing a connection state of a data driver for driving the liquid crystal panel of the pixel structure and wiring shown in FIG. 6B.

Referring to FIGS. 10A and 10B, the liquid crystal display device receives a six bus input signal (Re, Ge, Be, Ro, Go, Bo) in FIG. 6B and synchronizes with a data clock. The input signals Re, Ge, Ro, Go, and Bo are input to output the first to Nth data lines DL1 to DLN.

In the present invention, in the output terminal connected to the data driver 23, the second and eighth output terminals of every twelve output terminals are disconnected from the data line DL.

Thereafter, the fifth and eleventh output terminals from the data driver 23 are normally connected to the data line DL to output and drive B data.

The same connection method applies to the Nth output terminal.

FIG. 11 is a diagram illustrating in detail a data pulse generator for generating data in a pixel as in FIGS. 10A and 10B.

Referring to FIG. 11, the data pulse generator includes multiplexers MUX1 to MUX4 controlled to selectively input pixel data through the timing controller 22, and a control signal from the timing controller 22 to be controlled. -Consists of flip flops 34,35.

The multiplexers MUX1 to MUX4 include a first multiplexer MUX1 to which R data is input when driving odd data and G data is input when driving even data; A second multiplexer (MUX2) configured to input G data when driving odd data and to input R data when driving even data; A third multiplexer MUX3 for selectively inputting B data when driving odd data and even data; A fourth multiplexer MUX4 is connected to the third multiplexer MUX3 and outputs a control signal for controlling the third multiplexer MUX3.

The D-flip flops 34 and 35 are controlled by the dot clock Dclk from the timing controller 22 and transmit a control signal to the fourth multiplexer MUX4, and the first D-flip flops 34 are inputted. A second D-flip flop 35 is provided to output the horizontal synchronous signal Hsync once as a pulse divided into two divided forms.

The dot clock Dclk from the timing controller 22 is input to the clock terminal CLK of the first D flip-flop 34, and the output terminals Q and Q ′ of the first D flip-flop 34 are provided. ), The output signal from the inversion output terminal Q 'is input to the input terminal D. In addition, an output signal from the non-inverting output terminal Q among the output terminals Q and Q 'of the first D-flip flop 34 is input to the fourth multiplexer MUX4.

The horizontal synchronization signal Hsync from the timing controller 22 is input to the clock terminal CLK of the second D flip-flop 35, and the output terminals Q and Q of the second D flip-flop 35 are provided. An output signal from the inversion output terminal Q 'is input to the input terminal D. The output signal from the non-inverting output terminal Q among the output terminals Q and Q 'of the second D-flop flop 35 is the fourth multiplexer MUX4, the first multiplexer MUX1 and the second multiplexer ( MUX2).

When the horizontal synchronizing signal Hsync is input from the timing controller 22, a controlled pulse having a shape divided into two by the second D-flip flop 35 is output to the non-inverting output terminal Q.

In addition, when the dot clock Dclk is input to the first D-flip-flop 34 from the timing controller 22, a controlled pulse having a divided frequency is input to the fourth multiplexer MUX4.

The first multiplexer MUX1 receives the R and G data and selects and outputs the color signal by the control signal output by the second D-flip-flop 35. The second multiplexer MUX2 receives input of G and R data, and selects and outputs the color signal by the control signal output by the second D-flip-flop 35. The third multiplexer MUX3 receives the B data and selectively outputs the color signal by an input signal of the fourth multiplexer MUX4 controlled by the second D-flip-flop 35.

12A and 12B are diagrams showing that odd and even color data are outputted to a data line through a data driver through the driving device of FIG.

12A and 12B, in the driving method of the liquid crystal display according to the second exemplary embodiment of the present invention, as described with reference to FIGS. 9A and 9B, in order to drive a liquid crystal panel having five color dots in one pixel, R The data bus and the G data bus alternately input one R data signal and one G data signal every scan line.

As shown in FIG. 11, the R and G data signals are respectively driven by the driving of the D-flip flops 34 and 35 and the connection relationship between the output terminal of the data driver 23 and the data line DL. While being input four times, it is input twice as shown in FIGS. 12A and 12B. For example, when the R data signal is input first, the second and fourth data signals B2 and B4 are generated in the B data signal, and when the G data signal is input first, the first and third data signals B1 and B3. Will be generated. The B data signal repeats the signal generation pattern as described above. Accordingly, even-numbered B data signals are generated when the R data signal is input first, and even-numbered B data signals are generated when the G data signal is input first.

6 to 12 illustrate a case where a part of the output terminal of B data is disconnected in order to drive a liquid crystal panel having five color dots in one pixel using a conventional data driver as it is.

A new type of data driver can be manufactured and used to drive a liquid crystal panel configured in such a pixel form.

In detail, a typical data driver outputs three dots of color dots, and thus has three times as many output channels as the 384 channel. However, in the present invention, one color dot (B color dot) is used to generate six color dots. Since the output terminal of is disconnected, the output terminal from the data driver may have only 5 times as many channels as the 320 channel. As a result, a pixel can be driven by driving a data driver having a 5-fold channel.

13A and 13B are diagrams illustrating polar patterns of data signals supplied to pixels of the liquid crystal panel by the method of driving the liquid crystal panel shown in FIG. 6.

Referring to FIGS. 13A and 13B, pixels are arranged in a matrix in a shape of a lozenge inscribed in a square.

In the first pixel of FIG. 13A, the polarity of the upper left and upper right is positive (+) and the polarity of the lower left and lower right is negative with respect to the B-shaped data of the center. At this time, the polarity of the central B data becomes positive (+).

In the second pixel, the polarity of the upper left and upper right is negative (-) and the polarity of the lower left and lower right is positive (+) centering on the B-shaped data in the center. At this time, the polarity of the central B data becomes negative (-).

In the third pixel, the upper left-right polarity is positive (+) and the lower left-right polarity is negative (-) centering on the B-shaped data of the center. At this time, the polarity of the central B data becomes negative (-).

In the fourth pixel, the polarity of the upper left and upper right is negative (-) and the polarity of the lower left and lower right is positive (+) centered on the B-shaped data of the center. At this time, the polarity of the central B data becomes positive (+).

In the first pixel of FIG. 13B, the polarity of the upper left-right upper end is negative polarity (-) and the polarity of the lower left-right lower center is positive (+) centered on the B-shaped data of the center. At this time, the polarity of the central B data becomes negative (-).

In the second pixel, the polarity of the upper left and upper right is positive (+) and the polarity of the lower left and lower right is negative (-) centering on the B-shaped data of the center. At this time, the polarity of the central B data becomes positive (+).

In the third pixel, the upper left-right polarity is negative (-) and the lower left-right polarity is positive (+) centered on the B-shaped data of the center. At this time, the polarity of the central B data becomes positive (+).

In the fourth pixel, the polarity of the upper left and upper right is positive (+) and the polarity of the lower left and lower right is negative (-) centering on the B-shaped data of the center. At this time, the polarity of the central B data becomes negative (-).

In this manner, the polarity patterns of the data signals supplied to the pixels of the liquid crystal panel according to the present invention alternately repeat FIGS. 13A and 13B and have voltage-charge characteristics for each dot throughout the panel.

As described above, the method and apparatus for driving the liquid crystal display according to the present invention vary the connection relationship between the output terminal of the data driver and the data line in order to drive the liquid crystal panel having five color dots in one pixel. By using a new data driver with a different number of output terminals, the liquid crystal panel of the dot inversion method is driven and flicker is reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a general liquid crystal display device;

FIG. 2 is a diagram illustrating in detail a relationship between a pixel and a TFT structure of the liquid crystal display of FIG.

FIG. 3 is a view illustrating an RGB color filter arrangement state and a connection state of a gate driver and a data driver according to the prior art of the liquid crystal display shown in FIG. 1;

4A and 4B illustrate a dot inversion scheme according to the prior art.

5 is a block diagram showing a liquid crystal display device according to the present invention;

6A and 6B illustrate a pixel structure of a liquid crystal panel and data input to pixels according to first and second embodiments of the present invention.

7A and 7B schematically show a connection state of a data driver for driving the liquid crystal panel of the pixel structure and wiring shown in FIG. 6A;

8 illustrates in detail a data pulse generator for generating data in a pixel as in FIGS. 7A and 7B.

9A and 9B are diagrams for explaining that odd and even color data are output to a data line through the driving apparatus in FIG.

10A and 10B schematically show a connection state of a data driver for driving the liquid crystal panel of the pixel structure and wiring shown in FIG. 6B;

FIG. 11 illustrates in detail a data pulse generator for generating data in a pixel as in FIGS. 10A and 10B.

12A and 12B are diagrams showing that odd and even color data are output to a data line through a data driver through the driving apparatus in FIG.

13A and 13B illustrate polar patterns of data signals supplied to pixels of a liquid crystal panel by the method of driving the liquid crystal panel shown in FIGS. 6A and 6B.

<Description of the symbols for the main parts of the drawings>

1:21: digital video card 2:22: timing controller

3,23: data driver 5,25: gate driver

6,26 liquid crystal panel 12 pixel electrode

14 TFT 16: Pixel

27: pixel 28: dot with R color filter

29: Dot with G color filter 30: Dot with B color filter

31,32,33,34,35: D-flip flop

Claims (9)

In the method of driving the liquid crystal panel, A subpixel of a first color disposed in the center of the pixel, and a subpixel of the adjacent first color spaced apart from the subpixel of the first color by a predetermined interval to short-circuit the subpixels of the adjacent first color. Applying color data; Applying data of a second color to a plurality of sub-pixels of a second color arranged at one edge of the one pixel based on the sub-pixel of the first color; Driving data of a third color to sub-pixels of a plurality of third colors disposed at the other edge of the first pixel, based on the sub-pixel of the first color; Way. The method of claim 1, The applying of the data of the second color may include applying data to the subpixels of the second color arranged in a diagonal direction with respect to the subpixel of the first color in the pixel. Method of driving a liquid crystal panel. The method of claim 1, The applying of the data of the third color may include applying data to the subpixels of the third color arranged correspondingly in a diagonal direction with respect to the subpixel of the first color in the one pixel. Method of driving a liquid crystal panel. The method of claim 2, And causing the sub-pixels of the second color corresponding to each other in the diagonal direction to respond to data signals having opposite polarities to each other. The method of claim 3, wherein And causing the sub-pixels of the third color corresponding to the diagonal direction to respond to data signals having polarities opposite to each other. The method of claim 1, And causing the plurality of first colors of the sub-pixels disposed in the center of the pixel to respond to data signals having opposite polarities at predetermined intervals. Subpixels of a first color disposed at the center of the pixel, a plurality of subpixels of a second color arranged at one edge of the first pixel in the one pixel, and within the pixel; A driving apparatus of a liquid crystal panel in which pixels including a plurality of third pixels subpixels disposed at other edges of the first color subpixel are arranged in a matrix form. Signal selection means for selectively selecting the sub-pixels to input red, green and blue data; And a control signal generating means for generating a control signal for controlling the signal selecting means by using a horizontal synchronous signal and a dot clock inputted from the outside, The data output by the signal selecting means is applied to the sub-pixels so that an image is displayed on the liquid crystal panel. The method of claim 7, wherein The signal selecting means includes first signal selecting means for alternately supplying red data and green data first by the control signal when the liquid crystal panel is driven; And second signal selecting means for supplying blue data at predetermined intervals. The method of claim 7, wherein The control signal generating means includes first control signal generating means for applying a control signal for supplying the green data at predetermined intervals by using the dot clock; And second control signal generation means for applying a control signal to the signal selection means and the first control signal generation means by using the horizontal synchronization signal.