JP2001296829A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a planar display device capable of obtaining satisfactory and high picture quality by improving display unevenness by positions of a screen even in display devices of a large-sized display, a high definition display and a multi-level display in which signal lines are wired in a comb shape. SOLUTION: This display device is provided with a display position detecting circuit 72 detecting a horizontal display position and a vertical display position in a liquid crystal panel based on a control signal, a data adjusting circuit 74 correcting a picture signal so that the picture signal equivalent to a voltage drop by the impedance of the signal line based on these position detection signals and is provided with a data timing control circuit 78 and a selector circuit 52 which controls horizontal timing and vertical timing and, also, outputs the picture signal to an upper side source driver 24 and a lower side source driver 26 by changing the arrangement of the picture signal so as to display the corrected picture signal on the liquid crystal panel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an active matrix type liquid crystal or organic EL using a thin film transistor (hereinafter referred to as a TFT) as a switching element in each pixel.
And the like.

[0002]

2. Description of the Related Art A flat display device represented by a liquid crystal display device has been used in various fields by utilizing its features of thinness, light weight and low power consumption. In recent years, such flat display devices have been particularly enlarged,
The demand for higher definition is increasing.

In general, it is known that when a DC voltage is applied for a long period of time, display defects such as image sticking or deterioration of characteristics occur in a liquid crystal.
In order to reduce flicker, for example, a method is adopted in which an AC voltage is applied to each pixel every frame period.

In an active matrix type liquid crystal display device, a signal voltage and a polarity of a common electrode are inverted for each horizontal scan (H line common inversion), or a direct current is applied to the common electrode, and a signal line is applied to the adjacent horizontal lines. A method of inverting the polarity every time (dot inversion) is adopted.

[0005] When performing the above-described high definition,
Since it is necessary to narrow the bit width beyond the number of signal lines and the mounting limit of the source driver IC, it is difficult to arrange the source driver IC on one side of the array substrate of the display panel, and it is necessary to arrange the source driver IC from both sides. .

At this time, the signal lines on the array substrate are
As shown in (1), the pitch is reduced during mounting by comb-shaped wiring.

[0007]

By the way, as shown in FIG. 19, as the potential of the signal line becomes farther from the source driver IC, a voltage drop occurs due to the impedance of the signal line itself, and a predetermined pixel voltage is reduced. Voltage cannot be achieved.
In particular, as the screen becomes larger as described above, the voltage loss increases.

This voltage loss is usually caused by the source driver I
When C is arranged on only one side of the display panel and driven,
The visibility is low because the voltage gradually drops. However, FIG.
As shown in FIG. 9, when the source driver IC is connected to the interdigital wiring arranged on both sides of the array substrate, there are the following problems.

That is, in the upper pixel of the screen, the distance between the upper source driver IC and the pixel is short, but the distance between the lower source driver IC and the pixel is long. Since these signal lines are adjacent to each other, display unevenness occurs due to a difference in pixel voltage due to a voltage drop of the signal line. In particular, when a halftone or the like is displayed, the display unevenness is noticeably recognized. There is also a similar problem at the bottom of the screen.

In view of the above-mentioned problems, the present invention improves display unevenness due to screen position without requiring a cost increase due to a complicated circuit configuration even in a large-screen, high-definition, multi-tone display panel. To provide a flat display device capable of obtaining good high image quality.

[0011]

According to the present invention, there are provided a plurality of signal lines and scanning lines which are arranged orthogonally to each other, and a pixel which is arranged in the vicinity of an intersection between the signal lines and the scanning lines via a switching element. A display panel including an array substrate having electrodes, a first signal line driving circuit connected to the signal lines of a first predetermined number and outputting a corresponding analog image signal, and a second signal circuit of a second predetermined number. A second signal line drive circuit connected to the signal line and outputting a corresponding analog image signal;
The predetermined number of signal lines are electrically connected to the first signal line driving circuit at one end of the array substrate, and the second predetermined number of signal lines are opposite to the one end of the array substrate. A position detection circuit electrically connected to the second signal line driving circuit on an end side and detecting a horizontal display position and a vertical display position on the display panel based on a control signal input from the outside; A data correction circuit for correcting an image signal so that a voltage drop due to the impedance of the signal line is corrected based on a position detection signal from the circuit; and displaying the corrected image signal from the data correction circuit on the display. In order to display on the panel, the horizontal timing and the vertical timing are controlled, and the arrangement of the image signals is changed and output to the first signal line driving circuit and the second signal line driving circuit. Is a flat display device, characterized in that a that the data sequence operation circuit.

Further, the present invention comprises a plurality of signal lines and scanning lines which are arranged orthogonally to each other, and a pixel electrode which is arranged via a switch element near an intersection of the signal line and the scanning line. A display panel including an array substrate, a first signal line driving circuit connected to the first predetermined number of signal lines and outputting a corresponding analog image signal, and a digital image signal. A second signal line driving circuit connected to the signal lines for every second predetermined number and outputting a corresponding analog image signal is provided, wherein the signal lines for every first predetermined number are connected to the array substrate One end of the array substrate is electrically connected to the first signal line drive circuit, and the second predetermined number of signal lines are connected to the second signal line drive circuit at the other end opposite to the one end of the array substrate. Electrically connected and outside A position detection circuit that detects a horizontal display position and a vertical display position on the display panel based on a control signal input from the control panel, and the first signal line driving circuit and the first signal line drive circuit based on a position detection signal from the position detection circuit. A flat display device, further comprising a reference value correction circuit for changing a reference value for digital-to-analog conversion of a digital image signal into an analog image signal in the second signal line drive circuit.

Thus, even in a large-screen, high-definition, multi-gradation display panel in which signal lines are interdigitated, display unevenness due to the screen position can be improved without increasing the cost due to a complicated circuit configuration. And good high image quality can be obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device 10 according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a schematic configuration of a liquid crystal display device 10 according to the present embodiment.

The liquid crystal display device 10 has a QUXGA (3200 × 2400) having an effective display area of 20.8 inches diagonally.
The liquid crystal panel 12 having the color display pixels of the specifications is provided. That is, the effective display area of the liquid crystal display device 10 is:
24 horizontal pixel lines consisting of 3200 × 3 (R, G, B) display pixels
It is provided with 00 pieces.

Since the liquid crystal display device 10 has such a large number of horizontal pixel lines L1,..., L2400, it employs the following characteristic driving.

That is, as shown in FIGS. 6 and 7, the effective display area is divided into upper and lower parts, and during one horizontal scanning period (1H), the horizontal pixel lines (L1 to L1200) in the upper display area and the horizontal In this method, writing is performed on each of the pixel lines (L1201 to L2400), and this is sequentially repeated. For example, in this embodiment, the horizontal pixel lines L1 and L2400 in the first horizontal scanning period (1H) and the second horizontal scanning period (1H)
, L2399, L2,... Are sequentially written.

Here, the horizontal scanning period (1H) is a period during which digital image data DATA for one horizontal pixel line is transmitted from the processing unit 32, and in this embodiment, 13 μs.
c.

It is assumed that the effective display area of the liquid crystal panel 12 is composed of four UXGA (1600 × 1200) areas divided into upper, lower, left and right as shown in FIG. Screen A, upper right screen B screen,
The lower left screen is a C screen, and the lower right screen is a D screen. In addition, when "upper screen" is described, A screen, or
Screen B means "screen C" or screen D when "lower screen" is described. Furthermore, A screen, B screen, C screen
It is assumed that the screen and the D screen are respectively composed of an A1 screen and an A2 screen, a B1 screen and a B2 screen, a C1 screen and a C2 screen, and a D1 screen and a D2 screen divided into right and left.

[Configuration of Liquid Crystal Panel] In order to realize the above-mentioned driving, the liquid crystal display device 10 is configured as follows.

That is, as shown in FIG. 1, the liquid crystal panel 12 has (3200 × 3 (R, G, B)) signal lines 16 and 2400 signal lines 16 arranged orthogonally to the signal lines 16. An array substrate 14 including a scanning line 18, a pixel electrode 22 disposed via a TFT 20 disposed near an intersection of each of the signal line 16 and the scanning line 18, and a predetermined position above an opposing surface of the array substrate 14. A counter substrate (not shown) provided with a color filter and a counter electrode arranged with a gap of
4 and a liquid crystal (not shown) as a light modulation layer disposed between the counter substrate 4 and the counter substrate.

If an organic EL panel is used instead of the liquid crystal panel, it is necessary to arrange an organic EL layer or the like instead of the liquid crystal.

Each of the scanning lines 18 is connected to the gate of the TFT 20, each of the signal lines 16 is connected to the drain of the TFT 20, each of the pixel electrodes 22 is connected to the source of the TFT 20,
Are electrically connected to each other so that the scanning line 1
An analog image signal Vs from the signal line 16 is written to the pixel electrode 22 in accordance with the scanning pulse Vg supplied to the pixel 8, and display is performed based on a potential difference between the pixel electrode 22 and the counter electrode.

The signal line 1 of the liquid crystal panel 12
As shown in FIG. 1, reference numeral 6 denotes an upper extraction signal line 16a electrically extracted from the upper side of the array substrate 14, and a lower extraction signal line 16 electrically extracted from the lower side of the array substrate 14.
b, and these signal lines 16a and 16b are alternately arranged as shown in FIG. In other words, the odd-numbered signal lines 16 are upper extraction signal lines 16a, and the even-numbered signal lines 16 are lower extraction signal lines 16b.

Of the odd-numbered signal lines 16a arranged on the AC screen, the upper lead-out signal lines 16a of R1, B1,..., G800 are for the first AC screen arranged on the upper side of the liquid crystal panel 12. R8 to upper source driver 24-ACU1
, G1600, the upper lead-out signal line 16a is electrically connected to the second AC screen upper source driver 24-ACU2 via the connection pad 17a.
Further, among the even-numbered signal lines 16b arranged on the AC screen, G1, R2,.
b indicates to the lower source driver 26-ACD1 for the second AC screen arranged on the lower side of the liquid crystal panel 12 that G801, R802,.
.., lower lead-out signal line 16b of B1600 is connected to lower source driver 26-ACD2 for the second AC screen by connection pad 1 respectively.
7b are electrically connected.

Similarly, among the odd-numbered signal lines 16a arranged on the BD screen, R1601, B1601,.
The upper lead-out signal line 16a is connected to the upper source driver 25-BDU1 for the first BD screen disposed on the upper side of the liquid crystal panel 12.
, R2401, B2401, ..., G3200 upper lead-out signal line 1
6a is the upper source driver for the second BD screen 25-BDU2
Are electrically connected via connection pads 17a. Further, among the even-numbered signal lines 16b arranged on the BD screen, the lower extraction signal line 16b of G1601, R1602,..., B2400 is the lower source for the second BD screen arranged on the lower side of the liquid crystal panel 12. Driver 27-BDD1, G2
, B3200, the lower extraction signal line 16b is electrically connected to the lower source driver 27-BDD2 for the second BD screen via the connection pad 17b.

The scanning line 18 is drawn out to one end of the array substrate 14 and is electrically connected to an upper screen gate driver 28 and a lower screen gate driver 30 via a connection pad 19. , A scanning pulse Vg is supplied to each scanning line 18.

With such a configuration of the liquid crystal panel 12,
Since each of the connection pads 17a and 17b of each signal line 16 is arranged at least with the signal line 16 therebetween, the interval between the connection pads 17a and 17b can be made sufficiently large with respect to the interval between the signal lines 16. Thus, the upper source drivers 24 and 25 and the lower source driver 2 can be used for higher definition.
Electrical connections of external circuits such as 6, 27 can be easily made.

[Circuit Configuration of Liquid Crystal Display] As described above (see FIG. 1), the liquid crystal display 10 has a liquid crystal panel 12 and a signal for supplying an analog image signal Vs to the signal line 16 of the liquid crystal panel 12. Upper source drivers 24 and 25 as line drive circuits, lower source drivers 26 and 27
And a scanning pulse V is applied to each scanning line 18 of the liquid crystal panel 12.
An upper screen gate driver 28 and a lower screen gate driver 30 as a scanning line driving circuit for supplying g, and a source driver 24, 25, 26, 27, and a liquid crystal controller 34 for controlling the gate drivers 28, 30 Have.

The circuit configuration of the liquid crystal display device 10 will be described in more detail with reference to FIG.

The processing device 32 corresponds to each of the A screen, the B screen, the C screen, and the D screen of the liquid crystal panel 12, and further, for each color of red (R), blue (B), and green (G), 24 sets of digital image data R: DATA-A (o), R: D corresponding to odd and even numbers in the horizontal pixel line direction
ATA-A (e), ..., R: DATA-B (o),
R: DATA-B (e), ..., R: DATA-C
(O), R: DATA-C (e), ..., R: DAT
AD (o), R: DATA-D (e), ..., B:
DATA-D (e) (see FIGS. 11 to 13) is output to the liquid crystal controller 34 in parallel.

Each digital image data DATA
Is constituted by 8 bits in this embodiment, whereby the liquid crystal display device 10 can realize 256 gradation display.

Here, the processing device 32 and the liquid crystal display device 10
The data transfer at 60 MHz is realized by dividing data into odd numbers (o) and even numbers (e) for each of the divided display screens and further performing the data transfer in parallel. This suppresses an increase in the data transfer speed, thereby making it possible to reliably transfer data and reduce the influence of EMI.

The processing device 32 is shown in FIGS.
As shown in FIG. 3, the liquid crystal display device 10 includes the horizontal synchronization signals HSYNC and HSYNC together with the digital image data DATA.
Vertical synchronization signal VSYNC, data enable signal ENA
B, transmitting the system clock signal NCLK.

The I / F connector 36 constituting the liquid crystal controller 34 has 24 input digital image data R: DATA-A (o),..., B: DATA-
D (e), 12 systems of digital image data R: DATA-A (o), R: D for constituting an AC screen
ATA-A (e), ..., B: DATA-A (e),
R: DATA-C (o), R: DATA-C (e),
.., B: DATA-C (e) is supplied to the AC screen liquid crystal controller 38, and the other 12 digital image data R: DATA-B (o), R: DAT constituting the BD screen
AB (e), ..., B: DATA-B (e), R:
DATA-D (o), R: DATA-D (e), ...
.., B: Distribute DATA-D (e) to the liquid crystal controller 40 for BD screen.

Each of the liquid crystal controllers 38 and 40 is an IC chip having the same configuration that can control the source drivers 24, 25, 26 and 27 and the gate drivers 28 and 30.

Then, the AC screen liquid crystal controller 38
Is the first and second upper source drivers 24-A for the AC screen
It is wired so as to control the CU1, 24-ACU2 and the first and second lower source drivers 26-ACD1, 26-ACD2 for the AC screen and the gate driver 28 for the upper screen. Further, the BD screen liquid crystal controller 40 includes first and second upper source drivers 25-BDU1 and 25-BDU2 for BD screen and first and second lower source drivers 27-BDD1 for BD screen,
It is wired to control the 27-BDD2 and to control the lower screen gate driver 30.

The AC screen liquid crystal controller 38 includes a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, a data enable signal ENAB,
Based on the system clock signal NCLK, control signals such as a vertical start signal STV-U, a vertical clock signal CPV-U, and a gate output enable signal OE-U are generated and transmitted to the upper screen gate driver 28.

Similarly, the BD screen liquid crystal controller 40
The vertical start signal STV-D and the vertical clock signal C
PV-D and a gate output enable signal OE-D are transmitted to the lower screen gate driver 30.

The AC screen liquid crystal controller 38
Is the input 12-system digital image data R: D
ATA-A (o), R: DATA-A (e), ...,
B: DATA-A (e), R: DATA-C (o),
R: DATA-C (e), ..., B: DATA-C
(E) is rearranged and the timing is controlled, and the rearranged twelve systems of digital image data R: UD
ATA-A1C1, G: UDATA-A1C1, B: U
DATA-A1C1, R: DDATA-A1C1, G:
DDATA-A1C1, B: DDATA-A1C1,
R: UDATA-A2C2, G: UDATA-A2C
2, B: UDATA-A2C2, R: DDATA-A2
C2, G: DDATA-A2 C2, B: DDATA-A
2C2 is a horizontal clock signal CPH and a horizontal start signal H
Together with START, the first and second upper source drivers 24 via a low voltage differential signal transmitting circuit 42, a low voltage differential signal receiving circuit 44, and a serial / parallel controller (hereinafter referred to as "S / P controller") 46. -ACU1,
24-ACU2 and first and second lower source drivers 26-AC
D1 and 26-ACD2 are output in parallel.

Further, a correction circuit 70 for correcting a voltage drop caused by the impedance of the signal line is provided.
The correction circuit 70 will be described later in detail.

The BD screen liquid crystal controller 40 performs substantially the same processing, and a description thereof will be omitted.

In FIG. 3, a range surrounded by a dotted line indicates a wiring board used in the liquid crystal display device 10, and each circuit is mounted on the wiring board shown by the dotted line. Is shown.

In this embodiment, the S / P controller 46 comprises first and second upper source drivers 24-ACU1, 24-AC
U2, 25-BDU1, 25-BDU2, and first and second lower source drivers 26-ACD1, 26-ACD2, 27-BDD1, 27-BD
Since D2 enables two-port input, control is performed to extend the time axis of the rearranged twelve systems of digital image data and to lead two lines to each driver in parallel.

[Configuration of AC Screen Circuit] FIG. 4 is a block diagram of an AC screen circuit among the circuits of the liquid crystal display device 10 shown in FIG. 3, and will be described in further detail.
Note that a similar circuit is configured for the BD screen circuit, and a description thereof will be omitted.

As shown in FIG. 4, the liquid crystal controller 38 for the AC screen, which constitutes the liquid crystal controller 34 of the liquid crystal display device 10, receives the A
Screens and 12 screens of digital image data R corresponding to odd-numbered and even-numbered colors corresponding to screens C and R:
DATA-A (o), R: DATA-A (e), ...
·, B: DATA-C (o), and B: DATA-C
(E) is input in parallel.

The AC screen liquid crystal controller 38 includes an upper screen line memory 48 corresponding to red (R), blue (B) and green (G), and a lower screen line memory 50, respectively. 48 and 50 are connected to one selector circuit 52.

The timing control and the rearrangement of data are achieved by writing and reading to and from the line memories 48 and 50 and setting the output destination by the selector circuit 52.

Next, the correction circuit 70 will be described.

The correction circuit 70 includes a display position detection circuit 7
2, a data addition / subtraction circuit 74, a data correction reference table (hereinafter, referred to as a table) 76, a data timing control circuit 78, and line memories 48 and 50;
A timing control circuit 68 is provided to synchronize with the selector circuit 52.

The correction circuit 70 determines in advance the signal lines 1 in the horizontal and vertical directions of the pixel positions on the array substrate 14.
6, the voltage drop due to the impedance is corrected, and the relationship between the pixel position and the correction amount is prepared in the table 76. The amount of correction is determined based on the table 76 from the position in the vertical direction according to the control signal, and the input image data is corrected.

That is, the horizontal synchronizing signal HSYNC and the vertical synchronizing signal V sent through the timing control circuit 68
The display position detection circuit 72 detects the horizontal position and the vertical position of the pixel data DATA sent from the selector circuit 52 based on the SYNC and the data enable signal ENAB. Based on the vertical position data, the correction amount is read from the table 76, and the data adjusting circuit 74
The correction amount is added to the pixel data DATA sent from Step 2. Then, the corrected pixel data DATA is timed by the data timing control circuit 78 and sent back to the selector circuit 52.

Hereinafter, for simplification of the concrete example, 3 bits (8
This will be described with reference to FIG.

As shown in FIG. 17, the positions on the screen (1,
1) and (1, 2) are adjacent in the horizontal direction and at the same position in the vertical direction.

Now, the entire screen is displayed as 4 of the display data (100).
If it is a raster display of gradation and the pixel voltage is set to V / 2 at this time, the two pixels are (1,
In (1), the voltage actually applied to the pixel is V / 2, but (1,
The voltage in 2) is, for example, due to the voltage drop due to the signal line,
3V / 8, which is exactly (011) as data,
That is, a state where a voltage lower by one gradation is applied.

Therefore, in the correction circuit 70, when the pixel data on the first line of the even-numbered column is shifted one gradation higher, the voltages actually applied to the pixels (1, 1) and (1, 2) are set to the same potential. Can be. In this case, in the table 76, data for shifting the pixel data to the upper side by one gradation is stored in the first line of the even-numbered column.

Conversely, even if the data in the odd-numbered columns is shifted down by one gradation, the actual voltages to the pixels can be made equal. These corrections may be based on correction amounts that are different for each gradation. In addition, black with low visual sensitivity (normally white liquid crystal,
(111)) and white (000), for example, this correction may not be performed.

By incorporating the correction circuit 70 in the liquid crystal controller 38 in this way, the apparent circuit configuration is not particularly complicated, and the number of components can be made equal to that of the conventional one.

In a large-screen, high-definition, multi-tone display liquid crystal panel of a digital input signal, display unevenness due to the screen position can be improved without necessitating an increase in cost due to a complicated circuit configuration, and good high image quality can be obtained. can get.

[Driving Method of Liquid Crystal Display Device] Hereinafter, a more detailed description will be given with reference to the drawings.

FIG. 12 shows the data input / output timing of the liquid crystal controller 34. The system clock signal NCLK, the horizontal synchronizing signal HSYNC, the data enable signal ENAB, and the digital image data R: DATA input from the processing unit 32 from above are shown. -A (o), R: DAT
A-A (e), ..., R: DATA-C (o), R:
, And a clock signal CL generated by the AC screen liquid crystal controller 38.
K, a horizontal start signal HSTART, and output image data U output from the AC screen liquid crystal controller 38.
DATA-A1C1, DDATA-A1C1, UDATA-A2C2,
UDATA-A2C2 is shown. 13 and FIG.
4 shows output image data UDATA-A1C1, DDATA-A1C1.
The enlarged view of FIG.

[1] From the processing device 32 to the liquid crystal display device 1
The 8-bit digital image data DATA, which is input in parallel to the 0 system in 24 systems, is distributed to the AC screen liquid crystal controller 38 and the BD screen liquid crystal controller 40 by the I / F connector 36. As described above, the digital image data DATA distributed in parallel to the AC screen liquid crystal controller 38 includes red (R), blue (B),
For each color of green (G), for screen A and screen C,
A total of 12 systems of 8-bit digital image data R: D
ATA-A (o), R: DATA-A (e), ...,
B: DATA-A (e), R: DATA-C (o),
R: DATA-C (e), ..., B: DATA-C
(E), and hereinafter, the AC screen liquid crystal controller 38
The operation will be described by taking the operation of FIG.

[2] AC Screen LCD Controller 38
Screen A digital image data R: DATA-A corresponding to the horizontal pixel line L1 distributed in parallel to
(O), R: DATA-A (e), G: DATA-A
(O), G: DATA-A (e), B: DATA-A
(O), B: DATA-A (e) is the line memory 48
The digital image data for the C screen corresponding to the horizontal pixel line L2400 R: DATA-C (o), R: DATA-
C (e), G: DATA-C (o), G: DATA-C
(E), B: DATA-C (o), B: DATA-C
(E) is sequentially stored in the line memory 50 based on the system clock signal NCLK.

[3] Thus, the line memory 4
The digital image data DATA corresponding to the horizontal pixel lines L1 and L2400 stored in the clock signal CL having the same frequency as the system clock signal NCLK.
The data is sequentially read out based on K and temporarily stored in the selector circuit 52.

The image data DATA stored in the selector circuit 52 is read out to the data adjusting circuit 74 based on the system clock signal NCLK by the timing control circuit 68.

As described above, the timing control circuit 68
The horizontal position and vertical position of the pixel data DATA sent from the selector circuit 52 are detected by the display position detecting circuit 72 based on the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC and the data enable signal ENAB sent through I do. Based on the vertical position data, the correction amount h corresponding to the position is read from the table 76, and the data adjusting circuit 74 adds the correction amount h to the pixel data DATA sent from the selector circuit 52. That is, the correction amount h is set to the gradation K of the pixel data DATA (in the case of 256 gradations,
K is an integer value from 0 to 255). For example, the gradation of the corrected pixel data DATA is K
+ H or Kh.

Then, the pixel data DAT whose gradation has been corrected
A is sent back to the selector circuit 52 by the data timing control circuit 78 based on the clock signal CLK having the same frequency as the system clock signal NCLK.

[4] The corrected pixel data DATA sent back from the data timing control circuit 78 is rearranged by the selector circuit 52.

More specifically, A-screen digital image data R: DATA-A corresponding to the horizontal pixel line L1
(O), G: DATA-A (o), B: DATA-A
(O) R1 to R799, R: DATA-A (e), G:
DATA-A (e), B: R2 of DATA-A (e)
When up to R800 are stored in the line memory 48, reading is sequentially started based on the clock signal CLK,
The image data is rearranged by the selector circuit 52.

For example, in the AC screen first upper source driver 24-ACU1, three parallel image data UDATA-A1C1 rearranged as shown in FIG. 13 are stored in the AC screen first lower source driver 24-ACU1. ACU1 has three parallel input image data UDAT rearranged as shown in FIG.
A-A1C1 is output, respectively.

Further, C corresponding to the horizontal pixel line L2400
Digital image data R for screen: DATA-C
(O), G: DATA-C (o), B: DATA-C
(O) R1 to R799, R: DATA-C (e), G:
DATA-C (e) and B: DATA-C (e) are stored in the line memory 50 and output of image data corresponding to the screen A is completed as shown in FIG.
Reading is sequentially started based on the clock signal CLK, and is temporarily stored in the selector circuit 52.

The stored image data is subjected to gradation correction by the correction circuit 70 and is returned to the selector circuit 52 again.

Then, the selector 52 sorts the image data.

[5] The first and second upper source drivers 24-ACU1 and 24-ACU2 for the AC screen and the first and second lower source drivers 24-ACD1 and 24-ACD2 for the AC screen are input horizontal pixels, respectively. A-screen image data UDATA-A1C1, DDATA-A1C1, UDA corresponding to line L1
TA-A2C2 and DDATA-A2C2 are subjected to serial-parallel conversion, and digital-to-analog conversion is performed.
/ 2) to output a desired analog image signal Vs to the corresponding signal line 16.

In this case, since the gradation of the image data UDATA and DDATA is corrected in the correction circuit 70, the voltage value of the analog image signal Vs is also corrected corresponding to the display position, and the adjacent upper source driver 24 There is no difference in pixel voltage between the upper lead-out signal line 16 connected to the lower line and the lower lead-out signal line 16 connected to the lower source driver 26, and display unevenness caused by the impedance of the signal line 16 is suppressed. Can be.

Subsequently, image data UDATA for screen C corresponding to the input horizontal pixel line L2400
-A1C1, DDATA-A1C1, UDATA-A2C2, DDAT
A-A2C2 is subjected to serial-parallel conversion and further digital-to-analog conversion, and outputs a desired analog image signal Vs to the corresponding signal line 16 over a 1/2 horizontal scanning period (H / 2).

Thus, one horizontal scanning period (1H)
Then, writing to two horizontal pixel lines (L1, L2400) is performed.

[6] In the next horizontal scanning period, C-screen digital image data R: DATA-C (o) and R: DATA corresponding to the horizontal pixel line L2399 distributed in parallel to the AC-screen liquid crystal controller 38. -C (e),
G: DATA-C (o), G: DATA-C (e),
B: DATA-C (o) and B: DATA-C (e) are stored in the line memory 48 in the A-screen digital image data R: DATA-A (o) corresponding to the horizontal pixel line L2.
R: DATA-A (e), G: DATA-A (o),
G: DATA-A (e), B: DATA-A (o),
B: DATA-A (e) is sequentially stored in the line memory 50 based on the system clock signal NCLK.

[7] In this way, the line memory 4
The digital image data DATA corresponding to the horizontal pixel lines L2399 and L2 stored in the clock signals CL2 and CL50 have the same frequency as the system clock signal NCLK.
The image data is sequentially read out based on K, and the image data is rearranged by the selector circuit 52 via the correction circuit 70.

More specifically, digital image data R for the C screen corresponding to the horizontal pixel line L2399 R: DATA-C
(O), G: DATA-C (o), B: DATA-C
(O) R1 to R799, R: DATA-C (e), G:
DATA-C (e), B: R2 of DATA-C (e)
When up to R800 are stored in the line memory 48, reading is sequentially started based on the clock signal CLK,
The data is temporarily stored in the selector circuit 52.

The stored image data is subjected to gradation correction by the correction circuit 70 and is returned to the selector circuit 52 again.

Then, the selector circuit 52 rearranges the image data.

Further, the digital image data R for the A screen corresponding to the horizontal pixel line L2: DATA-A (o),
G: DATA-A (o), B: R of DATA-A (o)
1 to R799, R: DATA-A (e), G: DATA-
A (e), B: For DATA-A (e), FIG.
As shown in (1), after the output of the image data corresponding to the screen C is completed in the line memory 50, the reading is sequentially started based on the clock signal CLK, and is temporarily stored in the selector circuit 52.

The stored image data is subjected to gradation correction by the correction circuit 70 and returned to the selector circuit 52 again.

Then, the selector 52 sorts the image data.

[8] The first and second upper source drivers 24-ACU1 and 24-ACU2 for the AC screen and the first and second lower source drivers 24-ACD1 and 24-ACD2 for the AC screen are input horizontal pixels, respectively. Image data UDATA-A1C1, DDATA-A1C1, UD for C screen corresponding to line L2399
The ATA-A2C2 and the DDATA-A2C2 are serial-parallel-converted, and the digital-to-analog conversion is performed, and the desired corrected analog image signal Vs is output to the corresponding signal line 16 over a half horizontal scanning period (H / 2). I do.

Subsequently, the image data UDATA-A for the A screen corresponding to the input horizontal pixel line L2, respectively.
1C1, DDATA-A1C1, UDATA-A2C2, DDATA-
A2C2 is subjected to serial-to-parallel conversion, and further digital-to-analog conversion, and outputs a desired corrected analog image signal Vs to the corresponding signal line 16 over a half horizontal scanning period (H / 2).

Thus, one horizontal scanning period (1H)
Then, writing to two horizontal pixel lines (L2399, L2) is performed.

Thereafter, this operation is sequentially repeated.

[Writing Method] Next, based on FIG.
An analog image signal Vs is applied to each pixel electrode in this embodiment.
Will be described.

As described above, in this embodiment, the effective display area is divided into upper and lower parts (AB screen and CD screen), and driving for writing to the horizontal pixel lines in each area within each horizontal scanning period (1H) is performed. Has adopted.

For this reason, it is necessary to consider driving so that the boundary between the upper and lower divisions is not visually recognized.

Further, if a direct current component is applied to the liquid crystal for a long time, the liquid crystal is deteriorated. Therefore, it is necessary to invert the polarity of the voltage applied to the liquid crystal every predetermined period.

For this reason, for example, a method of inverting the polarity of the voltage applied to the pixel electrode for each field (F) with respect to the reference voltage, and a method of inverting the polarity for each horizontal pixel line (H line inversion driving) Further, a method of inverting the polarity for each display pixel (HV inversion driving) and the like are known.
In order to reduce flicker, HV inversion driving is effective.

Therefore, in this embodiment, HV inversion driving may be adopted. However, in order to control the alternately arranged upper extraction signal lines 16a and lower extraction signal lines 16b by different source drivers, As shown in FIGS. 6 and 7, the H2V inversion drive (every horizontal pixel line, every two vertical pixel lines) is employed.

In this embodiment, the polarity of the analog image signal Vs is inverted for each horizontal pixel line. However, by reducing the polarity inversion cycle of the analog image signal Vs itself,
A method of securing a sufficient write time and achieving low power consumption is employed.

That is, an analog image signal Vs including signals for the upper screen (AB screen) and the lower screen (CD screen) is output to each signal line 16 within one horizontal scanning period (H), and each horizontal scanning is performed. Writing is performed on the corresponding horizontal pixel lines in the first half and the second half of the period (H), and the polarity inversion cycle is the horizontal scanning period (H).

More specifically, as shown in FIG. 6, during the first half of one horizontal scanning period (H), the positive analog image signal Vs
Is written to the pixel electrode connected to the signal line R1 of the horizontal pixel line L1, and in the latter half, the analog image signal Vs of positive polarity is written to the pixel electrode connected to the signal line R1 of the horizontal pixel line L2400. In the first half of the next horizontal scanning period (H), the negative analog image signal Vs is applied to the pixel electrode connected to the signal line R1 of the horizontal pixel line L2399 in the first half, and the negative analog image signal Vs is applied to the horizontal pixel line L2 signal in the second half. Writing is performed on the pixel electrode connected to the line R1.

With such an operation, although the polarity is inverted for each horizontal pixel line, the inversion cycle can be set as the horizontal scanning period.

[Writing State] By the way, in the above-described driving, there are four kinds of states as shown in FIG.

First, the four states will be described.

[1] Positive polarity pre-write state (P1) With respect to the analog image signal Vs on the positive polarity side with respect to the reference voltage, the analog image signal Vs supplied in the first half is determined based on the corresponding scan pulse Vg. State to write to pixel electrode in period.

[2] Post-Positive Polarity Write State (P2) With respect to the analog image signal Vs on the positive polarity side with respect to the reference voltage, the analog image signal Vs supplied in the latter half is converted to the analog signal Vs based on the corresponding scan pulse Vg. State to write to pixel electrode in period.

[3] Negative Polarity Pre-Write State (N1) With respect to the analog image signal Vs on the negative polarity side with respect to the reference voltage, the analog image signal Vs supplied in the first half is changed based on the corresponding scan pulse Vg. State to write to pixel electrode in period.

[4] Negative polarity post-write state (N2) With respect to the analog image signal Vs on the negative polarity side with respect to the reference voltage, the analog image signal Vs supplied in the latter half is determined based on the corresponding scan pulse Vg. State to write to pixel electrode in period.

These four states have different writing states, and thus cause display defects. Specifically, even when the same image is displayed, writing is more disadvantageous in the positive polarity pre-writing state (P1) than in the positive polarity post-writing state (P2). Similarly, the negative polarity pre-write state (N
In the case of 1), writing is disadvantageous compared to the writing state after negative polarity (N2). In particular, such a phenomenon becomes remarkable under a severe writing condition, for example, a low temperature condition.

Also, for example, a positive polarity pre-write state (P1) and a negative polarity pre-write state (N1), or a positive polarity post-write state (P2) and a negative polarity post-write state (N2) It is not possible to realize completely the same display quality due to the difference in polarity.

As described above, the liquid crystal display device 1 of this embodiment
In the case of 0, it is desired to prevent the boundary of the upper and lower divisions from being visually recognized during driving, further suppress the occurrence of flicker and display unevenness, and secure good display quality.

Further, since the gradation of the image data UDATA and DDATA is corrected in the correction circuit 70, the voltage value of the analog image signal Vs is also corrected in accordance with the display position, and is connected to the adjacent upper source driver 24. There is no difference in the pixel voltage between the signal line 16 and the signal line 16 connected to the lower source driver 26, and display unevenness due to the impedance of the signal line 16 can be suppressed.

[Scanning Method] Therefore, in this embodiment, FIG.
And the operation shown in FIG. FIG. 6 shows a screen of n fields, and FIG. 7 shows a screen of n + 1 fields.

The scanning method is such that the upper screen (AB screen) scans from top to bottom, that is, sequentially scans from the horizontal pixel line L1 to the horizontal pixel line L1200, and the lower screen (CD screen) moves from bottom to top. Scanning, that is, sequential scanning in the reverse direction from the horizontal pixel line L2400 to the horizontal pixel line L1201.

The writing method for the pixel electrode is performed by using the signal line R1.
For example, in the n-th field, in the first half of one horizontal scanning period (H), the corresponding pixel electrode of the horizontal pixel line L1 is set to the positive pre-write state (P1), and in the second half, the corresponding pixel electrode of the horizontal pixel line L2400 is set. The pixel electrode to be written is in a positive write state (P
2). In the first half of the next horizontal scanning period, the corresponding pixel electrode of the horizontal pixel line L2399 is set in the negative pre-write state (N
1), and in the latter half, the corresponding pixel electrode of the horizontal pixel line L2 is set to the negative post-write state (N2). Thereafter, the processing is sequentially repeated. In the (n + 1) th field, the corresponding pixel electrode of the horizontal pixel line L1 is set to the negative pre-write state (N1) in the first half of one horizontal scanning period, and the corresponding pixel electrode of the horizontal pixel line L2400 is set to the negative pre-write state in the second half. Write state (N2)
And In the first half of the next horizontal scanning period, the horizontal pixel line L23
The corresponding pixel electrode 99 is set to a positive polarity pre-writing state (P1), and the corresponding pixel electrode of the horizontal pixel line L2 is set to a positive polarity post-writing state (P2) in the latter half. Thereafter, the processing is sequentially repeated.

The above-mentioned problem can be solved by controlling the scanning method and the polarity of the analog image signal Vs.

That is, by scanning the upper screen (AB screen) from top to bottom and the lower screen (CD screen) from bottom to top, the horizontal pixel line L near the division boundary is scanned.
The timing of writing to 1200 and L1201 becomes close in time, and the drop in pixel potential during the holding period becomes substantially equal between adjacent horizontal pixel lines, so that the boundary is prevented from being visually recognized. As another method of reducing the visibility of the division boundary, for example, the upper screen (AB screen) is scanned from the bottom to the top, and the lower screen (CD screen) is scanned from the top to the bottom. Horizontal pixel line L near the boundary
It becomes possible to make the write timings for 1200 and L1201 close in time.

The upper screen (AB screen) and the lower screen (CD
Screen), the four states related to writing are dispersed, so that the display state is prevented from being different between the upper screen (AB screen) and the lower screen (CD screen).

The above-described control of the polarity of the analog image signal Vs is based on the polarity inversion signal POL transmitted from each of the liquid crystal controllers 38 and 40 to each of the source drivers 24, 25, 26 and 27. The driver performs digital-to-analog conversion of the input image data into a positive or negative analog image signal Vs based on the polarity inversion signal POL.

[Modification 1] The above-described embodiment shows an optimal example of the present invention. Instead of the scanning shown in FIGS. 6 and 7, for example, scanning is performed as shown in FIGS. It doesn't matter.

[Modification 2] The scanning method shown in FIGS. 15 and 16 can also be adopted. This is shown in FIGS.
In the scanning method of, the pre-writing state (P1, N1) and the post-writing state (P2, N2) are fixed, but in the scanning method shown in FIGS. 15 and 16, the pre-writing state (P1, N1). And the post-write state (P2, N2) are not fixed for each horizontal pixel line. This effectively reduces the occurrence of display unevenness in a specific display pattern such as a horizontal stripe screen.

[Modification 3] In addition to the above, the upper screen (AB
Screen), the lower screen (CD screen) can be sequentially scanned.

[Modification 4] In the above embodiment, A,
The present embodiment is realized by four screens of B, C, and D screens. However, the present embodiment is not limited to this, and the present embodiment can be applied to six or eight divisions in which three or more vertically divided screens are arranged. Further, the present embodiment can be applied to a simply divided upper and lower divided screen.

[Fifth Modification] In this embodiment, the present invention is realized in a liquid crystal display device. However, the present invention can be suitably applied to other flat display devices such as an organic EL display device instead.

[Modification 6] By the way, referring to FIG.
There are four states for writing, and the writing before the positive polarity state (P1) is disadvantageous compared to the writing state after the positive polarity (P2). It has been described that writing is more disadvantageous than writing after the negative polarity (N2).

Therefore, in addition to the method of distributing each state to the respective screen areas as described above, the disadvantageous state is reduced, for example, the positive pre-write state (P1) and / or the negative pre-write state The amplitude of the scan pulse of (N1) is changed to the positive write state (P2) and / or the negative write state (N2).
Or the width of the scanning pulse may be longer, or may be used in combination with the above method.

Further, before the positive polarity pre-writing state (P1) and / or the negative polarity pre-writing state (N1), the pre-scanning may be performed to ease the writing.

[Modification 7] In the above embodiment, the correction circuit 70 is provided in the selector circuit 52, but the following method may be used instead.

That is, the upper source drivers 24 and 25
And the lower source drivers 26 and 27 individually change the conversion reference value for digital-to-analog conversion of the digital image data into the analog image signal Vs in accordance with the display position detected by the display position detection circuit. Alternatively, the voltage drop of the impedance of the signal line 16 may be corrected.

Although the analog image signal Vs itself may be corrected, the digital processing described above is simple.

[0129]

As described above, according to the flat display device of the present invention, even a large screen, high definition, multi-gradation display panel in which signal lines are interdigitally wired does not require a cost increase due to a complicated circuit configuration. In addition, display unevenness due to the position of the screen is improved, and good high image quality is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a liquid crystal display device showing one embodiment of the present invention.

FIG. 2 is a diagram showing a divided state of an effective display area.

FIG. 3 is a block diagram illustrating a circuit configuration of a liquid crystal display device.

FIG. 4 is a block diagram for an AC screen.

FIG. 5 is a waveform diagram of an analog image signal and a scanning pulse showing a writing state to a pixel electrode.

FIG. 6 is a drawing showing a write state of an n-th field in the present embodiment.

FIG. 7 is a diagram showing a write state of an (n + 1) th field.

FIG. 8 is a diagram showing a write state of an n-th field according to a first modification.

FIG. 9 is a drawing of a screen showing a write state of an (n + 1) th field of a first modification.

FIG. 10 is a timing chart of a data interface in horizontal timing.

FIG. 11 is a timing chart of a data interface at a vertical timing.

FIG. 12 is a data input / output timing diagram of a liquid crystal controller.

FIG. 13 is an enlarged view of an upper screen data output period.

FIG. 14 is an enlarged view of a lower screen data output period.

FIG. 15 is a diagram illustrating a write state of an n-th field according to a second modification.

FIG. 16 is a drawing of a screen showing a writing state of an (n + 1) th field of a second modification.

FIG. 17 is a simplified explanatory diagram in the case where the gradation is corrected in the embodiment.

FIG. 18 is a drawing of a comb wiring when source drivers are arranged on both sides.

FIG. 19 is a drawing of a distance from a source driver and a signal line potential.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 12 Liquid crystal panel 14 Array substrate 16 Signal line 18 Scan line 20 TFT 22 Pixel electrode 24 Upper source driver for AC screen 25 Upper source driver for BD screen 26 Lower source driver for AC screen 27 Lower source for BD screen Driver 28 Upper screen gate driver 30 Lower screen gate driver 34 Control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA31 NA53 NB10 NB14 NB23 NC62 ND09 ND10 ND52 5C006 AA22 AC21 AC26 AF46 BB14 BB16 BC13 FA22 FA25 FA37 5C080 AA06 AA10 BB06 CC03 DD05 DD07 EE29 EJ01 JJ01 JJ01 JJ01 JJ01 JJ01 JJ30

Claims (4)

[Claims] 1. An array substrate comprising a plurality of signal lines and scanning lines arranged orthogonally to each other, and pixel electrodes arranged via switching elements near intersections of the signal lines and the scanning lines. A first signal line drive circuit connected to the first predetermined number of signal lines and outputting a corresponding analog image signal; a second analog signal connected to the second predetermined number of signal lines. A second signal line driving circuit for outputting an image signal, wherein the signal lines of the first predetermined number are electrically connected to the first signal line driving circuit on one end side of the array substrate; The signal lines for each number are electrically connected to the second signal line driving circuit at the other end opposite to the one end of the array substrate, and the horizontal display on the display panel is performed based on a control signal input from the outside. Position and vertical display position A data correction circuit for correcting an image signal such that a voltage drop due to the impedance of the signal line is corrected based on a position detection signal from the position detection circuit; In order to display the corrected image signal from the display panel on the display panel, the horizontal signal and the vertical signal are controlled, and the arrangement of the image signals is changed so that the first signal line driving circuit and the second signal line driving circuit are driven. A flat panel display device comprising a data array operation circuit for outputting to a circuit. 2. The data correction circuit according to claim 1, wherein the image signal increases or decreases n gradations based on a position detection signal from the position detection circuit.
A flat display device as described in the above. 3. The data correction circuit stores a correction value for correcting the voltage drop in advance in correspondence with a display position of the display panel, based on a position detection signal from the position detection circuit. 2. The flat display device according to claim 1, wherein the stored correction value is called up by using the stored correction value, and the image signal is corrected based on the called out correction value. 4. An array substrate comprising a plurality of signal lines and scanning lines arranged orthogonally to each other, and pixel electrodes arranged near switching points between the signal lines and the scanning lines via switching elements. A first signal line driving circuit connected to the first predetermined number of signal lines and outputting a corresponding analog image signal, and a digital image signal is input. And a second signal line drive circuit connected to the signal lines of a second predetermined number and outputting a corresponding analog image signal, wherein the signal lines of the first predetermined number are provided at one end of the array substrate. The second signal line driving circuit is electrically connected to the first signal line driving circuit, and the second predetermined number of signal lines are electrically connected to the second signal line driving circuit at the other end opposite to the one end of the array substrate. Input from outside A position detection circuit for detecting a horizontal display position and a vertical display position on the display panel based on the control signal, and the first signal line drive circuit and the second signal detection circuit based on a position detection signal from the position detection circuit. A flat display device, comprising: a reference value correction circuit for changing a reference value when digital-to-analog conversion of a digital image signal into an analog image signal is performed in a signal line driving circuit.