KR100956343B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention relates to a method of driving a liquid crystal display device, the method comprising: receiving 8-bit image data from an external device, and having a first gray level indicated by the upper six bits of the image data during four consecutive frames. The number of frames and the number of frames having a second gradation one step higher than the first gradation are adjusted according to the lower two bits of the image data, and the display frequency of the first gradation and the second gradation in the 4 × 2 pixel block is the lower two of the image data. And converting the frame data to be adjusted according to the bits. When the lower two bits are '10' in the frame data converting step, the same gray level is vertically adjacent to the frame data at least once in each column of the 4x2 pixel block. To convert. According to the present invention, it is possible to prevent a flicker phenomenon in which the screen flickers.

LCD, frame rate control, dithering, flicker, inversion driving, 1 dot pattern

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 shows a frame rate control scheme according to an embodiment of the present invention.

4 shows a frame rate control scheme according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a liquid crystal display and a driving method for performing frame rate control (FRC).

In recent years, with the reduction in weight and thickness of personal computers, televisions, and the like, there has been a demand for weight reduction and thickness reduction in the field of display devices, and in order to satisfy such demands, liquid crystal displays instead of cathode-ray tubes (CRTs). Flat panel displays such as liquid crystal displays (LCDs) have been developed and put into practical use in various fields.

The liquid crystal display device is representative among flat panel displays, and includes a liquid crystal panel assembly including two display panels each having two kinds of field generating electrodes, such as a pixel electrode and a common electrode, and a liquid crystal layer injected therebetween and having a dielectric anisotropy therebetween. do. When the potential difference between the two field generating electrodes changes, that is, when the intensity of the electric field generated by the two electrodes changes, the transmittance of light passing through the liquid crystal display changes, so that the desired image signal is adjusted by adjusting the potential difference between the two electrodes. Get A general liquid crystal display device is a switching element that controls a voltage applied to a pixel electrode and has a thin film transistor (TFT) and a plurality of display signal lines transferring a signal applied to the thin film transistor.

N-bit RGB data of red, green, and blue is input to the liquid crystal display from an external graphic source. After the data format is converted by the signal controller of the liquid crystal display, the analog gray voltage corresponding to the RGB data is selected by the driving IC, and the selected gray voltage is applied to the liquid crystal panel assembly. As a result, the display operation is performed.

In general, the number of bits of RGB data input from the graphic source to the signal controller is the same as the number of bits that can be processed by the driver IC. Currently, N = 8-bit products are common in liquid crystal displays on the market. However, since a driving IC capable of processing 8-bit RGB data is expensive, if the liquid crystal display device can be designed as a driving IC having a lower processing capability, the unit cost of the product may be much lowered.

According to this technical need, the proposed method is frame rate control. Frame rate control is a technique of reconstructing frame data so that display is possible using only (N-M) bits, which are the number of bits that can be processed by the driver IC among the input N-bit RGB data.

On the other hand, in the liquid crystal display, various inversion driving is performed in order to prevent deterioration of the liquid crystal and direct current stress. Examples thereof include dot inversion and line inversion. When the frame rate control is simultaneously applied in the liquid crystal display device to which the inversion driving method is applied, a flicker phenomenon occurs in which the screen flickers. In particular, this phenomenon is severe when displaying in a 1 dot pattern during 2 × 1 dot inversion driving.

Accordingly, an aspect of the present invention is to provide a liquid crystal display and a driving method thereof, which can prevent flicker, while simultaneously applying a frame rate control and an inversion driving method.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including receiving 8-bit image data from an external device, and the upper 6 bits of the image data during four consecutive frames. The number of frames having a first gray scale and the number of frames having a second gray level one step higher than the first gray scale are adjusted according to the lower two bits of the image data, and the first gray level and the And converting the frame data so that the display frequency of the second grayscale is adjusted according to the lower two bits of the image data, and when the lower two bits are '10' in the frame data converting step, the 4x2 pixel block. At least once in each column of the same gray level converts the frame data up and down adjacently.

In the frame data converting step, when the lower two bits are '10', the first gray level is added to the second and third row pixels of the first column of the 4x2 pixel block in the first frame of the four consecutive frames. The second grayscale is displayed in the second and third row pixels of the first column, and in the second frame, the first grayscale and the second grayscale are alternately displayed in the first frame, and in the third frame, the 4x2 pixel is displayed. The first gray level in the first and second row pixels of the first column of the block, the second gray level in the third and fourth row pixels, the second gray level in the first and second row pixels of the second column, and the third and fourth row of pixels. The first grayscale may be displayed, and in the fourth frame, the frame data may be converted to display the first grayscale and the second grayscale interchangeably in the third frame.

A liquid crystal display according to another exemplary embodiment of the present invention includes a liquid crystal panel assembly including a plurality of pixels, a data driver for applying a data voltage corresponding to image data to the pixels, and 8-bit image data from an external device. The number of frames having a first gray level indicated by the upper six bits of the image data and the number of frames having a second gray level one step higher than the first gray scale for four consecutive frames are adjusted according to the lower two bits of the image data. And a signal controller for converting the frame data into a 4 × 2 pixel block so that display frequencies of the first grayscale and the second grayscale are adjusted according to the lower two bits of the image data, and providing the converted data to the data driver. Frame data is the same at least once in each column of the 4x2 pixel block when the lower two bits are '10'. A gray level are converted adjacent the top or bottom.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display and a driving method thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. Is made of.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted in a tape carrier package (TCP) (not shown) to attach TCP to the liquid crystal panel assembly 300, or to integrate these onto a glass substrate without using TCP. Circuits may be directly attached (chip on glass, COG mounting method), and circuits performing the same functions as those integrated circuits may be directly mounted on the liquid crystal panel assembly 300.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) or the polarity of the data voltage applied to one pixel row may be different depending on the characteristics of the inversion signal RVS within one frame. ("Dot reversal").

In particular, the 2 × 1 dot inversion is a method of applying data voltages having the same polarity to the pixels above and below the two adjacent pixel rows, and applying data voltages having different polarities to pixels adjacent to each other in the row direction. 2x1 dot inversion is inverted in units of pixels of two adjacent gate lines positioned up and down.

Meanwhile, the 1 dot pattern refers to a display pattern in which odd-numbered pixels are turned on and even-numbered pixels are turned off, for example, when the red mode is implemented. Here, the application of the white voltage is called turn on, and the application of the black gray voltage is called turn off.

Next, the frame rate control according to the present invention will be described in detail with reference to FIGS. 3 and 4.

3 and 4 illustrate a frame rate control scheme according to an embodiment of the present invention.

As described above, the frame rate control is a technique of reconstructing frame data such that display is possible using only (NM) bits, which are the number of bits that can be processed by the driver IC, among the input N-bit RGB data. Here, M is an integer and represents the lower predetermined number of bits of the input RGB data. According to the frame rate control method, the number of frames having the gradation value 'A' indicated by the upper (NM) bit of the input RGB data and the gradation 'A + 1' immediately above the converted ^2M frames. The N-bit input data is converted into (NM) bit data so that the number of frames having? Is adjusted according to the lower M bits of RGB data. In addition, the frame rate control converts the N bit input data into a predetermined number of (NM) bit data allocated to a pixel group consisting of a predetermined number of pixels, and the number of pixels displaying grayscale 'A' for a predetermined number of frames and The number of pixels representing gradation 'A + 1' is adjusted by the lower M bits of the RGB data. Since the human eye recognizes the temporal and spatial averages of these (NM) bit data, the resulting image appears to be represented by N bits of RGB data. As a result, an additional 2 ^M gray scales can be displayed between the gray scales 'A' and 'A + 1'.

In the present embodiment, the input RGB image data is described as 8 bits, and the data that can be processed by the data driver 500 is described as 6 bits.

On the other hand, it can be represented by the average gray level of the spatially adjacent pixels with respect to the lower M bits, which is called dithering.

For example, if the lower two bits are "00", only the upper six bits of gray level 'A' data are given to all four adjacent pixels. If the lower two bits are "01", three of the four adjacent pixels give the upper six bits of gray 'A' data, and the other pixel receives the gray six 'A + 1' data obtained by adding one to the upper six bits of data. give. In this way, a gray level including the lower two bits can be displayed as the average data of four adjacent pixels. Similarly, if the lower two bits are "10" or "11", the upper six bits of 'A' data are added to two and one pixel, respectively, and the remaining two bits are added to the upper eight bits of data to three pixels. Give gradation 'A + 1' data. In this way, the spatial representation of the lower bits is dithering.

However, if the same voltage is continuously applied to one pixel, flicker is likely to occur, and thus dithering is performed in parallel with the frame rate control for displaying the data of one pixel so that the average is displayed for each frame.

3 shows a display state in a 4x2 pixel block according to the state of the lower two bits during four frames. Pixels shaded in the above pixel block are gray scale values indicated by the upper six bits of the RGB data, and pixels not shaded are the gray scale values indicated by the upper six bits plus '1', that is, the value of the upper gray scale. . In the 4x2 pixel block, 'o' stands for an odd column as an abbreviation of 'odd' and 'e' stands for an even column as an abbreviation of 'even'.

Referring to FIG. 3, four states of the lower two bits indicate four gray levels between two gray levels 'A' and 'A + 1', respectively, '00' is 'A', and '01' is 'A + 1'. / 4 ',' 10 'represents the gray level of' A + 2/4 ',' 11 'is' A + 3/4'. An example of the case where the lower two bits are '10' will be described. First, from a spatial point of view, if the lower two bits are '10', data is made such that the gray level 'A + 1' is always displayed in four pixels in a 4x2 pixel block having eight pixels. Also, from a temporal point of view, if the lower two bits are '10', for example, data is generated so that grayscale 'A + 1' is displayed twice in four frames in the one-row pixel of the odd-numbered column. Therefore, when temporally and spatially averaged, in a 4x2 pixel block, when the lower two bits are '10', the gray level obtained by adding the gray level 'A' to '2/4' may be recognized as an average. .

Meanwhile, in FIG. 3, in the 4 × 2 pixel block in which the lower two bits are '10', the gray level 'A' and the gray level 'A + 1' are displayed so that the same gray levels are not adjacent to each other. However, in contrast, in the 4 × 2 pixel block when the lower 2 bits are '10' in FIG. 4, the same gray level is displayed up and down at least once in any one of the odd and even columns. That is, in the first frame, the gray scale 'A' is displayed in the second and third row pixels of odd-numbered columns, and the gray scale 'A + 1' is displayed in the second and third row pixels of the even-numbered columns, and in the second frame, The gradation 'A' and the gradation 'A + 1' are displayed interchangeably. In the third frame, the gray scale 'A + 1' is displayed on the pixels 1 and 2 of the odd-numbered columns, the gray scale 'A' is displayed on the pixels 3 and 4, and the gray scale 'A' is displayed on the pixels 1 and 2 of the even columns. The gray scale 'A + 1' is displayed on the 3rd and 4th row pixels. Similarly, in the fourth frame, the gray level 'A' and the gray level 'A + 1' in the third frame are interchangeably displayed.

As shown in FIG. 4, when the spatial dithering process is performed to display a 1-dot pattern in the above-described 2 × 1 dot inversion driving, the pixel is turned on in the 4 × 2 pixel block when the lower 2 bits are '10' unlike in FIG. 3. Since the gray level 'A' is not repeatedly displayed on the pixel which is turned on, and the gray level 'A + 1' is not repeatedly displayed at the pixel which is turned off, the flicker phenomenon can be prevented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the dithering process according to the present invention is performed in the liquid crystal display, the flicker phenomenon can be prevented while simultaneously applying the frame rate control and the inversion driving method.

Claims (3)

Receiving 8-bit image data from an external device, and During four consecutive frames, the number of frames having a first gradation represented by the upper six bits of the image data and the number of frames having a second gradation one step higher than the first gradation are adjusted according to the lower two bits of the image data. Converting the frame data so that the display frequency of the first grayscale and the second grayscale is adjusted according to the lower two bits of the image data in a 4 × 2 pixel block. Including; In the frame data conversion step, when the lower two bits are '10', the frame data is converted such that at least once in each column of the 4x2 pixel block, the same gray level appears adjacent up and down. Driving method of liquid crystal display device. In claim 1, In the frame data converting step, when the lower two bits are '10', the first gray level is added to the second and third row pixels of the first column of the 4x2 pixel block in the first frame of the four consecutive frames. The second grayscale is displayed in the second and third row pixels of the first column, and in the second frame, the first grayscale and the second grayscale are alternately displayed in the first frame, and in the third frame, the 4x2 pixel is displayed. The first gray level to the first and second row pixels of the first column of the block, the second gray level to the third and fourth row pixels, the second gray level to the first and second row pixels of the second column, and the third and fourth row of pixels The frame data is converted to display the first gray scale, and in the fourth frame, the first gray scale and the second gray scale in the third frame are interchangeably displayed. Driving method of liquid crystal display device. A liquid crystal panel assembly comprising a plurality of pixels, A data driver which applies a data voltage corresponding to image data to the pixel, and Receiving 8-bit image data from an external device, the number of frames having a first gradation indicated by the upper six bits of the image data and the number of frames having a second gradation one step higher than the first gradation during four consecutive frames The data driver by converting the frame data to be adjusted according to the lower 2 bits of the image data, and adjusting the display frequency of the first gray level and the second gray level to be adjusted according to the lower 2 bits of the image data in a 4x2 pixel block. Signal control unit provided to Including; The frame data is converted such that at least once in each column of the 4x2 pixel block, the same gray level appears adjacent up and down when the lower two bits are '10'. Liquid crystal display.

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