KR100884997B1 - A driving circuit and a method for driving liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving circuit and a driving method of a liquid crystal display device for driving a liquid crystal panel. The driving circuit includes a random number generator using a vertical synchronization signal as a clock signal to generate at least two kinds of polarity signals, and a timing controller to select one kind of polarity signals. In response to the selected polarity signal, positive polarity and negative polarity are irregularly applied to the liquid crystal panel. By irregularly using the polarity signal on the liquid crystal display, the dim phenomenon and the flicker phenomenon due to the transverse luminance difference are minimized and the high quality is obtained.

LCD, random number generator, dot inversion driving method

Description

A driving circuit and a method for driving liquid crystal display device

1 is a plan view showing a general liquid crystal display device

2 is a block diagram of a general thin film transistor-liquid crystal display device

3A to 3D are diagrams for describing a driving method of a liquid crystal display device.

4A is a diagram for describing a method of driving a liquid crystal display using a conventional 1-dot inversion method.

4B is a diagram for describing a method of driving a liquid crystal display using a conventional 1-dot inversion method. FIG. 4B is a diagram showing an M + 1 th frame.

4C is a diagram for describing a method of driving a liquid crystal display using a conventional 1-dot inversion method. FIG. 4C is a diagram illustrating a pixel charging method according to a 1-dot inversion method.

FIG. 5A is a diagram for describing a method of driving a liquid crystal display using a conventional two-dot inversion method.

FIG. 5B is a diagram for describing a method of driving a liquid crystal display using a conventional two-dot inversion method. FIG. 5B is a diagram showing an M + 1 th frame.

FIG. 5C is a diagram for describing a method of driving a liquid crystal display using a conventional two-dot inversion method. FIG. 5C is a diagram showing a pixel charging method according to a two-dot inversion method.

6A is a diagram illustrating the generation of a preliminary polarity signal of any logic level by a random number generator in accordance with the present invention.

6B is a timing diagram showing the relationship between the vertical synchronization signal and the preliminary polarity signal according to FIG. 3A.

7 is a block diagram showing a driving circuit of the liquid crystal display according to the present invention.

8A to 8C are explanatory diagrams for generating and timing diagrams of a 1-dot polarity signal and a 2-dot polarity signal according to FIG. 7;

9 is a final polarization signal generation and logic circuit diagram in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

10: random number generator 20: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit and a driving method of a liquid crystal display device suitable for solving a dim phenomenon and a flicker phenomenon by irregularly performing an inversion method for each frame. It is about.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness and low power consumption, and mobile type such as notebook computer monitor. In addition, it is being developed in various ways such as a television for receiving and displaying a broadcast signal, a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display as a general screen display device in various parts, development of high quality images such as high definition, high brightness, and large area is required while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the first and second glass substrates. And a liquid crystal layer injected between the first and second glass substrates.

Here, the first glass substrate (TFT array substrate) includes a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing each of the gate lines and the data lines, and a plurality of pixels which are switched by signals of the gate lines to transfer signals of the data lines to the pixel electrodes Thin film transistors are formed.

The second glass substrate (color filter substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for implementing an image. Is formed.

The first and second glass substrates are bonded to each other by a seal material having a predetermined space by a spacer and having a liquid crystal injection hole, so that the liquid crystal is injected between the two substrates.

In this case, in the liquid crystal injection method, the liquid crystal is injected between the two substrates by osmotic pressure when the liquid crystal injection hole is immersed in the liquid crystal container by maintaining the vacuum state between the two substrates bonded by the reality. When the liquid crystal is injected as described above, the liquid crystal injection hole is sealed with a sealing material.

1 is a plan view illustrating a general liquid crystal display device.

As shown in FIG. 1, a plurality of gate lines 1 are arranged in one direction at regular intervals to define the pixel region 9 on the lower substrate, and are fixed in a direction perpendicular to the gate line 1. A plurality of data wires 3 are arranged at intervals.                         

A pixel electrode 8 is formed in each pixel region 9, and a thin film transistor T is formed at a portion where the gate lines 1 and the data lines 3 cross each other.

Here, the thin film transistor T is formed on the gate electrode 2 protruding from the gate wiring 1, the gate insulating film (not shown) formed on the front surface, and the gate insulating film above the gate electrode 2. The semiconductor layer 6, the source electrode 4 which protrudes from the said data wiring 3, and the drain electrode 5 so that it may oppose the said source electrode 4 are comprised.

The drain electrode 5 is electrically connected to the pixel electrode 8 through the contact hole 7.

On the other hand, the storage capacitor (Cst) is formed for the purpose of maintaining the cell voltage, the storage capacitor (Cst) is a metal film (3a) of the same material as the data wiring 3 on the gate wiring (1) of the front end It is formed so as to overlap in part, and is connected to the pixel electrode 8 through the contact hole (7a).

Therefore, when a voltage is applied to the pixel electrode 8, a gate insulating film is formed between the gate line 1 and the metal film 3a, thereby forming a storage capacitor Cst.

Although not shown in the drawing, the lower substrate 10 configured as described above includes a black matrix having an opening corresponding to the pixel area p and serving as a light blocking function, and a red / green / blue ( R / G / B) is bonded to an upper substrate including a color filter layer for displaying any color and a common electrode for driving a liquid crystal together with the pixel electrode 8.

The liquid crystal layer is formed between the two substrates bonded in this way.

However, the parasitic capacitance Cgs, the storage capacitance Cst, and the pixel electrode 8 formed between the gate electrode 2 and the source electrode 4 are characterized by the image quality characteristics of the general liquid crystal display device having the above structure. It is affected by the liquid crystal capacitance C _LC formed between the common electrodes.

That is, the variation ΔVp of the pixel voltage affecting the flicker phenomenon such as flickering on the screen may be expressed as a function of capacitance as shown in the following equation.

ΔVp = ΔVgCgs / (Cst + C _LC + Cgs)

ΔVg is the change in gate voltage, Cgs is the capacitance between the gate electrode and the source electrode in the thin film transistor, Cst is the storage capacitance, and C _LC is the liquid crystal capacitance.

It is preferable that such fluctuation? Vp has a small value, and if this fluctuation? Vp increases, flicker occurs.

2 is a configuration diagram of a general liquid crystal panel.

As shown in FIG. 2, a thin film transistor array having the configuration described with reference to FIG. 1 and a column drive for providing image signals R, G, and B analog signals to each data line CL of the thin film transistor array. The IC 20 and the gate lines GL of the thin film transistor array 10 are sequentially driven to turn on and off the thin film transistors T of the respective lines. It consists of a row driving IC 30 which allows an image signal applied to CL to be applied to the pixel electrode 8.

Here, when driving the TFT-LCD, the difference in luminance (due to the liquid crystal twist due to the difference in the electric field across the liquid crystal) occurs at regular time intervals (frequency 30Hz, 60Hz), causing the screen to flicker. This phenomenon is called flicker phenomenon.

The flicker of the 60 Hz period is represented by the OFF current and the leakage current of the TFT when charging and discharging are repeated in a frame period, and the flicker of the 30 Hz period is positive and negative. It is caused by the difference of effective voltage during negative voltage driving, the difference of ΔVp in the left and right of the screen due to the gate line delay, and the difference in ΔVp for each screen part due to the TFT characteristic deviation.

Accordingly, in order to reduce the occurrence of flicker, the driving circuit of the liquid crystal display device may include a frame inversion method, a line inversion method, and a column inversion as shown in FIGS. 3A to 3D. Inversion methods such as the < RTI ID = 0.0 >) and Dot Inversion method are used, respectively.

That is, in the frame inversion scheme in which the polarities of the data voltages applied to the liquid crystal with respect to the common electrode voltage are equally applied in units of frames, as shown in FIG. If is applied, a data voltage of negative polarity is applied to an odd frame.

However, such a frame inversion scheme has a small current consumption during switching, but is sensitive to flicker due to transmittance asymmetry between positive and negative polarity, and crosstalk due to inter-data interference. There is a problem that is very vulnerable.

The line inversion method is a polarity inversion driving method which is generally used for low resolution (VGA, SVGA, etc.) and applies a data application voltage so that the polarity of the pixel varies in units of horizontal lines. That is, as shown in FIG. 3B, a positive polarity data voltage is applied to the odd-numbered line and a negative polarity data voltage is applied to the even-numbered line, and in the next frame, a polarity data voltage is applied to the odd-numbered line and the even-numbered line. Apply the data voltage.

Since the line inversion scheme is applied with voltages of opposite polarity to adjacent lines, the flicker phenomenon is smaller than that of the frame inversion scheme by spatial averaging. Since the voltage of polarity is distributed, the coupling phenomenon between data is canceled, and thus the vertical crosstalk is small.

However, since voltages of the same polarity are distributed in the horizontal direction, horizontal crosstalk occurs, and the number of switching repetitions increases compared to the frame inversion method, and thus the current consumption increases.

The column inversion scheme is a driving scheme in which the polarity of the applied data voltage is applied with the same polarity in the vertical direction and the opposite polarity in the horizontal direction as in FIG. 3C.

Therefore, the flicker phenomenon and the horizontal crosstalk are small by the spatial averaging method as in the line inversion method.                         

However, a high voltage column driver IC must be used because data voltages having opposite polarities between adjacent lines must be applied in a vertical direction with respect to the common electrode.

Lastly, the dot inversion method is a driving method that realizes the best image quality at present, and is applied to high resolution (XGA, SXGA, UXGA, etc.), and as shown in FIG. 3D, the polarity of the data voltage between adjacent pixels in all directions This is the opposite.

Therefore, the dot inversion method can minimize the flicker by the spatial averaging method, but has a problem that a high voltage column driver IC must be used and the current consumption is large.

As described above, the phase of the image signal is inverted line by line or dot by dot. When the voltage difference of the same polarity persists between the pixel electrode and the common electrode, the liquid crystal between the pixel electrode and the common electrode deteriorates and the image flickers. Or dark.

By the way, the dot inversion method has less image flickering or darkening than the line inversion method or the column inversion method, and thus the image quality is good. This is because pixel voltages of different phases are applied to adjacent pixel electrodes.

For example, if a positive polarity pixel voltage is applied to the first pixel during the first period, a negative polarity pixel voltage is applied to the adjacent second pixel. Then, when a negative polarity pixel voltage is applied to the first pixel during the next period, a positive polarity pixel voltage is applied to the adjacent second pixel.                         

However, if a voltage drop occurs in a positive polarity pixel voltage at a first pixel during a predetermined period, a negative polarity pixel voltage is applied to the first pixel in a next period, so that a positive (+) Polarity pixel voltage drop is compensated for.

Among the polarity inversion schemes, the most widely used method for the best image quality and high resolution (XGA, SXGA, UXGA) is the dot inversion driving method. The dot inversion driving method is classified into a 1-dot inversion driving method and a 2-dot inversion driving method. Hereinafter, these two methods will be described with reference to the accompanying drawings.

4A to 4C are diagrams for describing the driving method for the 1-dot inversion. 4A is a diagram for explaining a conventional dot inversion driving method, and is a diagram for explaining the polarity of the data voltage of the Mth frame. FIG. 4B is a diagram illustrating a conventional dot inversion driving method and illustrating a polarity of a data voltage of an M + 1th frame.

As described above, the plurality of gate lines G1 -Gn and the plurality of data lines S1 -Sn are arranged in a direction crossing each other to form pixel regions in a matrix form. The data voltages are applied such that polarities of the data voltages applied to adjacent pixels in all directions of up, down, left, and right are opposite to each other. Then, the polarity of each pixel region in the next frame is reversed to the respective corresponding polarity in the previous frame.

That is, in consideration of the M th frame, when the odd gate lines are driven, the positive data voltages are applied to the odd data lines S1, S3, S5,... Negative polarity data voltages are applied to (S2, S4, S6, ...). When the even-numbered gate lines are driven, negative data voltages are applied to the odd-numbered data lines S1, S3, S5, ..., and the even-numbered data lines S2, S4, S6, ... ) Is applied with positive data voltages.

In consideration of the M + 1 th frame, which is the next frame of the M th frame, the odd-numbered data lines S1, S3, S5, ... when the odd-numbered gate lines are driven in contrast to the M-th frame. Negative data voltages are applied to (), and positive polarity data voltages are applied to even-numbered data lines (S2, S4, S6,...). Meanwhile, when the even-numbered gate lines are driven, positive data voltages are applied to the odd-numbered data lines S1, S3, S5,..., And even-numbered data lines S2, S4, and S6. Negative polarity data voltages are applied to.

4C is a diagram illustrating a charging shape of each pixel during the 1-dot inversion. As described above, in the 1-dot inversion scheme, the polarity change of each pixel to be charged and the polarity change of each corresponding charge voltage are the same, so that each corresponding charge is equally changed when the polarity change of each pixel is changed. The polarity of the voltage also changes. Thus, a flicker phenomenon may occur.

5A to 5C are diagrams illustrating the two-dot inversion driving method. FIG. 5A is a diagram for describing the two-dot inversion driving method and illustrates a polarity of a data voltage applied to an Mth frame. FIG. 5B is a diagram illustrating the two-dot inversion driving method and illustrating the polarity of the data voltage applied to the M + 1th frame.

As shown in FIGS. 5A to 5C, in the liquid crystal panel according to the present invention, n gate lines G1 -Gn and n data lines S1 -Sn are arranged in a direction orthogonal to each other. Pixel regions are formed in a matrix form. On the liquid crystal panel, two gate lines are divided into blocks in a row direction. Polarities of the data voltages applied to the adjacent blocks are opposite to each other.

In addition, polarities of data voltages applied to adjacent pixels in the column direction on the liquid crystal panel are reversed. On the other hand, in the next frame, the polarity of each pixel area is opposite to the polarity of the previous frame.

Referring to FIG. 5A, when the gate lines G1 + G2, G5 + G6, G9 + G10, ... are driven in the Mth frame, the odd-numbered data lines S1, are driven. Positive polarity data voltages are applied to S3, S5, ..., and negative polarity data voltages are applied to even-numbered data lines S2, S4, S6, ....

When the gate lines corresponding to the even-numbered blocks G3 + G4, G7 + G8, G11 + G12, ... are driven, the odd-numbered data lines S1, S3, S5, ... Data voltages of negative polarity are applied and data voltages of positive polarity are applied to the even-numbered data lines S2, S4, S6, ....

Referring to FIG. 5B, in the M + 1th frame, which is the next frame of the Mth frame, gate lines G1 + G2 and G5 + corresponding to the odd-numbered blocks in a row direction on the liquid crystal panel. When G6, G9 + G10, ... are driven, negative data voltages are applied to the odd-numbered data lines S1, S3, S5, ..., and the even-numbered data lines S2, S4. , S6, ... are applied with positive polarity data voltages.

On the contrary, when the gate lines corresponding to the even-numbered blocks G3 + G4, G7 + G8, G11 + G12, ... are driven, the odd-numbered data lines S1, S3, S5, ... Negative data voltages are applied to (), and negative polarity data voltages are applied to the even-numbered data lines (S2, S4, S6,...).

5C is a diagram illustrating a pixel filling shape in the 2-dot inversion. As described above, according to the conventional method of driving the liquid crystal panel using the two-dot inversion, the polarity fluctuation of each pixel being charged and the polarity fluctuation of the charging voltage applied to the respective pixels are different so that the brightness between the sound blocks is different. There was a problem that a difference occurs, and furthermore, a dim phenomenon occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention provides a driving circuit and a driving method of a liquid crystal display device to minimize flicker and dim by irregularly performing an inversion method every frame of the liquid crystal panel. The purpose is to provide.

The driving circuit of the liquid crystal display according to the present invention for achieving the above object comprises a random number generator for generating a selection signal having a random logic level by the vertical synchronization signal as a clock signal using a vertical synchronization signal; At least two kinds of polarity signals of the dot inversion method are made in the frame unit by using the horizontal synchronization signal and the vertical synchronization signal as the clock signal, and the polarity signals of the random dot inversion method are output according to the level of the selection signal. And a timing controller.

The random number generator generates a preliminary polarity signal having a high or low logic level in units of the vertical synchronization signal, and the random dot inversion method is any one of a 1-dot inversion method and a 2-dot inversion method. The timing controller generates a first polarity signal using the vertical synchronization signal and the horizontal synchronization signal as clock signals to generate a 1-dot inversion polarity signal as a first polarity signal in units of the vertical synchronization signal. Circuits; A second polarity signal generating circuit for generating a 2-dot inversion polarity signal as a second polarity signal in the vertical synchronization signal unit using the vertical synchronization signal and the horizontal synchronization signal as clock signals; And a third polarity signal generation circuit configured to select one of the first polarity signal and the second polarity signal as a final polarity signal in units of the vertical synchronization signal using the preliminary polarity signal as the selection signal. It is a drive circuit for liquid crystal display devices.

The polarity signal of the 1-dot inversion type has a change in polarity within each period of the vertical synchronization signal, and the polarity signal of the two-dot inversion type at the rising edge of each period of the horizontal synchronization signal. And having a change in polarity, wherein the first polarity signal generating circuit uses the vertical synchronous signal as a clock signal, a first D flip-flop connected to an input terminal and an inverted output terminal, and sets the horizontal synchronous signal as a clock signal. Exclusive OR for receiving a second D flip-flop connected to a terminal and an inverted output terminal, and output signals of the first D flip-flop and the second D flip-flop as two input signals and outputting the first polarity signal (Exclusive OR) A driving circuit for a liquid crystal display device, characterized in that it comprises a gate.

The second polarity signal generating circuit includes a third D flip-flop in which the vertical synchronization signal is a clock signal and an input terminal and an inverting output terminal are connected, and a fourth D flip in which the horizontal synchronization signal is a clock signal and an input terminal and an inverting output terminal are connected. A flop, a fifth D flip-flop connected with an input terminal and an inverted output terminal as an output signal of the fourth D flip-flop, and output signals of the third D flip-flop and the fifth D flip-flop as two input signals. And a second exclusive OR gate for receiving and outputting the polarity signal of the two dot inversion method.

The third polarity signal generating circuit includes a first inverter for inverting the preliminary polarity signal, a second inverter for inverting the output signal of the first inverter, and an output signal of the first polarity signal and the second inverter. A second AND gate which receives as input signals and receives the first AND gate, an output signal of the first inverter and the second polarity signal as two input signals, and the first AND gate and the second And a first OR gate which receives the output signals of the AND gate as two input signals.                     

Generating a polarity selection signal of a random logic level using each vertical synchronization signal as a clock signal; generating at least two types of polarity signals of the dot inversion scheme in units of frames using the horizontal synchronization signal and the vertical synchronization signal as a clock signal. And generating one of the at least two kinds of polarity signals as a final polarity signal according to the level of the polarity selection signal.

The at least two types of polarity signals of the dot inversion method include a polarity signal of the 1-dot inversion method and a polarity signal of the 2-dot inversion method.

 The level signal of the random logic circuit is a method of generating a polarity signal for a liquid crystal display device characterized by a high level signal and a multilevel signal.

Hereinafter, a driving circuit and a driving method of a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

 6A is a diagram illustrating the generation of an arbitrary polarity signal POL_S in accordance with the present invention. The arbitrary polarity signal POL_S is generated by the random number generator 10 using the vertical synchronization signal Vsync as a clock signal from a system interface unit (not shown).

6B shows a timing diagram of an arbitrary polarity signal POL_S and the vertical synchronization signal Vsync. The generated arbitrary polarity signal POL_S is synchronized with the rising edge of the vertical synchronization signal Vsync by the random number generator 10 so that its level, that is, high and low, is arbitrarily selected. Is determined.

Accordingly, the random number generator 10 uses the vertical synchronization signal Vsync as the clock signal CLK to generate the arbitrary polarity signal POL_S every cycle of the vertical synchronization signal Vsync.

7 is a schematic block diagram showing a driving circuit of the liquid crystal display according to the present invention.

As illustrated in FIG. 7, the random number generator 10 generates a random polarity signal POL_S every cycle of the vertical synchronization signal Vsync using the vertical synchronization signal Vsync as a clock CLK. The timing controller 20 then selects 1-dot or 2-dot inversion in response to the polarity signal POL_S that is applied to the selection pin. That is, the polarity signal POL_S is used as one inversion selection control signal. Therefore, the 1-dot inversion signal or the 2-dot inversion signal is output from the timing controller 20.

8A shows a logic circuit that generates a 1-dot polarity signal 1H_POL.

As shown in Fig. 8A, the first D-flip-flop 2 and the horizontal sync signal Hsync, which use the vertical synchronization signal Vsync as a clock signal and the non-inverted output signal as an input signal, The second D-flip flop 3 having the inverted output signal as an input signal, and the output signals of the first D-flip flop 2 and the second D-flip flop 3 using two input signals. It consists of an XOR gate 4 which generates the 1-dot polarity signal 1H_POL.

More specifically, the first D-flip-flop 2 inputs the vertical synchronization signal Vsync to its clock signal terminal CLK, and its inverted output terminal / Q (/ is inverted). Signal is the same below) is connected to the input terminal (D).

Also, the second D-flip-flop 3 inputs the horizontal synchronizing signal Hsync to its clock signal terminal CLK, and its inverting output terminal / Q has its input terminal D. It is connected with.

Signals output from each of the non-inverted output terminals Q of the first and second D-flip flops 2 and 3 are input to the XOR gate 4 and the XOR gate 4. Outputs the 1-dot polarity signal 1H_POL by performing a logical operation on the output signals of the first and second D-flip flops 2 and 3 as input signals, respectively.

The 1-dot polarity signal 1H_POL output from the XOR gate 4 is inverted every cycle of the horizontal sync signal Hsync and also inverted every cycle of the vertical sync signal Vsync.

8B shows a logic circuit that generates a two-dot polarity signal 2H_POL.

As shown in FIG. 8B, the third and fourth D-flip flops 5, 6 which use the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync as clock signals and their inverted output signals as input signals, respectively. ), A fifth D flip-flop 7 whose output signal of the fourth D flip-flop 6 is a clock signal and its inverted clock signal as an input signal, and the third D flip-flop 5 ) And a second XOR gate 8 for generating the two-dot polarity signal 2H_POL as the two input signals of the fifth D-flip-flop 7.                     

That is, the fifth D-flip flop 7 is added one more than the logic circuit for generating the 1-dot polarity signal 1H_POL.

The third D flip-flop 5 inputs the vertical synchronization signal Vsync to its clock terminal CLK, and the output signal of its inverted output terminal / Q is its input terminal D. Return to

In addition, the horizontal synchronization signal Hsync is input to the clock terminal CLK of the fourth D flip-flop circuit 6. The output signal of the inverted output terminal / Q of the fourth D flip-flop 6 is fed back to its input terminal D. The signal output from the output terminal Q of the fourth D flip-flop 6 is input to the clock terminal CLK of the fifth D flip-flop 7, and its inverted output terminal / Q. The signal output from it is fed back to its input terminal D.

 Signals output from the inverted output terminals / Q of the third and fifth D-flop flops 5 and 7 are input to the second XOR gate 8 and the second XOR gate 8 Outputs a 2-dot polarity signal 2H_POL by performing an exclusive logic operation on the two input signals.

The two-dot polarity signal 2H_POL output from the second XOR gate 8 is inverted every two periods of the horizontal synchronization signal Hsync, and is also inverted every one period of the vertical synchronization signal Vsync.

8C is a timing diagram illustrating the 1-dot polarity signal 1H_POL and the 2-dot polarity signal 2H_POL.                     

As shown in FIG. 8C, the 1-dot polarity signal 1H_POL is generated in synchronization with a rising edge of the horizontal synchronization signal Hsync, and is inverted to an opposite polarity signal within a period of the horizontal synchronization signal. .

The reverse polarity signal is then inverted again at the rising edge of the next horizontal sync signal. That is, the polarity signal of the 1-dot polarity signal is inverted once in each period of the horizontal synchronization signal.

The two-dot polarity signal 2H_POL is inverted in synchronization with the rising edge of each of the horizontal synchronization signals Hsync. That is, the two-dot polarity signal is not inverted for one period of each horizontal synchronization signal, and the same polarity signal is maintained.

9 shows a logic circuit for generating the final polarity signal POL.

As shown in FIG. 9, the first and second inverters 11 and 12, which receive an arbitrary polarity signal POL_S, are delayed for a predetermined time and output, and the output signal and external of the second inverter 12 are output. Inputs a first AND gate 14 for receiving a 1-dot polarity signal 1H_POL of the first logic input and a logic operation and outputs the output signal of the first inverter 11 and an external 2-dot polarity signal 2H_POL. And a second AND gate 15 that receives and logically operates and outputs the output signal of the first and second AND gates 14 and 15.

More specifically, the arbitrary polarity signal POL_S is input to the first inverter 11, and the output signal of the first inverter 11 is input to the second inverter 12. The signal output from the second inverter 12 is input to the first AND gate 14. Meanwhile, the 1-dot polarity signal 1H_POL is directly input to the first AND gate 14.

The arbitrary polarity signal POL_S is inverted in the first inverter 11 to become an input signal of the second AND gate 15, and the two-dot polarity signal 2H_POL is connected to the second AND gate 15. It becomes another input signal.

Signals output from the first and second AND gates 14 and 15 are also input to the OR gate 16, and the OR gate 16 logically combines the two input signals to generate a final polarity signal POL. Outputs

That is, the final polarity signal POL is generated by selecting the 1-dot polarity signal 1H_POL and the 2-dot polarity signal 2H_POL as an arbitrary polarity signal POL_S to generate the final polarity signal POL. The dot inversion driving method is determined by generating a 1-dot or 2-dot polarity signal 2-H_POL in random order).

As described above, the driving circuit and driving method of the liquid crystal display device of the present invention have the following effects.

That is, according to the conventional 1-dot or 2-dot inversion method, voltages of positive and negative polarities are regularly applied to the liquid crystal panel. Due to the regular dot reversal method, flicker and dim have occurred on the liquid crystal panel. Meanwhile, in the present invention, a random polarity signal POL_S is generated using a vertical synchronization signal Vsync as a clock signal of a random number generator, and then the liquid crystal panel is driven by an irregular dot inversion method using the vertical synchronization signal Vsync. Accordingly, the flicker phenomenon and the dim phenomenon can be minimized, and the side effect of the liquid crystal panel can be excluded.

Claims (9)

A random number generator using a vertical synchronization signal as a clock signal to generate a selection signal having a random logic level in units of the vertical synchronization signal; And By using the horizontal synchronization signal and the vertical synchronization signal as a clock signal, at least two kinds of polarity signals of the dot inversion method are made in units of frames, And a timing controller for outputting a polarity signal of a random dot inversion method, in accordance with the level of the selection signal generated by the random number generator. The driving circuit of claim 1, wherein the random number generator generates a preliminary polarity signal having a high or low logic level in units of the vertical synchronization signal. The first timing controller of claim 1, wherein the timing controller generates a polarity signal of a 1-dot inversion type as a first polarity signal in units of the vertical synchronization signal using the vertical synchronization signal and the horizontal synchronization signal as clock signals. Polarity signal generating circuit; A second polarity signal generating circuit for generating a 2-dot inversion polarity signal as a second polarity signal in the vertical synchronization signal unit using the vertical synchronization signal and the horizontal synchronization signal as a clock signal; And And a third polarity signal generating circuit configured to select one of the first polarity signal and the second polarity signal as a final polarity signal in units of the vertical synchronization signal using the preliminary polarity signal as the selection signal. A driving circuit of the liquid crystal display device. 4. The apparatus of claim 3, wherein the first polarity signal generating circuit comprises: a first D flip-flop, wherein the vertical synchronization signal is a clock signal and an input terminal and an inverting output terminal are connected; A second D flip-flop connected with the horizontal synchronization signal as a clock signal and having an input terminal and an inverted output terminal; And an XOR gate configured to receive output signals of the first D-flip flop and the second D-flip flop as two input signals and output the first polarity signal. 4. The second polarity signal generating circuit of claim 3, wherein the second polarity signal generating circuit comprises: a third D flip-flop, wherein the vertical synchronization signal is a clock signal and an input terminal and an inverting output terminal are connected; A fourth D flip-flop, wherein the horizontal synchronization signal is a clock signal and an input terminal and an inverting output terminal are connected; A fifth D flip-flop connected with an input terminal and an inverted output terminal as the clock signal using the output signal of the fourth D flip-flop, and And a second XOR gate configured to receive output signals of the third D-flip flop and the fifth D-flip flop as two input signals, and output a polarity signal of the two dot inversion scheme. Driving circuit. The method of claim 3, wherein the third polarity signal generating circuit comprises: a first inverter for inverting the preliminary polarity signal; A second inverter for inverting the output signal of the first inverter, The first polarity signal and the output signal of the second inverter are received as two input signals and the first AND gate, A second AND gate receiving the output signal of the first inverter and the second polarity signal as two input signals, and And a first OR gate configured to receive output signals of the first AND gate and the second AND gate as two input signals. Generating a polarity selection signal of a random logic level by using every vertical synchronization signal as a clock signal; Generating a polarity signal of at least two kinds of dot inversion schemes in units of frames by using a horizontal synchronization signal and the vertical synchronization signal as a clock signal; and And generating one of said at least two kinds of polarity signals as a final polarity signal in accordance with the level of said polarity selection signal. 8. The method of claim 7, wherein the at least two types of dot inversion polarity signals include a polarity signal of 1-dot inversion and a polarity signal of 2-dot inversion. 8. The method of claim 7, wherein the level signal of the random logic circuit is a high level signal and a multi level signal.

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