JP3675113B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device including a driver that converts digital image data into an analog signal voltage, and a panel that operates by the signal voltage and displays an image.
[0002]
[Prior art]
As a panel used for a display device, for example, an active matrix liquid crystal display (LCD) is widely used. An active matrix LCD panel has a flat structure in which liquid crystal is held as an electro-optical material between a pair of upper and lower substrates. On one substrate, pixel electrodes arranged in a matrix and thin film transistors that drive the switching are integrated. A counter electrode is entirely formed on the other substrate. Thin film transistors can be broadly classified into thin film transistors (poly-Si TFT) using polycrystalline silicon as an active layer and thin film transistors (α-Si TFT) using amorphous silicon as an active layer. The poly-Si TFT has a relatively high performance and can incorporate a peripheral scanning circuit on the same substrate in addition to a switching element for driving a pixel. On the other hand, since the α-Si TFT has a relatively low performance, a peripheral scanning circuit cannot be built in, and is generally an external type.
[0003]
[Problems to be solved by the invention]
In recent years, the resolution of LCD panels has been increased. For example, in the XGA standard, 1024 pixels in a matrix are arranged in the horizontal direction and 768 in the vertical direction. In the case of performing full color display, the number of pixels in the horizontal direction increases to 1024 × 3 = 3072. As the pixels become higher in definition and higher in density in this way, the transfer rate of the horizontal scanning circuit cannot catch up with the conventional built-in LCD panel, and it is difficult to display an XGA standard image. When displaying an XGA standard image, the effective time assigned to one horizontal period (1H) is about 10 μs, and in order to sample a signal voltage on 3072 signal lines, a selection time per signal line is required. About 10 ns. It is impossible to sufficiently write the signal voltage to the pixels in such a short time, and high-quality display cannot be performed. In addition, in an LCD panel using α-Si TFTs, a scanning circuit in addition to a driver for supplying a signal voltage is also provided externally. These are generally supplied as LSI chips. As described above, when full color display is performed in accordance with the XGA standard, 3072 signal lines and 768 scanning lines are required. For this reason, the LSI chip must be connected to a total of about 3800 panel-side wirings. From the viewpoint of mounting, a decrease in yield becomes a problem, and a large number of LSI chips are required, which causes an increase in cost.
[0004]
[Means for solving the problems]
In order to solve the above-mentioned problems of the prior art, the following measures were taken. A display device according to the present invention includes, as a basic configuration, a driver that converts digital image data into an analog signal voltage, and a panel that operates by the signal voltage and displays an image. According to the first aspect of the present invention, the panel includes a row-shaped scanning line, a column-shaped signal line, a matrix-like pixel arranged at the intersection of the two, and a row connected to the scanning line sequentially. A vertical scanning circuit for selecting the pixels, a switch that is provided for each set of a predetermined number of signal lines and applies a signal voltage for one set to a set of signal lines simultaneously, and a switch that is provided for each set is opened and closed sequentially. And a horizontal scanning circuit for writing a signal voltage to pixels of one row selected in this manner. The driver includes a shift register that sequentially transfers image data input from the outside, a latch memory that collectively collects one set of image data from the shift register, and one set of image data that has been captured. And a digital / analog converter for converting the signal voltage to the panel and supplying it to the panel. The driver is connected to the panel by wiring corresponding to a set of signal voltages. With this configuration, when the panel is writing a set of signal voltages, the driver transfers the next set of image data.
[0005]
According to the second aspect of the present invention, the panel is connected to the scanning line in a row by row scanning lines, column signal lines, matrix pixels arranged at the intersection of both, and the scanning lines. A vertical scanning circuit for selecting pixels, a switch group capable of distributing a predetermined number of signal voltages to a predetermined number of signal lines arranged at a fixed number, and opening / closing scanning of the switch group by repeating a predetermined number of times A horizontal scanning circuit for writing a signal voltage to a plurality of pixels determined by the product of the predetermined number of times and for performing the writing on all the selected pixels. The driver includes a shift register for sequentially transferring image data for one row input from the outside, and the plurality of image data corresponding to a part of the image data for one row from the shift register. A serial / parallel converter that divides the image data into a predetermined number at predetermined intervals and reads the image data in a predetermined number of times, and digital / analog that converts the predetermined number of read image data into signal voltages and repeatedly supplies them to the panel a predetermined number of times. And a converter. With this configuration, when the panel is writing a signal voltage to a plurality of pixels determined by the product of the predetermined number and the certain number of times, the driver transfers image data to be assigned to the next plurality of pixels. Do.
[0006]
The display device according to the first aspect of the present invention uses a driver including an N-stage shift register, a latch memory, a digital / analog converter, an output buffer, and the like. The N-stage shift register is transferred M times in one horizontal period (1H). When one data transfer of the shift register is completed, N pieces of image data are taken into the latch memory as a set. Based on this set of captured image data, a signal voltage for driving the panel is generated, thereby driving the panel. While the next set of data is transferred by the N-stage shift register, the signal voltage described above is applied to the panel to display an image. By repeating the N-stage data transfer M times, the signal voltage can be written at 1H to N × M pixels in one row. In this manner, N signal voltages can be simultaneously written at one time, and a sufficient writing time is ensured to realize a high-quality display. Further, since the signal writing frequency in the panel is lowered, the power consumption can be reduced.
[0007]
A display device according to the second aspect of the present invention provides a panel using a driver having an m-stage shift register, an n × θ = m-stage latch memory, a serial / parallel converter, a θ-stage digital / analog converter, and an output buffer. Driving. The serial / parallel converter fetches m = n × θ pieces of image data, and then reads out the serial data divided every n times into θ pieces of parallel data. On the other hand, the panel has n stages of horizontal scanning circuits for each block, and each of θ signal voltages is divided into n signal lines by n switches. The n switches can be controlled by an n-stage horizontal scanning circuit. Accordingly, θ signal voltages are divided into n times and written to n × θ = m pixels. This scanning is repeated for a plurality of blocks, and signal voltages are written to pixels for one row. With such a configuration, θ signal voltages can be simultaneously written to the pixel, and a sufficient writing time can be secured.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing a first embodiment of a display device according to the present invention. As shown in the figure, this display device is composed of a driver 1 and an LCD panel 2. The LCD panel 2 is an active matrix type, and a scanning line X and a signal line Y intersecting each other are arranged on the screen portion. Pixels PXL are formed at the intersections between the row-shaped scanning lines X and the column-shaped signal lines Y. The pixel PXL includes a liquid crystal capacitor LC, an auxiliary capacitor CS, and a thin film transistor Tr. The liquid crystal capacitor LC is composed of a pixel electrode and a counter electrode COM facing the pixel electrode, and a liquid crystal is held as an electro-optical material between the two electrodes. The liquid crystal capacitor LC is driven by the thin film transistor Tr. The drain electrode of the thin film transistor Tr is connected to the corresponding liquid crystal capacitor LC and auxiliary capacitor CS, the source electrode is connected to the corresponding signal line Y, and the gate electrode is connected to the corresponding scanning line X. Each scanning line X is connected to a V shift register 21 constituting a vertical scanning circuit, and is selectively scanned in a line sequential manner. One row of thin film transistors Tr connected to the selected scanning line X is placed in a conductive state. As a result, the liquid crystal capacitors LC included in one row of pixels PXL are electrically connected to the corresponding signal lines Y, respectively. The V shift register 21 operates in accordance with the vertical clocks VCK1 and VCK2 input from the outside, and sequentially selects the scanning lines X by sequentially transferring the vertical start pulses VST supplied from the outside. It has become. VCK1 and VCK2 have opposite polarities.
[0009]
M switches HSW1, HSW2,..., HSWM are formed at the upper periphery of the LCD panel 2. Each HSW is provided for each set of a predetermined number (N) of signal lines Y, and a set of signal voltages OUT1, OUT2,..., OUTN supplied from the driver 1 is simultaneously applied to a set of signal lines. Apply to Y. Further, an H shift register 22 constituting a horizontal scanning circuit is arranged on the upper periphery of the LCD panel 2, and a switch HSW1, HSW2,. The signal voltages OUT1, OUT2,..., OUTN are written into the corresponding pixels PXL (N × M). Each HSW can apply N signal voltages OUT1 to OUTN to N signal lines Y at a time.
[0010]
On the other hand, the driver 1 includes an N-stage shift register 11, an N-stage latch memory 12, an N-stage voltage generator 13, and an N-stage output buffer 14. The N-stage shift register 11 sequentially transfers digital image data input from the outside in accordance with a predetermined shift clock. The N-stage latch memory 12 operates in response to the latch pulse, and fetches one set of image data (N pieces) from the N-stage shift register 11 at once. The N-stage voltage generator 13 is a digital / analog converter (DAC), and converts a set of digital image data captured by the latch memory 12 into a set of analog signal voltages OUT1, OUT2,..., OUTN. . The DAC generates a signal voltage using a reference voltage supplied from the outside. The generated N signal voltages OUT1, OUT2,..., OUTN are supplied to the LCD panel 2 via the N-stage output buffer.
[0011]
FIG. 2 is a table for explaining the operation of the voltage generator (digital / analog converter) 13 shown in FIG. In this example, a signal voltage OUT is generated by selecting any of 16 gradation reference voltages V0 to V15 according to digital image data having 4 bits (D0, D1, D2, D3) as 1 byte. . However, in an actual display device, digital image data having 6 bits or 8 bits as one byte is often used. 6-bit digital image data can express 64 gradations, and 8-bit digital image data can express 256 gradations. When the digital image data (D0, D1, D2, D3) assigned to a certain pixel PXL takes the value (1, 1, 1, 1), the highest reference voltage V0 is applied to the pixel PXL. . If the LCD panel 2 performs monochrome display in the normally white mode, the pixel PXL exhibits black color by applying the highest reference voltage V0. Further, when the digital image data (D0, D1, D2, D3) takes a value of (0, 0, 0, 0), the lowest reference voltage V15 is applied as a signal voltage to the pixel PXL, and white color is exhibited. . When the value of the digital data (D0, D1, D2, D3) is (1, 0, 0, 0), a substantially intermediate reference voltage V7 is applied as a signal voltage, and the pixel PXL has a substantially intermediate gray color. Present. In general, the LCD panel 2 gives the pixel PXL brightness divided into multiple gradations from black to white according to the value of digital data having a multi-bit configuration.
[0012]
FIG. 3 is a timing chart showing various signals input from the outside to the display device shown in FIG. A horizontal start pulse HST is input to the H shift register 22 on the LCD panel 2 side every 1H. A horizontal clock HCK is also supplied to sequentially transfer the HST. HCK contains M pulses per 1H. On the other hand, a shift clock is input to the N-stage shift register 11 on the driver 1 side. A latch pulse is input to the N-stage latch memory 12. This latch pulse is in phase with the above-described HCK, and exactly N data shift clocks are included in the period of the adjacent latch pulse.
[0013]
The operation of the display device shown in FIG. 1 will be described in detail below with reference to the timing chart of FIG. The driver 1 has an N-stage shift register 11 and an N-stage latch memory 12. The latched digital image data is processed by the N-stage voltage generator 13 and converted into an analog signal voltage weighted or gradation according to the value. The analog signal voltages OUT1, OUT2,..., OUTN are output from the N-stage output buffer 14 to the LCD panel 2 side. For example, when displaying in the XGA standard, the shift register 11 transfers digital image data of 1024 × 3 = 3072 bytes per 1H. Here, when N = 384 is set, M = 8. The digital image data input from the outside is latched by the N-stage latch memory 12 when 384 bytes are transferred by the N-stage shift register 11. The latched digital image data is converted into an analog signal voltage by the N-stage voltage generator 13 and input to the LCD panel 2 side through the output buffer 14. The shift register 11 on the driver 1 side transfers the next 384 bytes of digital data after the 384 bytes of digital data are latched.
[0014]
On the other hand, when the first 384 signal voltages OUT1, OUT2,..., OUTN are input, the LCD panel 2 turns on the HSW1 and applies the signal voltages OUT1 to OUTN to the corresponding 384 signal lines Y. . The on-time of the HSW1 lasts until the next 384 bytes of digital data are transferred. When the next 384 bytes of digital data are transferred by the shift register 11 of the driver 1, the latch memory 12 takes in the digital data of 384 bytes again. At this time, HSW1 shifts to the off state, and HSW2 is turned on instead. As a result, the next 384 signal voltages OUT1 to OUTN are written to the corresponding 384 signal lines Y. Thus, by repeating the opening / closing operation (ON / OFF operation) of HSW1 to HSWM 8 times, a total of 3072 bytes of image data is written to each pixel PXL. In the case of the XGA standard, data transfer is performed with a 95 MHz shift clock. In this case, the time for transferring 384 bytes of data is about 1.3 μs. During this time, the LCD panel 2 can write to the signal line Y. Conventionally, only about 10 ns time could be secured, but in the present invention, sufficient writing time can be secured, and high-quality display can be realized. Further, since the signal writing frequency in the LCD panel 2 is lowered, the power consumption can be reduced. In addition, since the LCD panel 2 can be driven by the one-chip driver 1 according to the present invention, it is not necessary to perform electrical connection between the IC chip and the LCD panel over thousands of wires as in the prior art. Reliability is improved.
[0015]
FIG. 4 is a block diagram showing a second embodiment of the display device according to the present invention. As shown in the figure, this display device includes a driver 1 that converts digital image data into analog signal voltages OUT1 to OUTθ, and an LCD panel 2 that operates by θ signal voltages OUT1 to OUTθ and displays an image. ing. The driver 1 converts the digital image data into an analog signal voltage and writes it to the pixels of the LCD panel 2 to display an image. The driver 1 includes an m-stage shift register 11, a serial / parallel converter 15, a θ-stage voltage generator 13, and a θ-stage output buffer 14. The m-stage shift register 11 operates according to the shift clock 1 and sequentially transfers digital image data input from the outside. The serial / parallel converter 15 collectively takes in image data to be assigned to a plurality (m) of pixels PXL and delimits them by a predetermined number (θ) every predetermined number (n). Read it out separately. Specifically, the serial / parallel converter 15 collectively takes m bytes of digital data according to a latch pulse supplied from outside, and further receives m bytes of digital data according to a shift clock 2 supplied from outside. Rearrange by θ bytes and read by dividing into a certain number of times n. In the first round, the total θ bytes of the first byte, n + 1 byte, 2n + 1 byte,..., N (θ−1) +1 byte are read and sent to the voltage generator 13 side in the subsequent stage. . In the second time (n = 2), the total θ bytes of the second byte, n + 2 byte, 2n + 2 byte,... Are read and sent to the voltage generator 13. In the final n-th time, the total θ bytes of the n-th byte, the 2n-th byte, the 3n-th byte,..., The n × θ-byte are read at a time and sent to the voltage generator 13 side. In this way, the serial / parallel converter 15 rearranges the m-byte serial data array latched together to form a θ × n parallel data array. The θ-stage voltage generator 13 functions as a digital / analog converter, and converts a predetermined number (θ pieces) of image data read from the serial / parallel converter 15 into signal voltages OUT1 to OUTθ, respectively. These signal voltages OUT1 to OUTθ are repeatedly supplied to the LCD panel 2 side a predetermined number of times (n times) via the θ-stage output buffer 14.
[0016]
FIG. 5 is a schematic circuit diagram showing a specific configuration of the LCD panel 2 shown in FIG. Parts corresponding to those of the LCD panel according to the previous embodiment shown in FIG. 1 are given corresponding reference numerals for easy understanding. As shown in FIG. 5, this LCD panel is arranged at the intersection of row-shaped scanning lines X, columnar signal lines Y divided into a plurality of (m) blocks, and scanning lines X and signal lines Y. Matrix-shaped pixels PXL. In the figure, only one block including m signal lines Y is shown. Further, a V shift register 21 is arranged on the left side of the periphery of the LCD panel so as to be connected to the scanning line X, and the pixels PXL are selected line by line. Further, a predetermined number (θ) in which a predetermined number (θ) of signal voltages OUT1, OUT2,..., OUTθ are arranged at regular intervals (n) in the upper periphery of the LCD panel 1 in one block. A switch group SW that can be simultaneously distributed to the signal line Y is provided. The individual switches SW are divided into θ groups represented by G1, G2,. The first group G1 includes a total of n switches SW including SW1, SW2, SW3,. Similarly, the second group G2 includes switches SW1 to SWn. Similarly, SW1, SW2, SW3,..., SWn are also included in the last group Gθ. OUT1 is supplied to each SW of G1, OUT2 is supplied to each SW of G2, and OUTθ is supplied to each SW of Gθ. First, SW1 belonging to the groups G1 to Gθ are turned on all at once, and OUT1 to OUTθ are sampled, respectively. As a result, OUT1 to OUTθ are written simultaneously to every n signal lines Y arranged. In the next round, all SW2s belonging to G1 to Gθ are in a conductive state, and OUT1 to OUTθ are sampled all at once on the signal lines Y arranged every n lines. Further, an H shift register 22 is provided at the upper periphery of the LCD panel, and the above-described opening / closing scanning of the switch SW is repeated a predetermined number of times (n times) to obtain a predetermined number (θ) of signal voltages and a predetermined number of times (n The signal voltages OUT1 to OUTθ are written to a plurality (m) of pixels PXL via a plurality (m) of signal lines Y equal to the product of the number of times. Further, the signal voltages OUT1 to OUTθ are written to all the selected pixels PXL by repeating this writing for each block.
[0017]
FIG. 6 is a timing chart showing various control signals supplied from the outside to the display device shown in FIGS. As shown in the figure, one horizontal period (1H) is defined by a horizontal synchronization signal HSYNC. A horizontal start pulse HST is input to the H shift register 22 on the LCD panel side. Since the H shift register 22 is provided for each block, an HST pulse corresponding to the number of blocks is input from the outside within 1H. The H shift register 22 sequentially transfers HST according to HCK and performs SW open / close scanning. On the other hand, the shift clock 1 is input to the m-stage shift register 11 on the driver 1 side from the outside. This is included in one HST period. The serial / parallel converter 15 receives a latch pulse in phase with the HST. Further, the shift clock 2 having the same phase as HCK is input to the serial / parallel converter 15. The shift clock 2 is used to divide m bytes of digital data n times by θ bytes.
[0018]
The operation of the display device shown in FIGS. 4 and 5 will be described in detail below with reference to the timing chart of FIG. For example, when full-color display is performed in accordance with the XGA standard, 3072 bytes of data are transferred during a period of 1H. Here, m = 768, n = 12, and θ = 64 are set. That is, m = n × θ. 3072 ÷ 768 = 4 is the number of blocks. When image data input from the outside is transferred by the shift register 11 for 768 bytes, it is latched by the serial / parallel converter 15. Furthermore, serial / parallel conversion is performed, and parallel data of θ = 64 bytes rearranged every n = 12 is obtained. The shift register 11 transfers the next data after the above-described latch. The 64-byte parallel data is output 12 times by the shift clock 2 during the next 768 data transfer. The LCD panel 2 inputs signal voltages OUT1 to OUT64 corresponding to 64-byte parallel data, and switches SW in synchronization with HCK. That is, 12 sets of 12 SWs are operated as 64 groups by 12 stages of H shift registers 22. By repeating this operation for four blocks, all 3072-byte digital data is written to the signal line Y of the LCD panel. In the case of the XGA standard in which data transfer is performed with a 95 MHz clock, the time for transferring 768 bytes of data is about 2.7 μs. During this time, since the 64-byte data is written in 12 times, the write time for one time is about 220 ns. Compared to the conventional writing period of only about 10 ns, the writing time is 20 times or more and sufficient writing is possible. In this embodiment, the driver 1 can be used in common for each block of the LCD panel 2.
[0019]
【The invention's effect】
As described above, according to the present invention, since the LCD panel can be driven by one driver, it is not necessary to connect thousands of wires as in the conventional case, and the mounting reliability can be improved. It is. In addition, since the signal voltages are written to the signal lines all at once, a sufficient writing time can be secured and a high-quality display can be realized. In addition, since the writing frequency to the signal line is reduced in the LCD panel, the power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a display device according to the present invention.
2 is a table for explaining the operation of a voltage generator incorporated in a driver of the display device shown in FIG.
FIG. 3 is a timing chart for explaining the operation of the display device shown in FIG. 1;
FIG. 4 is a block diagram showing a second embodiment of a display device according to the present invention.
5 is a circuit diagram showing a specific configuration of an LCD panel included in the display device shown in FIG. 4. FIG.
6 is a timing chart for explaining the operation of the display device shown in FIGS. 4 and 5. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Driver, 2 ... LCD panel, 11 ... Shift register, 12 ... Latch memory, 13 ... Voltage generator, 14 ... Output buffer, 15 ... Serial / parallel converter , 21 ... V shift register, 22 ... H shift register, X ... scanning line, Y ... signal line, PXL ... pixel

Claims (4)

A display device comprising a driver that converts digital image data into an analog signal voltage, and a panel that operates by the signal voltage and displays an image,
The panel includes a row-shaped scanning line, a column-shaped signal line, a matrix-shaped pixel arranged at the intersection of the two, a vertical scanning circuit that is connected to the scanning line and sequentially selects pixels for one row, A switch that is provided for each set of signal lines and applies a set of signal voltages to a set of signal lines at the same time, and a switch that is provided for each set is opened and closed in sequence, and signals are sent to pixels for a selected row. A horizontal scanning circuit for writing voltage,
The driver includes a shift register that sequentially transfers image data input from the outside, a latch memory that collectively collects one set of image data from the shift register, and one set of image data that has been captured. A digital / analog converter that converts the signal voltage to the panel and supplies it to the panel,
The driver is connected to the panel with wiring corresponding to a set of signal voltages,
The display device, wherein when the panel is writing a set of signal voltages, the driver transfers the next set of image data. A display device comprising a driver that converts digital image data into an analog signal voltage, and a panel that operates by the signal voltage and displays an image,
The panel includes a row-shaped scanning line, a column-shaped signal line, a matrix-shaped pixel arranged at an intersection of the two, a vertical scanning circuit that selects the pixel for each row by connecting to the scanning line, and a predetermined line A switch group capable of distributing a predetermined number of signal voltages to a predetermined number of signal lines arranged every fixed number, and a plurality determined by a product of the predetermined number and the predetermined number of times by repeating open / close scanning of the switch group a predetermined number of times A horizontal scanning circuit that writes a signal voltage to each of the pixels and performs this writing on all selected pixels,
The driver includes a shift register for sequentially transferring image data for one row input from the outside, and the plurality of image data corresponding to a part of the image data for one row from the shift register. A serial / parallel converter that rearranges a predetermined number every predetermined number and reads the predetermined number of times, and a digital / digital converter that converts the predetermined number of read image data into a signal voltage and repeatedly supplies the panel to the panel a predetermined number of times. An analog converter,
When the panel is writing a signal voltage to a plurality of pixels determined by the product of the predetermined number and the certain number of times, the driver transfers image data to be allocated to the next plurality of pixels. Display device. A driver that converts digital image data into an analog signal voltage and writes it to a panel pixel to display an image.
A shift register that sequentially transfers image data for one line input from the outside , and image data corresponding to a part of the image data for one line to be assigned to a plurality of pixels at once are fetched at regular intervals. A serial / parallel converter that sorts a predetermined number and reads it in a certain number of times,
A digital / analog converter that converts a predetermined number of read image data into signal voltages and supplies the panel to the panel repeatedly,
A driver for transferring image data to be assigned to a next plurality of pixels when the panel is writing a signal voltage to a plurality of pixels equal to a product of the predetermined number and the predetermined number of times. A row of scanning lines;
Column-shaped signal lines divided into multiple blocks,
Matrix-like pixels arranged at intersections of scanning lines and signal lines;
A vertical scanning circuit connected to the scanning line for selecting pixels line by line;
A switch group capable of simultaneously distributing a predetermined number of signal voltages in each block to a predetermined number of signal lines arranged at fixed intervals;
By repeating open / close scanning of the switch group a predetermined number of times, a signal voltage is written to a plurality of pixels via the plurality of signal lines equal to the product of the predetermined number and the predetermined number of times, and this writing is performed for each block. A horizontal scanning circuit for writing a signal voltage to all pixels selected repeatedly.

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