JP4047594B2 - Signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing circuit for sampling the digital video signal relates example, signal processing circuits for level conversion to a larger voltage amplitude while sampling the signal voltage of the digital video signal.
[0002]
[Prior art]
Active matrix liquid crystal display devices are light, thin and have low power consumption, and can display clear images with a resolution comparable to or higher than that of CRTs. Therefore, they are widely used as monitor displays for information equipment terminals and thin televisions. Yes. A typical active matrix liquid crystal display device includes a liquid crystal display panel that displays an image and a display control circuit that controls the operation of the liquid crystal display panel.
[0003]
The liquid crystal display panel includes a plurality of display pixels arranged in a matrix, a plurality of scanning lines arranged along the rows of the display pixels, a plurality of signal lines arranged along the columns of the display pixels, and these signals. A plurality of pixel switches are provided respectively near the intersections of the lines and the scanning lines. Each pixel switch is a thin film transistor using a semiconductor thin film such as amorphous silicon or polysilicon, and applies the potential of the corresponding signal line to the corresponding display pixel in response to the scanning signal from the corresponding scanning line. The display pixel has a structure in which a liquid crystal layer is sandwiched between a pixel electrode and a counter electrode, and the light transmittance of the liquid crystal layer is set by a signal line potential applied to the pixel electrode with respect to the counter electrode potential. The display control circuit is a scanning line driving circuit that sequentially supplies scanning signals to a plurality of scanning lines for each vertical scanning period, and a video signal is supplied to a plurality of signal lines for each horizontal scanning period in which the scanning signal is supplied to one scanning line. And a liquid crystal controller that controls operations of the scanning line driving circuit and the signal line driving circuit. The scanning line driving circuit and the signal line driving circuit are usually mounted on the end of the liquid crystal display panel as a driver IC chip.
[0004]
In recent years, instead of mounting the above-described driver IC chip, a scanning line driving circuit is used to reduce the manufacturing cost while relaxing the restrictions on the effective screen area depending on the area occupied by the connection terminal group with the external circuit of the liquid crystal display panel. Further, development of a liquid crystal display panel with a built-in drive circuit in which a signal line drive circuit is formed of, for example, a thin film transistor in the same manner as a pixel switch and is integrated with the liquid crystal display panel is progressing. The signal line driving circuit receives a digital video signal generated in series with respect to a plurality of signal lines from the liquid crystal controller and supplied to an external wiring terminal of the liquid crystal display panel, and a plurality of signals connected to the external wiring terminal via a bus wiring. The digital video signal is sequentially sampled using the sampling latch, and a plurality of signal lines are driven in parallel based on the sampling results.
[0005]
[Problems to be solved by the invention]
Incidentally, an external circuit such as a liquid crystal controller is generally constituted by an IC chip made of single crystal silicon and is driven with a voltage amplitude of about 3.3V. On the other hand, a signal line driving circuit composed of a thin film transistor using a semiconductor thin film such as polysilicon needs to be driven with a larger amplitude than that of an external circuit, for example, a voltage amplitude of about 5 V due to the problem of the threshold. . For this reason, it is necessary to convert the level of a digital video signal input with 3.3 V amplitude from an external circuit to 5 V amplitude.
Conventionally, various level conversion methods have been considered for this signal line driving circuit. When only a positive-phase digital video signal is supplied from the LCD controller to reduce the number of bus lines, for example, a level shifter using an inverter is inserted in the bus line near the external wiring terminal, and level conversion is performed by this level shifter. It is conceivable to distribute the digital video signal thus obtained to a plurality of sampling latches. However, in this method, the level shifter needs to shift the potential of the bus wiring having a large parasitic capacitance to near 5 V, which causes an increase in power consumption. When the voltage amplitude on the bus wiring is maintained at 3.3 V, for example, a plurality of inverters are arranged as level shifters between these sampling latches and the bus wiring. In this method, the signal line driver circuit may malfunction due to threshold variations that are difficult to avoid between these inverters. This malfunction can be prevented by adding a threshold cancel circuit in front of each inverter and preparing a reference voltage for the threshold cancel circuit, but this leads to an increase in circuit scale and power consumption.
[0006]
An object of the present invention is to provide a stable operation possible signal processing circuits without increasing the power consumption or circuit scale.
[0007]
[Means for Solving the Problems]
According to the present invention, a bus wiring for receiving a digital video signal and a data register for sequentially sampling and outputting the digital video signal on the bus wiring in parallel are provided. Each of the sampling latches includes a plurality of capacitor elements and a plurality of capacitor elements connected in parallel to each other to convert a signal voltage from a corresponding bit line of the bus wiring into a plurality of capacitor elements. signal processing including a connection control circuit for setting the output state of outputting a plurality of capacitive elements connected to the signal voltage obtained by level added to the series of a plurality of capacitive elements following the sampling state and the sample state is held respectively A circuit is provided.
[0009]
In this signal processing circuits, the sample state and the connection control circuit of each sampling latches to hold respectively a signal voltage from the corresponding bit line by connecting bus lines several capacitive elements in parallel to a plurality of capacitive elements Following sample state to set the output state of outputting a plurality of capacitive elements connected to the signal voltage obtained by level added to the series of a plurality of capacitive elements. In this case, since it is not necessary to drive a bus wiring having a large parasitic capacitance for level conversion, an increase in power consumption can be prevented. Further, since the data register also performs level conversion and sequentially samples the video signals on the bus wiring and outputs them in parallel, an increase in circuit scale can be prevented. Furthermore, even if an inverter circuit is provided for output from the data register, the above-described configuration does not require level conversion of the signal voltage input by the inverter circuit at a level close to its own threshold value. Works without receiving. Therefore, the operation of the signal processing circuit can be stabilized.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.
[0011]
FIG. 1 shows a schematic structure of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel 1 in which a plurality of display pixels PX are arranged in a display region DS, and a liquid crystal composed of an IC chip arranged on an external drive substrate such as a PCB or FPC independent of the liquid crystal display panel 1. A controller 2 is provided. The liquid crystal display panel 1 has a structure in which, for example, the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT.
[0012]
The array substrate AR includes a plurality of pixel electrodes PE arranged in a matrix on a glass substrate, a plurality of scanning lines Y (Y1 to Ym) formed along a row of the plurality of pixel electrodes PE, and a plurality of pixel electrodes PE. A plurality of signal lines X (X1 to Xn), signal lines X1 to Xn, and scanning lines Y1 to Ym, which are formed along the column, are arranged adjacent to the intersections of the scanning lines Y1 to Ym. In response, the video signal voltage from the corresponding signal line X is captured and supplied to the corresponding pixel electrode PE, the pixel switch W, the scanning line driving circuit 3 for driving the scanning lines Y1 to Ym, and the signal for driving the signal lines X1 to Xn. A line driving circuit 4 is included. Each pixel switch W is composed of an N channel polysilicon thin film transistor (TFT), and the scanning line driving circuit 3 and the signal line driving circuit 4 are formed of a plurality of N and P channel polycrystals formed on the glass substrate integrally with the pixel switch W. It is composed of a combination of silicon thin film transistors. The counter substrate CT includes a single counter electrode and a color filter which are arranged to face the plurality of pixel electrodes PE and set to a common potential. Each display pixel PX includes a pixel electrode PE, a counter electrode, and a liquid crystal material of a liquid crystal layer LQ sandwiched therebetween.
[0013]
The liquid crystal controller 2 outputs, for example, a 4-bit digital video signal DATA (D0 to D3) together with various control signals synchronized with the video signal DATA. These control signals include a horizontal scanning control signal YCT such as a vertical start pulse and a vertical clock signal, and a horizontal scanning control signal such as a horizontal start pulse STH, a horizontal clock signal CKH, a latch signal LT, and a load signal LOAD. The vertical start pulse and the vertical clock signal are supplied to the scanning line drive circuit 3 as the vertical scanning control signal YCT, and the digital video signal DATA, horizontal start pulse STH, horizontal clock signal CKH, latch signal LT, and load signal LOAD are horizontal scanning control signals. Is supplied to the signal line driving circuit 4.
[0014]
The horizontal start signal STH is a pulse generated every horizontal scanning period (1H), the horizontal clock signal CKH is a pulse generated by the number of signal lines in each horizontal scanning period, and the vertical start signal is one vertical scanning period. The vertical clock signal CHV is generated every number of scanning lines in each vertical scanning period, and the latch signal LT latches the sample result of the digital video signal DATA every horizontal scanning period. The load signal LOAD is a signal for permitting parallel driving of the plurality of signal lines X every horizontal scanning period. The liquid crystal controller 2 has a power supply circuit that generates the gradation reference voltage VREF. This gradation reference voltage VREF is supplied to the signal line drive circuit 4.
[0015]
The scanning line driving circuit 3 sequentially selects the plurality of scanning lines Y1 to Ym by shifting the vertical start pulse in synchronization with the vertical clock signal, and outputs a scanning signal for making the pixel switch W conductive to the selected scanning line. The signal line driving circuit 4 sequentially selects the plurality of signal lines X1 to Xn by shifting the horizontal start signal STH in synchronization with the horizontal clock signal CKH, and the video supplied via the bus wiring DB on the array substrate AR. The signal lines X1 to Xn are driven in parallel based on the signal DATA.
[0016]
The signal line drive circuit 4 includes a shift register 5, a data register 6, a D / A converter 7, and an output buffer circuit 8. The shift register 5 sequentially generates sampling signals S1 to Sn by shifting the horizontal start signal STH in synchronization with the horizontal clock signal CKH. The data register 6 sequentially samples the digital video signal DATA from the bus wiring DB by the number of signal lines under the control of the sampling signals S1 to Sn, and holds the digital video signal DATA under the control of the latch signal LT. The D / A converter 7 is composed of an addition type capacitor DAC based on the gradation reference voltage VREF, and sequentially applies a gradation reference voltage VREF corresponding to the sampled digital video signal DATA to the corresponding capacitor to obtain a desired gradation. Generate voltage. Thus, digital / analog conversion is performed by selectively outputting these gradation voltages corresponding to the video signals DATA output from the data register 6 in parallel. In addition to the above configuration, the D / A converter 7 is a resistive DAC that generates a predetermined number of gradation voltages by, for example, dividing the gradation reference voltage VREF by resistance based on the corresponding digital video signal DATA. It can also be configured. The output buffer circuit 8 outputs the analog video signal voltage from the D / A converter 7 to the plurality of signal lines X1 to Xn in parallel under the control of the load signal.
[0017]
FIG. 2 shows a detailed circuit configuration of the data register 6. In this embodiment, the data register 6 is composed of n latch circuits 9 assigned to the signal lines X1 to Xn because the digital video signal DATA for the signal line X is serially input sequentially in the horizontal scanning period. Is done. The sampling signals S1 to Sn are supplied to the latch circuits 9 respectively, and the latch signal LT is supplied to the latch circuits 9 in common. Each latch circuit 9 includes four sampling latches 10 for sampling the 4-bit video signal DATA in bit units.
[0018]
Each sampling latch 10 connects the first and second capacitive elements C1 and C2 and the capacitive elements C1 and C2 in parallel to each other corresponding to the bit lines D0 to D3 of the bus wiring DB, for example, from the bit line D0. output state of outputting a sample state and the signal voltage the following a sample state the capacitor C1, C2 connected in series to level added to each hold a signal voltage in the capacitor C1, C2 from the capacitor elements C1, C2 Including a connection control circuit SWC for setting and an inverter circuit INV operated by a signal voltage output from the capacitive elements C1 and C2 in the output state. Here, the inverter circuit INV is configured by one inverter, but a configuration in which a plurality of inverter circuits are connected in cascade may be employed.
[0019]
The connection control circuit SWC is controlled by one of the sample signals S1 to Sn, for example, the first to third switch elements SW1, SW2, SW3, which are controlled by the sample signal S1 and conducted in the sample state, and the latch signal LT, and in the output state. It includes fourth and fifth switch elements SW4 and SW5 that are conductive. The capacitive element C2 is connected at one end to the bit line D0 via the switch element SW1 and at the other end to the reference potential terminal GND. The capacitive element C1 is connected at one end to the bit line D0 via the switch elements SW1 and SW2, and further connected to the input terminal of the inverter circuit INV via the switch element SW5, and at the other end to the reference potential via the switch element SW3. It is connected to the terminal GND and further connected to one end of the above-described capacitive element C2 via the switch element SW4.
[0020]
Next, the operation of the sampling latch 10 will be described. For example, when the sample signal S1 is output from the shift register 5, the switch elements SW1 to SW5 are in the sample state shown in FIG. That is, only the switch elements SW1 to SW3 are turned on, the signal voltage from the bit line D0 of the bus line DB is applied to one end of the capacitive element C2 via the switch SW1, and the capacitive element C1 via the switches SW1 and SW2. Applied to one end of the. At this time, since the switch SW3 connects the other end of the capacitive element C1 to the reference power supply terminal GND, the capacitive elements C1 and C2 are in parallel with each other. Assuming that the signal voltage from the bit line D0 is 3.3V, the capacitive elements C1 and C2 each store electric charges up to 3.3V. When the switch elements SW1 to SW3 become non-conductive as the output of the sample signal S1 stops, the capacitive elements C1 and C2 hold 3.3V and are electrically floating.
[0021]
Subsequently, when the latch signal LT is output from the liquid crystal controller 2, the switch elements SW1 to SW5 are in the output state shown in FIG. That is, only the switch elements SW4 and SW5 are conducted, and the capacitive elements C1 and C2 are in series with each other. As a result, the level of the 3.3V signal voltage held in each of the capacitive elements C1 and C2 is added and output to the inverter circuit INV.
[0022]
Incidentally, when the signal voltage is 0V, the signal voltage input to the inverter circuit INV remains 0V even when the switch elements SW1 to SW5 transition from the sample state to the output state. Moreover, if larger than the capacitance of the capacitor C1 a capacitance of the capacitor C2, it is possible to shift more have high levels resulting signal voltage input to the inverter circuit INV level adder.
[0023]
FIG. 4 shows a configuration example of the switch elements SW1 to SW5. Each of the switch elements SW1 to SW5 can be composed of a transfer gate composed of a pair of P and N channel thin film transistors. However, since only the switch element SW1 is for supplying a reference potential, a single N channel thin film transistor is used here. It consists of.
[0024]
In this embodiment, the display device includes a signal processing circuit including at least a bus line DB that receives a digital video signal and a data register 6 that sequentially samples and outputs the digital video signal DATA on the bus line DB in parallel. The data register 6 includes a plurality of sampling latches 10 for level-converting the signal voltage of the digital video signal in bit units, and the connection control circuit SWC of each sampling latch 10 connects the capacitive elements C1 and C2 in parallel to connect the bus wiring DB signal voltage capacitive elements C1 to from the corresponding bit line, C2 the sample state and the sample state is followed by the capacitive element C1, C2 and connected in series level summed signal voltage the capacitor C1 were to be held respectively, Sets the output state output from C2. In this case, since it is not necessary to drive the bus wiring DB having a large parasitic capacitance for level conversion, an increase in power consumption can be prevented. Further, since the data register 6 also performs level conversion and sequentially samples the video signal DATA on the bus wiring DB and outputs it in parallel, an increase in circuit scale can be prevented. Further, even if the inverter circuit INV is provided for output from the data register 6, the above-described configuration does not require level conversion of the signal voltage input by the inverter circuit INV at a level close to its own threshold value. Operates without being affected by. Therefore, the operation of the signal processing circuit can be stabilized.
[0025]
In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.
[0026]
The sampling latch 10 shown in FIG. 2 may be modified as shown in FIG. 5, for example. In FIG. 5, the third capacitor element C3 is provided, and the connection control circuit SWC further includes sixth and seventh switch elements SW6 and SW7 that conduct in the sample state, and an eighth switch element SW8 that conducts in the output state. Bit line D0 of bus line DB is connected to reference potential terminal GND via switch elements SW1 and SW6 and capacitive element C3, and the other end of capacitive element C2 is connected to reference potential terminal GND via switch element SW7 and further switched. It is connected to the reference potential terminal GND through the element SW8 and the capacitive element C3. Thus, with the configuration in which the capacitive element C3 is added, it is possible to shift the level of a signal having a low voltage amplitude.
[0027]
In the above-described embodiment, the liquid crystal display device has been described. However, the present invention can also be applied to an organic EL display device and the like.
[0028]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a signal processing circuit that can operate stably without increasing power consumption or circuit scale, and a display device including the signal processing circuit.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic structure of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a detailed circuit configuration of a data register shown in FIG. 1;
FIG. 3 is a diagram for explaining an operation when the connection control circuit shown in FIG. 2 transitions from a sample state to an output state;
4 is a diagram showing a configuration example of first to fifth switch elements shown in FIG. 2. FIG.
FIG. 5 is a view showing a modification of the sampling latch shown in FIG. 2;
[Explanation of symbols]
4 ... signal line drive circuit 6 ... data register 10 ... sampling latches C1, C2 ... capacitive element DB ... bus wiring SWC ... connection control circuit PX ... display pixel X ... signal line

Claims (8)

A bus line for receiving a digital video signal and a data register for sequentially sampling and outputting the digital video signal on the bus line in parallel, the data register level-converting the signal voltage of the digital video signal in units of bits. A plurality of sampling latches, and each sampling latch connects a plurality of capacitive elements and the plurality of capacitive elements in parallel to hold the signal voltage from the corresponding bit line of the bus wiring in the plurality of capacitive elements, respectively. and wherein the sample state and subsequently to the sample state includes a connection control circuit for setting the output state of outputting the level summed allowed signal voltage by connecting the plurality of capacitive elements in series from said plurality of capacitive elements Signal processing circuit.   The signal processing circuit according to claim 1, wherein the sampling latch includes an inverter circuit that operates by a signal voltage output from the plurality of capacitive elements in the output state.   The plurality of capacitive elements include first and second capacitive elements, and the connection control circuit includes first to third switch elements that are conductive in the sample state and fourth and fifth switch elements that are conductive in the output state. The second capacitive element is connected to the bit line through the first switch element at one end and to the reference potential terminal at the other end, and the first capacitive element is connected to the first and second switches at one end. Connected to the bit line via an element, further connected to the input terminal of the inverter circuit via the fifth switch element, and connected to the reference potential terminal via the third switch element at the other end. The signal processing circuit according to claim 2, wherein the signal processing circuit is connected to the one end of the second capacitive element via a fourth switch element.   Each of the first, second, fourth, and fifth switch elements is a transfer gate including a pair of P and N channel thin film transistors, and the third switch element is a single N channel thin film transistor. The signal processing circuit according to claim 3.   The plurality of capacitive elements further include a third capacitive element, the connection control circuit includes sixth and seventh switch elements that conduct in the sample state and an eighth switch element that conducts in the output state, and the bit line includes the bit line The first and sixth switch elements and the third capacitor element are connected to the reference potential terminal, and the other end of the second capacitor element is connected to the reference potential terminal via the seventh switch element. The signal processing circuit according to claim 3, wherein the signal processing circuit is connected to the reference potential terminal via an eighth switch element and the third capacitor element.   2. The signal processing circuit according to claim 1, further comprising a D / A converter for converting digital video signals output in parallel from the data register into analog gradation voltages.   A plurality of display pixel portions; a plurality of signal lines connected to the plurality of display pixel portions; and a signal line drive circuit that drives the plurality of signal lines in response to a video signal, the signal line drive circuit A display device comprising the signal processing circuit according to claim 1. A bus line for receiving a digital video signal and a data register for sequentially sampling and outputting the digital video signal on the bus line in parallel, the data register level-converting the signal voltage of the digital video signal in units of bits. A plurality of sampling latches, and each sampling latch connects a plurality of capacitive elements and the plurality of capacitive elements in parallel to hold the signal voltage from the corresponding bit line of the bus wiring in the plurality of capacitive elements, respectively. sample state and subsequently to the sample state to include a connection control circuit for setting the output state of outputting from one of said plurality of capacitive elements connected in series the signal voltage is les Berushifuto with the plurality of capacitive elements A characteristic signal processing circuit.

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