JP4664466B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device, and more particularly to a display device that can reduce the number of connections with an external circuit.
[0002]
[Prior art]
As a driving circuit for a display device, for example, a liquid crystal display device using amorphous silicon TFTs, a tape carrier package (TCP) in which a signal line driving IC and a gate line driving IC are mounted on a flexible wiring board is used. ing. This TCP is connected to electrodes provided on an array substrate having pixels arranged in a matrix, and drives the pixels.
[0003]
On the other hand, in a liquid crystal display device using a polycrystalline silicon TFT, a part of a signal line driving circuit as a driving circuit and a gate line driving circuit can be integrally formed on an array substrate. In this case, a part of the signal line driving circuit, for example, a digital / analog conversion circuit (DAC) is also provided outside the substrate. However, in comparison with a liquid crystal display device using amorphous silicon TFTs, connection wiring to the array substrate is not necessary. The number can be greatly reduced.
[0004]
[Problems to be solved by the invention]
In a liquid crystal display device using amorphous silicon TFTs, connection lines for inputting video signals from TCP to the signal lines on the array substrate are necessary, but the number of connection lines increases as the pixels become higher definition. It is difficult to ensure a sufficient pitch between these connection wirings.
[0005]
On the other hand, in a liquid crystal display device using a polycrystalline silicon TFT, a signal line driving circuit is further integrally formed on the substrate in addition to the gate line driving circuit. The length of the rotated wiring becomes long, and there is a possibility that the signal is deteriorated to cause a display defect.
[0006]
The present invention has been made in view of the above-described problems, and an object of the present invention is to enable high-definition of pixels and to prevent display defects even on a large display screen. It is to provide a display device.
[0007]
[Means for Solving the Problems]
According to this embodiment,
A plurality of gate lines and a plurality of signal lines arranged orthogonally to each other on the substrate; a pixel transistor disposed at each intersection of the gate line and the signal line; and a pixel electrode connected to each pixel transistor; The input digital signal is converted into an analog signal, and the signal line is divided into a plurality of signal line groups each including a predetermined number of signal lines, and an analog signal corresponding to each signal line group is serially output. A drive circuit; a selection unit that sequentially distributes the analog signal from the drive circuit to a corresponding signal line of each of the signal line groups; and a control unit that controls the order of distribution of the analog signal to the signal line by the selection unit. The control means comprises four vertical scanning periods or longer Multiple multiple vertical scans All the pixel transistors connected on each signal line of the plurality of signal lines within a period But Each horizontal scanning period In Drive with one polarity based on a given potential at the same timing Control the selection means to be The first pixel transistor group selected at the first timing within one horizontal scanning period is driven with the first polarity, and the second pixel transistor selected at the second timing following the first timing within one horizontal scanning period. When the group is driven with the second polarity opposite to the first polarity, when the driving potential of the first pixel transistor group fluctuates as the second pixel transistor group is driven, the driving of the first pixel transistor group is performed. The reference potential is shifted by a predetermined amount in accordance with the amount of potential variation, and an offset potential in a direction opposite to the direction of variation of the driving potential is applied to the first pixel transistor group, and the driving potential is applied to the second pixel transistor group. A display device is provided that provides an offset potential in the same direction as the fluctuation direction.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a display device of the present invention, that is, a light transmission type liquid crystal display device having an effective display area of 15 inches diagonally using a polycrystalline silicon TFT as a pixel TFT will be described with reference to the drawings.
[0009]
As shown in FIG. 1, the liquid crystal display device 1 includes an array substrate 100, a counter substrate 200 including a counter electrode 210 disposed to face the array substrate 100 at a predetermined interval, and these array substrates. 100 and a counter substrate 200, and a liquid crystal layer 300 disposed via an alignment film (not shown). The array substrate 100 and the counter substrate 200 are bonded together by a sealing material 400 arranged around the periphery.
[0010]
The array substrate 100 includes a plurality of gate lines Y extending along the row direction, a plurality of signal lines X extending along the column direction, and intersections of the gate lines Y and the signal lines X. A pixel thin film transistor as a switching element, that is, a pixel TFT 110, and a pixel electrode 120 provided corresponding to each pixel surrounded by the gate line Y and the signal line X are provided.
[0011]
The pixel TFT 110 is a polycrystalline silicon TFT having a polycrystalline silicon film as a semiconductor layer. The gate electrode of the pixel TFT 110 is connected to the gate line Y, and the source electrode is connected to the signal line X. The drain electrode of the pixel TFT 110 is connected to the pixel electrode 120 and one electrode constituting the auxiliary capacitance element 130 in parallel with the pixel electrode 120.
[0012]
A gate line driving circuit 150 that functions as a gate line driving unit that outputs a driving signal for driving the gate line Y is integrally formed on the array substrate 100 in the same process as the pixel TFT 110.
[0013]
The signal line drive circuit unit 160 that outputs a drive signal for driving the signal line X is mounted with a signal line drive IC 511 on a flexible wiring board, and is electrically connected to the array substrate 100 TCP 500-1, 500. ,..., 500-6, and a selection circuit 170 that functions as selection means formed on the array substrate 100 by the same process as the pixel TFT 110.
[0014]
The TCPs 500-1 to 6 are arranged on one side of the array substrate 100 and connected to a PCB substrate 600 on which circuit components as external circuit substrates are mounted. The PCB substrate 600 is mounted with a control IC, a power supply circuit, and the like that output various control signals and data signals synchronized with the control signals based on a reference clock signal and a digital data signal input from the outside. .
[0015]
As shown in FIG. 2, the TCP 500 -N is connected to the PCB-side pad 513 connected to the connection terminal on the connection wiring formed on the PCB substrate 600 and the connection terminal on the connection wiring formed on the array substrate 100. Array side pads 515 and various wirings for connecting these pads. The PCB-side pad 513 and the array-side pad 515 are electrically and mechanically connected to the PCB substrate 600 and the array substrate 100, respectively, via an anisotropic conductive film (ACF).
[0016]
The signal line driving IC 511 of the signal line driving circuit unit 160 outputs a data signal as an analog video signal based on an input signal from the PCB substrate 600.
[0017]
That is, as shown in FIG. 3, the signal line driving IC 511 includes a shift register 521, a data register 523, a D / A converter 525, and the like. A clock signal and a control signal are input to the shift register 521 from the PCB substrate 600 side. A data signal is input to the data register 523 from the PCB substrate 600 side. The D / A converter 525 receives a reference signal from the PCB substrate 600 side, and converts the input data signal into an analog video signal.
[0018]
Each analog video signal output from the TCP-N signal line driving IC 511 includes an analog video signal corresponding to two signal lines for each horizontal scanning period, which is output in time series, and this is the array substrate 100. The signal is input to the selection circuit 170 of the signal line driver circuit unit 160 formed above.
[0019]
The selection circuit 170 is connected to the wiring from the signal line driving IC 511, and is connected to output terminals OUT1, OUT2,... To which each serial analog video signal is output from the signal line driving IC 511, and one end of the signal lines X1, X2,. .. Are provided for selectively connecting the provided input terminals 1A and 1B, 2A and 2B..., So that two horizontal scanning periods from the signal line driving IC 511 are provided. Serial analog video signals corresponding to adjacent signal lines are sequentially distributed to two adjacent signal lines as will be described later.
[0020]
In this embodiment, the number of output terminals OUT is half the number of signal lines X, and drive signals are sequentially output from one output terminal to two signal lines in the first half and the second half of one horizontal scanning period. ing. If the number of connections is further reduced, the number of output terminals OUT can be reduced to 1/3, 1/4 of the number of signal lines X, and the like.
[0021]
For example, the switch SW1 connects the output terminal OUT1 and the input terminal 1A of the signal line X1 at the timing of the first half or the second half within one horizontal scanning period based on the switch signal. The switch SW2 connects the output terminal OUT1 and the input terminal 1B of the signal line X2 at the timing of the first half or the second half within one horizontal scanning period based on the switch signal.
[0022]
The switch SW3 connects the output terminal OUT2 and the input terminal 2A of the signal line X3 at the first half or second half timing within one horizontal scanning period based on the switch signal. The switch SW4 connects the output terminal OUT2 and the input terminal 2B of the signal line X4 at the first half or second half timing within one horizontal scanning period based on the switch signal.
[0023]
Each switch SW connects the output terminal OUT and the input terminal of the signal line X when the switch signal is ON, and disconnects the output terminal OUT and the input terminal when the switch signal is OFF.
[0024]
Each switch that turns ON / OFF the connection between one output terminal and the input terminals of the two signal lines does not turn ON at the same time within one horizontal scanning period. It is controlled by a switch signal that turns off.
[0025]
For example, the switch SW1 that connects the output terminal OUT1 and the input terminal 1A of the signal line X1 is ON / OFF controlled based on a control signal that is turned on in the first half of one horizontal scanning period and turned off in the second half. At this time, the switch SW2 that connects the output terminal OUT1 and the input terminal 1B of the signal line X2 is ON / OFF controlled based on a control signal that is turned off in the first half of one horizontal scanning period and turned on in the second half. That is, in the first half of one horizontal scanning period, the output terminal OUT1 is connected to the input terminal 1A, and the analog signal from the output terminal OUT1 is written to the signal line X1. In the second half of one horizontal scanning period, the output terminal OUT1 is connected to the input terminal 1B, and an analog signal from the output terminal OUT1 is written to the signal line X2. At this time, analog signals having different polarities are written into the signal lines X1 and X2 using the voltage applied to the counter electrode 210 as a reference voltage.
[0026]
In addition, each switch for turning on / off the connection between two different output terminals and the input terminals of two signal lines adjacent to each other is simultaneously turned on and off at a predetermined timing within one horizontal scanning period. It is controlled by a switch signal.
[0027]
For example, the switch SW2 that connects the output terminal OUT1 and the input terminal 1B of the signal line X2 is ON / OFF controlled based on a control signal that is turned on in the first half of one horizontal scanning period and turned off in the second half. At this time, the switch SW3 that connects the output terminal OUT2 and the input terminal 2A of the signal line X3 is ON / OFF controlled based on a control signal that is turned on in the first half of one horizontal scanning period and turned off in the second half. That is, in the first half of one horizontal scanning period, the output terminal OUT1 is connected to the input terminal 1B, and the analog signal from the output terminal OUT1 is written to the signal line X2. At the same time, the output terminal OUT2 is connected to the input terminal 2A, and the analog signal from the output terminal OUT2 is written to the signal line X3. At this time, analog signals having different polarities are written into the signal lines X2 and X3 using the voltage applied to the counter electrode 210 as a reference voltage.
[0028]
In this way, the gate line driving circuit is integrally formed on the substrate, the signal line driving circuit is integrally formed on the substrate, and the signal line driving IC mounted on the TCP is configured. The switch of the selection circuit sequentially outputs drive signals to a plurality of signal lines within one horizontal scanning period, so that the number of connection wirings formed on the array substrate is equal to the number of signal lines even if the pixels are made high definition. Therefore, the pitch between the connection wires can be sufficiently secured.
[0029]
Further, compared to the case where all of the gate line driving circuit and the signal line driving circuit are formed on the substrate, it is possible to prevent the wiring length made of the thin film on the array substrate from being increased, and thereby the data It is possible to prevent deterioration of the signal or video signal and to prevent an increase in manufacturing cost.
[0030]
Next, an example of a method for driving each signal line X, that is, a method for writing an analog signal from each signal line to each pixel will be described.
[0031]
In this embodiment, as shown in FIG. 3, two signal lines can be connected to one output terminal, and the gate line Y1, all signal lines X1, X2, X3, X4. The pixel electrodes connected via the pixel transistors arranged at the intersection with the pixel 11, the pixel 12, the pixel 13, the pixel 14... Constitute one line, and the signal line X 1 and all the gate lines Y 1, Y 2. Pixel electrodes connected via pixel transistors arranged at the intersections with... Are pixel 11, pixel 21. The signal lines X1, X2, X3, X4, X5, X6,... Are connected to the red pixel R1, the green pixel G1, the blue pixels B1, R2, G2, B2,.
[0032]
In this embodiment, the most preferred analog signal writing method is:
(1) In at least four vertical scanning periods (that is, four frames), pixels connected on all signal lines (that is, pixel electrodes connected via pixel transistors) are respectively sent to the same timing (one horizontal scanning period). Including driving in the first half)
(2) The case where all the pixels are driven with only one polarity using the applied voltage of the counter electrode as a reference voltage at the same timing (for example, the first half) within one horizontal scanning period is included.
The reasons (1) and (2) are satisfied at the same time.
[0033]
In the case of driving with the above-described configuration, for example, the signal line X1 in which a predetermined analog signal is written in the first half of one horizontal scanning period is when the analog signal is written to the signal line X2 adjacent in the second half of one horizontal scanning period. In addition, with the potential displacement of the signal line X2, the potential of the signal line X1 changes due to the coupling capacitance between the signal lines. As a result, the signal line X1 may fluctuate to a potential different from the potential based on the analog video signal to be originally written, which may cause a problem in display.
[0034]
Therefore, as in the reason (1), by dispersing the pixels driven at the same timing within one horizontal period, it is possible to disperse the pixels in which the potential variation occurs temporally or spatially. It is possible to make it difficult to visually recognize the gradation variation of the display screen.
[0035]
Further, as in the reason (2), when all the pixels are always driven with one polarity, for example, positive polarity when selected in the same timing of one horizontal scanning period, for example, the first half, from all output terminals The output analog signal has positive polarity in the first half of one horizontal scanning period and negative polarity in the second half of one horizontal scanning period, so that driving power can be reduced.
[0036]
Further, in this most preferable analog signal writing method, as described in the reason (1), the potential of the signal line written in the first half should be originally written in accordance with the potential displacement of the signal line written in the second half. In order to prevent the potential from changing to a potential different from the displacement based on the analog signal, the following control is performed.
[0037]
For example, when a uniform black screen is displayed by applying a voltage, if the common potential is 5V, a voltage of 9V is applied on the positive side and 1V is applied on the negative side. At this time, after the potential of 9V is written to the signal line X1, the potential of 1V is written to the adjacent signal line X2, but the potential of the signal line X1 approaches 5V due to the potential fluctuation of the signal line X2. Will change direction. That is, when the black level is changed and the fluctuation is large, stripes having different gradations can be seen in the vertical direction, and the function as a display device is seriously hindered.
[0038]
Specifically, as shown in FIG. 4, a switch signal that is turned on in the first half of one horizontal scanning period and turned off in the second half is input to the switch SW1, and turned off in the first half of one horizontal scanning period. switch signal to oN is input to the second half. The output terminal OUT1 is connected to the input terminal 1A of the signal line X1 in the first half of one horizontal scanning period, and writes a positive polarity analog signal. The output terminal OUT1 is connected to the input terminal 1B of the signal line X2 in the second half of one horizontal scanning period, and writes a negative analog signal.
[0039]
At this time, according to the first driving method as described above, a positive video signal is written to the pixels 11 connected to the signal line X1 in the first half of one horizontal scanning period, and the pixels connected to the signal line X2 are connected. 12, a negative video signal is written in the latter half of one horizontal scanning period.
[0040]
At this time, the potential written in the first half of one horizontal scanning period varies due to the influence of the writing potential of the adjacent pixel. That is, in the pixel 11, due to the influence of the potential being written in the pixel 12, the voltage drops from 9V at the time of writing to, for example, 8V.
[0041]
That is, in the first half of one horizontal scanning period, the potential written in the pixel 11 is 9 V, and a potential difference of +4 V is generated between the common potential (5 V). On the other hand, in the second half of one horizontal scanning period, a potential difference of −4V is generated between the pixel 12 and the common potential (5V) because the potential of 1V is written in the pixel 12. At the same time, the potential written in the pixel 11 varies by −ΔV, for example, −1V due to the influence of the potential written in the pixel 12, and becomes 8V, so that the potential difference from the common potential (5V) becomes + 3V. It will fluctuate. For this reason, a potential difference occurs between the pixel 11 and the pixel 12 in the latter half of one horizontal scanning period, and the black of the pixel 11 becomes light.
[0042]
As described above, the potential written in the first half of one horizontal scanning period shifts in a direction close to the common potential (5 V) due to the influence of the potential written in the second half of one horizontal scanning period, and a display defect occurs.
[0043]
For this reason, in this most preferred analog signal writing method, control is performed so as to disperse the influence of this potential fluctuation.
[0044]
That is, according to the second driving method, a positive video signal is written to the pixels 11 connected to the signal line X1 in the first half of one horizontal scanning period, and 1 to the pixels 12 connected to the signal line X2. A negative video signal is written in the second half of the horizontal scanning period.
[0045]
In the first half of one horizontal scanning period, the potential written in the pixel 11 is offset to 9.5 V in consideration of the fluctuation amount ΔV of the driving potential of the pixel 11. The common potential at this time is shifted by +0.5 V corresponding to + ΔV / 2 from the normal potential (5 V) to 5.5 V. For this reason, a potential difference of +4 V is generated between the potential (9.5 V) written in the pixel 11 and the shifted common potential (5.5 V).
[0046]
On the other hand, in the second half of one horizontal scanning period, the fluctuation amount ΔV of the drive potential of the pixel 11 is taken into consideration and the offset is 0.5V. At this time, the common potential is shifted from the normal potential (5V) by −0.5V corresponding to −ΔV / 2 to 4.5V. For this reason, a potential difference of −4 V is generated between the potential written to the pixel 12 (0.5 V) and the shifted common potential (4.5 V). At the same time, the potential written to the pixel 11 is changed by −ΔV, that is, −1V due to the influence of the potential written to the pixel 12, and becomes 8.5V, which is the common potential (4.5V). Can be maintained at + 4V.
[0047]
For this reason, the pixel 11 and the pixel 12 can apply a driving potential that should be originally written in the latter half of one horizontal scanning period, and can display black on the entire screen with a uniform density.
[0048]
Here, the V-line inversion driving method will be described as an example as the first embodiment. In this V line inversion driving method, the polarity of the analog signal written to all the pixels is inverted every vertical scanning period (one frame). Analog signals written to all pixels connected on one signal line have the same polarity, and analog signals written to adjacent signal lines are inverted in polarity.
[0049]
Here, as shown in the second driving method of FIG. 4, for example, signal lines X1 (pixel column R1) and X2 (pixel column) respectively connected to the input terminal 1A and the input terminal 1B in the first half and the second half of one horizontal scanning period. A case where an analog signal is written to G1) will be described.
[0050]
In one line of the first frame (first vertical scanning period), a switch signal that is turned on in the first half of one horizontal scanning period 1H and turned off in the second half is input to the switch SW1. Thereby, the output terminal OUT1 is connected to the input terminal 1A of the signal line X1 in the first half of one horizontal scanning period. Then, a positive analog signal higher than the reference potential is written to the corresponding pixel 11 (R1).
[0051]
At this time, for example, the reference potential is shifted from 5 V by a predetermined amount in consideration of the fluctuation amount of the drive potential of the pixel 11. For example, when the fluctuation amount ΔV of the driving potential of the pixel 11 is set to −1V, the reference potential is shifted by + ΔV / 2 = 0.5V to 5.5V. Further, the drive potential of the pixel 11 (R1) is offset by a predetermined amount in consideration of the variation amount ΔV. For example, when the fluctuation amount ΔV is set to −1V, the reference potential is offset by + ΔV / 2 = 0.5V, and when the normal driving potential is 9V, it is set to 9.5V.
[0052]
On the other hand, a switch signal that is turned off in the first half of one horizontal scanning period 1H and turned on in the second half is input to the switch SW2. Thereby, the output terminal OUT1 is connected to the input terminal 1B of the signal line X2 in the second half of one horizontal scanning period. Then, with the analog signal held in the signal X1, a negative analog signal lower than the reference potential is written to the corresponding pixel 12 (G1).
[0053]
At this time, for example, the reference voltage is shifted by a predetermined amount from 5 V in consideration of the fluctuation amount of the drive potential of the pixel 11. For example, when the fluctuation amount ΔV of the driving potential of the pixel 11 is set to −1V, the reference potential is shifted by −ΔV / 2 = 0.5V to 4.5V. Further, the drive potential of the pixel 11 (R1) is offset by a predetermined amount in consideration of the variation amount ΔV. For example, when the fluctuation amount ΔV is set to −1V, the reference potential is offset by −ΔV / 2 = 0.5V, and the normal driving potential is set to 1V.
[0054]
Similarly, the positive polarity analog signal is written to the pixel row R1 in the first half of one horizontal scanning period 1H and the negative polarity analog signal is written to the pixel row G1 in the latter half of the first and second lines of the first frame. At this time as well, similarly, the control potential is controlled in consideration of the fluctuation amount of the driving potential of the pixel written in the first half of one horizontal scanning period, the reference potential is shifted by a predetermined amount, and the driving potential written in each pixel column is Offset by a predetermined amount.
[0055]
In the second frame (second vertical scanning period), the polarity of the analog signal written to each pixel is inverted and the order of writing is reversed. That is, a switch signal that is turned off in the first half of one horizontal scanning period 1H and turned on in the second half is input to the switch SW1. Thereby, the output terminal OUT1 is connected to the input terminal 1A of the signal line X1 in the second half of one horizontal scanning period. Then, a negative analog signal lower than the reference potential is written to the corresponding pixel 11 (R1).
[0056]
On the other hand, a switch signal that is turned on in the first half of one horizontal scanning period 1H and turned off in the second half is input to the switch SW2. Thereby, the output terminal OUT1 is connected to the input terminal 1B of the signal line X2 in the first half of one horizontal scanning period. Then, a positive analog signal higher than the reference potential is written to the corresponding pixel 12 (G1).
[0057]
In the third frame (third vertical scanning period) and below, the odd-numbered frames are controlled in the same manner as the first frame, and in the fourth frame (fourth vertical scanning period) and below, the even-numbered frames are controlled in the same manner as the second frame. Is done.
[0058]
For the other pixels, the pixels are selected in the same manner, and analog signals having a predetermined polarity are written respectively.
[0059]
That is, as shown in FIG. 5, in the first frame, for one line, analog signals having a polarity of “++++...” Output from each output terminal are respectively supplied to R1 and B1 in the first half of one horizontal scanning period. , G2, R3, B3, G4... Also, for one line, analog signals having a polarity of “-----...” Output from each output terminal in the second half of one horizontal scanning period are respectively G1, R2, B2, G3, R4, B4. Are written in each pixel column.
[0060]
Further, in the first frame, the drive control is similarly performed for two or less lines, and a positive analog signal is written in the first half of one horizontal scanning period to the pixel column corresponding to the odd-numbered signal line described above. Thus, a negative analog signal is written to the pixel column corresponding to the even-numbered signal line in the second half of one horizontal scanning period.
[0061]
On the other hand, in the second frame, for one line, analog signals having a polarity of “++++...” Output from each output terminal in the first half of one horizontal scanning period are respectively G1, R2, B2, G3, R4, Write to each pixel column of B4. For one line, analog signals having a polarity of “-----...” Output from each output terminal in the latter half of one horizontal scanning period are respectively R1, B1, G2, R3, B3, G4. Are written in each pixel column.
[0062]
Further, in the second frame, the drive control is similarly performed for the lines of 2 or less lines, and a positive analog signal is written in the first half of one horizontal scanning period to the pixel column corresponding to the even-numbered signal line described above. Thus, a negative analog signal is written to the pixel column corresponding to the odd-numbered signal line in the second half of one horizontal scanning period.
[0063]
In this manner, by driving each pixel at a predetermined timing in one horizontal scanning period, an analog signal having a predetermined polarity is written to all the pixels with a write pattern A as shown in FIG. In FIG. 6, “+” indicates that the analog signal written to the pixel is positive, and “−” indicates that the analog signal written to the pixel is negative. Further, the pixels surrounded by the square indicate that writing is performed in the first half of one horizontal scanning period.
[0064]
The write pattern A as shown in FIG. 6 satisfies all the above-mentioned reasons (1) and (2) at the same time, and considers the amount of fluctuation in the drive potential of the pixel written in the first half of one horizontal scanning period. By shifting the reference potential and offsetting the drive potential, pixels with potential fluctuations can be dispersed, and display defects can be suppressed.
[0065]
In the above-described embodiment, an example in which all two reasons are satisfied has been described. However, even with a writing pattern that satisfies at least one reason, display quality can be sufficiently improved.
[0066]
For example, the write pattern B shown in FIG. 6 is an example that satisfies the reason (1) but cannot satisfy the reason (2). Since the write pattern B can improve at least one reason, the same operation as the write pattern A can be performed by controlling the reference potential and the drive potential in consideration of the fluctuation of the drive potential of the pixel as described above. An effect is obtained.
[0067]
Next, as a second embodiment, an H / V inversion driving method will be described as an example. In this H / V inversion driving method, the polarity of the analog signal written to all the pixels is inverted every one vertical scanning period (one frame). Further, the polarity of the analog signal written to all the pixels connected on one signal line is inverted for each pixel, and the polarity of the analog signal written to the adjacent signal line is also inverted.
[0068]
As shown in the writing pattern C in FIG. 7, in one line of the first frame (first vertical scanning period), a positive analog signal is written to the pixel R1 in the first half of one horizontal scanning period, and one horizontal scanning period. In the second half, a negative analog signal is written to the pixel G1. Similarly, in one line, an analog signal having a positive polarity is written to each pixel of B1, G2, R3, B3, G4... In the first half of one horizontal scanning period. Further, in the second half of one horizontal scanning period, an analog signal having a negative polarity is written to each pixel of R2, B2, G3, R4, B4.
[0069]
In the two lines of the first frame, a positive analog signal is written in each pixel of the pixels G1, R2, B2, G3, R4, B4... In the first half of one horizontal scanning period, and the pixel R1 in the second half of one horizontal scanning period. , B1, G2, R3, B3, G4... Are written with negative analog signals.
[0070]
In one line of the second frame (second vertical scanning period), a positive analog signal is written to each of the pixels G1, R2, B2, G3, R4, B4... In the first half of one horizontal scanning period. In the second half of the scanning period, a negative analog signal is written to each of the pixels R1, B1, G2, R3, B3, G4.
[0071]
In the second line of the second frame, a positive analog signal is written to each of the pixels R1, B1, G2, R3, B3, G4... In the first half of one horizontal scanning period, and the pixel G1 is written in the second half of one horizontal scanning period. , R2, B2, G3, R4, B4... Are written with negative polarity analog signals.
[0072]
In the third frame (third vertical scanning period) and below, the odd-numbered frames are controlled in the same manner as the first frame, and in the fourth frame (fourth vertical scanning period) and below, the even-numbered frames are controlled in the same manner as the second frame. Is done.
[0073]
For the other pixels, the pixels are selected in the same manner, and analog signals having a predetermined polarity are written respectively.
[0074]
As described above, the writing pattern C as shown in FIG. 7 satisfies all the above-mentioned reasons (1) and (2) at the same time, and considers the fluctuation amount of the driving potential of the pixel written in the first half of one horizontal scanning period. Thus, by shifting the reference potential and offsetting the drive potential, pixels with potential fluctuations can be dispersed, and display defects can be suppressed.
[0075]
In the above-described embodiment, an example in which all two reasons are satisfied has been described. However, even with a writing pattern that satisfies at least one reason, display quality can be sufficiently improved.
[0076]
For example, the write pattern D shown in FIG. 7 is an example that satisfies the reason (1) but cannot satisfy the reason (2). Since the write pattern D can improve at least one reason, the same effect as the write pattern C can be obtained by controlling the reference potential and the drive potential in consideration of the fluctuation of the drive potential of the pixel as described above. An effect is obtained.
[0077]
Next, as a third embodiment, an H / 2V inversion driving method will be described as an example. In this H / 2V inversion driving method, the polarity of the analog signal written to all the pixels is inverted every two vertical scanning periods (2 frames). Further, the polarity of the analog signal written to all the pixels connected on one signal line is inverted for each pixel, and the polarity of the analog signal written to the adjacent signal line is also inverted.
[0078]
In this H / 2V inversion driving method, there is no write pattern that satisfies the above-mentioned reasons (1) and (2) at the same time. However, as with the write patterns E, F, and G shown in FIG. There is a writing pattern that satisfies only the above-described reason and cannot satisfy the reason (2).
[0079]
Even with such a writing pattern, the display quality can be sufficiently improved by controlling the reference potential and the driving potential in consideration of the fluctuation of the driving potential of the pixel as described above.
[0080]
As described above, in the display device according to this embodiment, since the number of output terminals of the signal line driving IC is smaller than the number of signal lines, the number of signal line driving ICs can be reduced, and the cost can be reduced. In addition to reducing the number of signal line driving ICs, it is possible to display without reducing the display quality of the screen.
[0081]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a display device that can increase the definition of pixels and prevent the occurrence of display defects without increasing costs. .
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display device according to an embodiment of a display device of the present invention.
FIG. 2 is a diagram schematically showing a configuration of a TCP provided on one side of the liquid crystal display device shown in FIG.
FIG. 3 is a diagram schematically showing a configuration of a signal line driving circuit of the liquid crystal display device shown in FIG. 1;
FIG. 4 is a timing chart for explaining a driving potential variation and a preferable driving method in the V-line inversion driving method according to the first embodiment;
FIG. 5 is a diagram showing signals written to one line in a preferred driving method in the V-line inversion driving method of the first embodiment within two vertical scanning periods;
FIG. 6 is a diagram showing a write pattern for explaining a preferred drive method and other drive methods in the V-line inversion drive method of the first embodiment.
FIG. 7 is a diagram showing a write pattern for explaining a preferred drive method and other drive methods in the H / V inversion drive method of the second embodiment.
FIG. 8 is a diagram showing a write pattern for explaining a preferred drive method and other drive methods in the H / 2V inversion drive method of the third embodiment.
[Explanation of symbols]
1. Liquid crystal display device
100: Array substrate
110 ... polycrystalline silicon thin film transistor
150: Gate line driving circuit
160... Signal line driving circuit
170 ... selection circuit
200 ... Counter substrate
300 ... Liquid crystal layer
500-N ... TCP
511 ... Signal line driving IC
OUT ... Output terminal
SW ... switch
X ... Signal line
Y ... Gate line

Claims (8)

A plurality of gate lines and a plurality of signal lines arranged orthogonal to each other on the substrate;
A pixel transistor disposed at each intersection of the gate line and the signal line;
A pixel electrode connected to each pixel transistor;
A drive that converts an input digital signal into an analog signal, divides the signal line into a plurality of signal line groups including a predetermined number of signal lines, and serially outputs an analog signal corresponding to each signal line group Circuit,
Selection means for sequentially distributing the analog signal from the drive circuit to the corresponding signal line of each signal line group;
Control means for controlling the distribution order of the analog signal to the signal line by the selection means,
Wherein, 4 in the vertical scanning periods or fewer in a plurality of vertical scanning periods, said plurality of predetermined potential to the same timing every pixel transistor connected on each signal line in each horizontal scanning period of the signal line Controlling the selection means to be driven with one polarity with reference to
The first pixel transistor group selected at the first timing in one horizontal scanning period is driven with the first polarity, and the second pixel transistor group selected at the second timing following the first timing in one horizontal scanning period is When driving with the second polarity opposite to the first polarity, when the driving potential of the first pixel transistor group fluctuates as the second pixel transistor group is driven, the driving potential of the first pixel transistor group The reference potential is shifted by a predetermined amount in accordance with a variation amount, and an offset potential in a direction opposite to the variation direction of the drive potential is applied to the first pixel transistor group, and the variation of the drive potential is applied to the second pixel transistor group. A display device characterized by providing an offset potential in the same direction as the direction.   2. The display device according to claim 1, wherein the reference potential is shifted in the same direction as a change direction of a driving potential of the first pixel transistor group.   The display device according to claim 2, wherein the shift amount of the reference potential is approximately −ΔV / 2 when a variation amount of the drive potential is −ΔV.   The display device according to claim 1, wherein the offset potential of the first pixel transistor group is approximately + ΔV / 2 when a variation amount of the drive potential is −ΔV. Wherein, in the second vertical scanning period, driven at one polarity with reference to a predetermined potential in the first half of every pixel transistor each horizontal scanning period which is connected on each signal line of said plurality of signal lines The display device according to claim 1 , wherein the selection unit is controlled as described above.   The signal lines adjacent to each other are driven with different polarities, and the pixel transistors adjacent to each other on one signal line are driven with different polarities, and the drive polarities of all the pixel transistors are inverted every vertical scanning period. The display device according to claim 5.   Adjacent signal lines are driven with different polarities, and all the pixel transistors connected on one signal line are driven with the same polarity, and the driving polarities of all the pixel transistors are inverted every vertical period. The display device according to claim 1. 8. The display device according to claim 7, wherein all the pixel transistors connected on the one signal line are driven at the same timing in each horizontal scanning period in one vertical scanning period .

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