JP3297335B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device in which the number of signal lines for driving each pixel is reduced.

[0002]

2. Description of the Related Art FIG. 19 is a diagram showing a configuration of a conventional liquid crystal display device. In this figure, reference numeral 1 is a liquid crystal panel, r scan lines G ₁ ~G _r and s signal lines D ₁ to D _s are arranged in a matrix, each of the scanning lines G ₁ ~G _r and the signal Line D
TFT T at the intersection of ₁ ~D _s, T, ... are formed. The liquid crystal layers L, L,... Are driven by turning on / off the transistors T, T,. The gate driver code 2 for driving the scan lines G ₁ ~G _r, 3 is a data driver for driving the signal lines D ₁ to D _s. Also,
Figure 20 is a diagram showing the drive timing of the scanning lines G ₁ ~G _r and the signal lines D ₁ to D _s.

[0003] In the configuration described above, the horizontal pixel rows are sequentially driven from the first row by the scanning lines G ₁ ~G _r are sequentially turned on, thereby, display is performed. Also, interlacing (interlaced scanning) according to the NTSC standard
In some cases, it is driven depending on the method.

As described above, in an active matrix liquid crystal display device having _r scanning lines G _{1 to} Gr and s signal lines D _{1 to} D _s , a gate driver 2 having r outputs and a s A data driver 3 having a book output is required outside the liquid crystal panel 1. This thin film transistor T, T, ... small carrier mobility in the amorphous silicon required for the formation of, for driving the scan lines G ₁ ~G _r or signal lines D ₁ to D _s in the interior of the liquid crystal panel 1 This is because a high-speed circuit cannot be formed.

[0005]

By the way, when the display screen is to be made higher definition (improvement in resolution), particularly,
An increase in the number of signal lines D _{1 to} D _s causes a narrower pitch of terminals, an increase in the number of data drivers, and an increase in power consumption. Although an example in which some functions of the data driver are formed of amorphous silicon has been reported, the external circuit becomes complicated such as generation of several tens of multiplexed signals, which leads to an increase in cost as a whole.

As a method of reducing power consumption, a driver voltage is reduced. For that purpose, a method of inverting the counter electrode (common inversion driving) is used. However, in this method, it is necessary to write signals of the same polarity during scanning, and it has been pointed out that a problem of crosstalk due to capacitive coupling between a signal line and a counter electrode has been pointed out. Also, in a liquid crystal display device, a number of thin film transistors must be formed,
There is a problem that the yield at the time of manufacturing decreases as the number increases.

The present invention has been made in view of the above circumstances, and can reduce the number of signal lines to avoid a narrow pitch of a terminal portion of a data driver, thereby reducing power consumption and cost. It is an object to provide a liquid crystal display device capable of achieving the above. Another object is to provide a liquid crystal display device in which a decrease in contrast and an increase in crosstalk do not occur even when common inversion driving is used. It is another object of the present invention to provide a liquid crystal display device in which the number of thin film transistors to be formed is reduced as much as possible to improve the production yield.

[0008]

In order to solve the above problems SUMMARY OF THE INVENTION The present invention includes a plurality of scan lines and a plurality of signal lines provided in a matrix, provided in parallel alternately to the signal lines each a control line which is adjacent the signal line and the front
Surrounded by said scanning lines adjacent to each other with serial control line
Provided corresponding to pixels formed in the first region, connected to the pixel electrode of the <br/> control line and the pixel, a first switch element which is turned on / off controlled by the control line, next to
Surrounded by the scanning lines adjacent to each other with the control line between the contact and at least two of said first switching element is the pixel into two including a second region, one and the second region of the adjacent scan lines Said two adjacent
Connected to said signal lines arranged between the pixel, the turned on by the drive signal applied to the scanning line <br/>, the first switch signal of said at least two from the signal line <br/> And one second switch element for supplying the element. The present invention also provides a plurality of scanning lines and a plurality of signal lines provided in a matrix, a plurality of control lines provided alternately and in parallel with each of the signal lines, and a plurality of control lines adjacent to the signal lines and the signal lines. The control line and the scanning line adjacent to the scanning line are provided corresponding to each of the pixel electrodes formed for every region surrounded by the adjacent scanning lines, and the pixel electrodes adjacent to each other across the signal line A switch element pair including two switch elements having one end connected to each other and the other end connected to each other, and turned on / off by a signal applied to the control line defining each area of the pixel electrode; a first switch element pair to be turned off controlled, define the region of the first of said other end and the pixel electrode of the switching element pairs, the first switching element pairs
Are disposed between the pixel electrodes to which the one ends are respectively connected.
That the connected between the signal line, the turned on by the drive signal either applied to one scan line among the scan lines defining a region of the pixel electrode, wherein a signal applied to the signal line A second switch element for supplying the first switch element pair
And the first switch element pair is controlled to be turned on / off by control signals applied to the control lines on both sides adjacent to the signal line at a time interval from each other. And

According to the present invention, a control line parallel to a signal line is provided on a liquid crystal panel, a second switch element,
Since the two switch elements are provided in correspondence with each other, it is possible to select a pixel to which image data is to be written by a signal applied to the control line, and it is possible to improve the yield during manufacturing. Further, the number of signal lines with respect to the number of pixels can be reduced, and the effect of avoiding the narrow pitch of the terminal portion of the data driver can be obtained. In addition, since the number of signal lines can be reduced, power consumption can be reduced, the size of the entire liquid crystal display device can be prevented, and the cost of the liquid crystal display device can be significantly reduced. The effect that it can be obtained is obtained.

The control line is provided alternately with the signal line, and is an n-th control line (where n is an odd number).
Are connected in common and the m-th control line (where m is 0
, And m = n ± 1) are commonly connected, and the m-th control line and the n-th control line may be alternately driven for each image display unit. . The control lines are provided alternately with the signal lines, and an n-th control line (where n is an odd number) is commonly connected,
The m-th control line (where m is an even number not including 0)
, And m = n ± 1) are connected in common, and the n-th
The n-th control line and the m-th control line may be alternately driven each time the scanning line is driven. Further, the control line is provided alternately with the signal line,
The nth control line (where n is an odd number) is commonly connected, and the mth control line (where m does not include 0).
Are evenly connected and m = n ± 1) , the n-th control line and the m-th control line are alternately driven for each image display unit, and the signal line May be driven by signals having different polarities between adjacent ones. Further, the present invention provides the control line
A voltage for canceling a potential based on the signal line is superimposed. Further, an average value of voltages to be applied to each of the signal lines may be calculated, and a voltage based on the average value may be superimposed on the control line. The second switch element provided between the n-th control line and the signal line; a storage capacitor provided between the m-th control line; and the m-th control line. And the signal line and the second switch element, and a storage capacitor provided between the n-th control line.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a liquid crystal panel of a liquid crystal display according to a first embodiment of the present invention.
This figure is a diagram showing a configuration of a pixel in a part of the liquid crystal panel. Pixels having the configuration shown are arranged in a matrix of n in a horizontal direction and m in a vertical direction to form a liquid crystal panel. The liquid crystal panel is provided with a gate driver for driving the scanning lines and a data driver for driving the signal lines (see FIG. 3).

In FIG. 1, G _i (i = 1, 2,...,
m) is a scanning line arranged in the horizontal direction, and transmits a gate signal output at a predetermined timing from a gate driver to sequentially drive pixels in each row. D _j (j = 1, 3,
.., N-1) are signal lines arranged in the vertical direction, transmit an image signal output from the data driver at a predetermined timing, and supply the image signal to pixels in each column.

[0013] CA, CB denotes a control line arranged in parallel with the signal lines D _j so as to sandwich the respective signal lines D _j. The control lines CA and CB are alternately arranged as shown in the drawing, and one of the control lines is arranged between the signal lines. The control lines CA are commonly connected, and the control lines CB are also commonly connected (see FIG. 3).
A control signal at a predetermined timing described later is transmitted.

P (i, j) in FIG. 1 indicates a pixel at the i-th row and the j-th column. Each pixel is provided corresponding to an intersection of each scanning line with each signal line and each control line. That is, in each row, two pixels are arranged for one signal line, and one of the two pixels is located on the control line CA side and the other is located on the control line CB side. For example, the scanning line G _i in FIG.
And the intersection of the signal lines D _j, the signal line D _j left control line C
The pixel P (i, j) is located on the A side, and the pixel P (i, j + 1) is located on the right control line CB side. Note that FIG.
Control lines shown CA, signal lines D _j, and the scanning line G _i, in G _{i + 1}
A region surrounded by the pixel P (i, j) and a control line C
B, the pixel is surrounded by the signal line D _j and the scanning lines G _i and G _{i + 1.}
The region including P (i, j + 1) is the first region according to the present invention.
Is an area corresponding to. Control line CA, control line C
B, and the scanning line G _i, surrounded by G _{i + 1,} pixel P (i, j)
And a region including the pixel P (i, j + 1)
This is an area corresponding to two areas.

[0015] Each pixel has a liquid crystal layer L, the liquid crystal layer L provided between the drawing signal lines D _j and the control line CA is
Is connected to the drain electrode of the switching element T _CA of the TFT or the like, a liquid crystal layer L provided between the control line CB and the signal line D _j is connected to the drain electrode of the switch element T _CB. Further, a source electrode of the source electrode and the switching element T _CA of the switch element T _CA are electrically connected. The gate electrode of the switching element T _CA is connected to the control line CA, a gate electrode of the switch element T _CB is connected to the control line CB.

The signal line D_jHas a signal line D_jLeft and right of
Provided pixel P (i, j) and pixel P (i, j + 1)
One switching element T in units of_DIs provided
You. This switch element T_DGate electrode is scanning line G_iContact
The source electrode is connected to the signal line D _jConnected to the drain
Electrode is switch element T_CA, T_CBTo the source electrode of each
It is connected. The above switch element T_DIs the gate signal
Therefore, it is turned on / off and the switching element T_{C A}, T_CBIs control
Turned on by control signals transmitted to lines CA and CB
/ Off. With the above configuration, each liquid crystal layer L
Is the switch element T_DON / OFF and switch element T_CAor
Is T_CBSignal lines according to the logical product of on / off
Image signal is applied to write image data.
It is.

Next, an image display operation according to the above configuration will be described. FIG. 2 shows how each signal is generated in the present embodiment. In this figure, G ₁ and G ₂ are gate signals for transmitting scanning lines G ₁ and G ₂ , and D ₁ and D ₃ are signal lines D ₁ and D 2.
₃ , image signals CA and CB are transmitted on control lines CA and CB.
, Respectively. The scanning lines G ₁ and G ₂ and the signal lines D ₁ and D ₃ correspond to i = j = 1 in FIG.
Corresponding to when viewed as (for signal line D _3, are omitted in FIG. 1).

First, at time t ₁ in FIG. 2, when a display of a certain display field (display unit of an image) is to be started, the control signal of the control line CA is set to the H level, and the control line CB is set.
Is set to L level, the switch element _TCA is turned on, and the switch element _TCB is turned off. Also, at the same time the gate signal of the scanning lines G ₁ this time is set to the H level, which holds one horizontal scanning period. As a result, during one horizontal scanning period, the pixels (P
(1,1), P (1,4), ..., P (1, j), P
Only at (1, j + 3),...), The switching element T _D
And the switch element _TCA are both turned on, and the image data supplied from the signal line is written to those pixels.

Here, the image data is supplied by an image signal corresponding thereto. In the present embodiment, as shown by D ₁ and D ₃ in the figure, the same polarity is applied during one horizontal scanning period, and An image signal is supplied with a polarity that is inverted every horizontal scanning period. The same applies to image signals supplied via other signal lines D ₅ , D ₇ ,. As a result, first, the image data at the time of the display operation of the first row is supplied by a + polarity image signal as shown in the figure, and the pixels in the first row, j-th column and the first row, j + 3-th column have + Image data is written with the polarity.

Next, one horizontal scanning period elapses and the scanning line G
When _one of the gate signal becomes the L level, the gate signal of the scanning lines G ₂ and H level. Further, the control signals of the control lines CA and CB maintain the above-mentioned state, and the switching elements T
_CA is kept on and the switching element T _CB is kept off. Thereby, the pixels (P (2,1), P (2,4),..., P (2, j),
P (2, j + 3),...
_D and the switch element _TCA are both turned on, and image data is written to those pixels. Here, since the polarity of the image signal is inverted as described above, the image data of the second row is written with the negative polarity of the polarity opposite to that of the first row.

Thereafter, similarly, the gate signals of the scanning lines G ₃ , G ₄ ,... Are sequentially set to H level while the control signal of the control line CA is set to H level and the control signal of the control line CB is set to L level. (Not shown), image data is written to the pixels in each row.
Thus, the period of one field from time t ₁ ~t _2, pixel P (i, j) and P (i, j + 3) (i = 1,
2,..., M: j = 1, 5,..., N−3). FIG. 3A schematically illustrates the pixels to which the image data is written in this way by the polarity of the image signal with a circle. The portion of the polarity is not shown together circles in the figure, already shows a pixel image data is written at time t ₁ earlier field.

Next, when the time t ₂ in FIG. 2, to start the display of the next display field, the control signal of the control line CA L level, the control signal of the control line CB and H level,
The switch element _TCA is turned off, and the switch element _TCB is turned on. That is, the time t ₁ ~t pixels P image data has been written in the _second period (i, j) and P
Instead of (i, j + 3), the pixels P (i, j + 1) and P (i, j + 2) are brought into a state in which image data can be written. Then, similarly to the above, first, the scanning line G ₁
Of the pixels (P (1,2), P (1,3),..., P) located on the control line CB side of the first row
Only at (1, j + 1), P (1, j + 2),..., The switch element T _D and the switch element T _CB are turned on, and image data is written to those pixels with the positive polarity.

Next, when the gate signal of the scanning line G ₁ goes low, the gate signal of the scanning line G ₂ goes high. Also, at this time, the state of the control signal is held, and the pixels (P (2,
2), P (2,3),..., P (2, j + 1), P (2,
j + 2),...) is written with negative polarity. Thereafter, similarly, the gate signals of the scanning lines G ₃ , G ₄ ,... Are set to the H level (not shown), and the pixels P (i, j +
1) and P (i, j + 2) (i = 1, 2,..., M: j =
, N-3) is written.

The pixels to which the image data is written in this manner are schematically shown in FIG. In FIG. 3B as well, the pixels to which the image data is written are represented by the polarities of the image signals with circles. Also, portions of the polar not shown together circles in the figure, the time t ₂ previous field, i.e., the image data indicates a pixel written by the above-mentioned fields of the time t ₁ ~t _2, these 3 correspond to the pixels in which the polarity of the image signal is indicated by a circle in FIG. As shown in these figures, the polarity inversion in the present embodiment is similar to 1H inversion in which the polarity is inverted every horizontal scanning period.

Thereafter, the above-described display operation is repeated in the same manner.
Pixels P (i, j) and P (i, j + 3) for each field
Alternatively, the image data is written by selecting the pixels P (i, j + 1) and P (i, j + 2). According to such a display operation, each pixel is written with image data once in two fields and driven by polarity inversion once in two fields. This results in a polarity distribution not shown.

[Second Embodiment] In the first embodiment, since the control signal is switched for each display field, the pixel potential fluctuates as shown in FIG. 4 (V _com is the counter electrode potential). This is due to the feed-through voltage (ΔV ₁ , ΔV ₁ ′) from the scanning line immediately after writing of the image data (t ₂₀ , t ₂₂ ) and the feed-through voltage from the control line CA (CB). Here, the fluctuation (ΔV ₂ , ΔV ₂ ′) of the pixel potential due to the feed-through voltage from the control line occurs at the timing (t ₂₁ , t ₂₃ ) when the control signal is at the L level. The pixel P
At (m, j), a variation (ΔV ₃ ) in the pixel potential due to the feed-through voltage from the control line occurs at the timing (t ₂₂ ) when the control signal is set to the H level. They are,
As shown in the drawing, the relative timing with respect to the writing of the image data differs depending on the position of the scanning line.
The effective voltage differs between (1, j) and the pixel P (m, j), and as a result, luminance unevenness may occur in raster display of the same color.

Therefore, in a second embodiment of the present invention described below, the manner of generating control signals on the control lines CA and CB is changed as shown in FIG. First, at time t ₃ , when a display of a certain display field is to be started, the control signal of the control line CA is set to the H level, the control signal of the control line CB is set to the L level, the switch element _TCA is turned on,
The switching element T _CB is turned off, and the pixels P (1,1) located on the control line CA side of the first row as in the first embodiment.
j) and P (1, j + 3) are written with positive polarity image data.

[0028] Then, the gate signal of the scanning lines G ₁ becomes L level at time t _4, when the gate signal of the scanning lines G ₂ is H level, the control signal of the control line CA L level, the control line CB The control signal is switched to H level. As a result, in the second row, image data is written in the negative polarity to the pixels P (2, j + 1) and P (2, j + 2) located on the control line CB side.

Thereafter, similarly, the control signals of the control lines CA and CB are switched every one horizontal scanning period, and the pixels P (i, j) and P (i, j + 3) located on the control line CA side are controlled. Pixels P (i, j + 1) and P located on the line CB side
(I, j + 2) are alternately selected to write image data.

In the next display field after time t ₅ , first, at time t ₅ , the control signal of the control line CA is set to L level, the control signal of the control line CB is set to H level, and Pixel P (1, j) located on the control line CB side
+1) and P (1, j + 2) are written with the + polarity. And, thereafter while switching the same control signal, writing the image data, to write the image data to a pixel that has not been selected at the time t ₃ ~t _5.

FIGS. 6A and 6B schematically show pixels to which image data is written in each field. This figure also shows pixels to which image data is to be written with polarities marked with circles as in FIGS. 3A and 3B. The polarity distributions shown in FIGS. 6A and 6B are slightly different from those in FIGS. 3A and 3B, but are similar to 1H inversion in any case.

FIG. 7 shows how the pixel potential fluctuates in the display operation described above. In the present embodiment, since the control signal is switched every one scanning line period, as shown in the figure, depending on the position of the scanning line, the timing of setting the control signal to the L level, the writing of image data, There is no difference in the relative timing of Therefore, the pixel P
The effective voltages at (1, j) and the pixel P (m, j) do not differ, and no luminance unevenness occurs in raster display of the same color.

However, in the case of the above display operation
Means that the retention rate of the image signal in each pixel decreases.
Problem. Therefore, as shown in FIG.
Child T _CAAnd T_CBAre provided with a storage capacitor C. in this way
By doing so, the problem of such a decrease in the retention rate can be solved.

[Third Embodiment] In the above-described second embodiment, the control signal is switched every period of one scanning line, so that the control signal is kept low regardless of the position of the scanning line.
The difference in the relative timing between the level timing and the image data writing is eliminated. However,
There may be a case where it is desired to drive using the generation form of the control signal in the first embodiment shown in FIG. In this case, the problem cannot be solved in the first place. In order to eliminate the difference in the effective voltage between the pixel P (1, j) and the pixel P (m, j) shown in the first embodiment, it is conceivable to compensate for the difference in the voltage value by an appropriate method. However,
When compensating for differences in voltage values, there are many cases where differences in voltage values cannot be compensated for due to variations in the liquid crystal layer L. The third embodiment of the present invention has been made to solve the above-described problems.

FIG. 9 shows a liquid crystal display according to a third embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of a liquid crystal panel of the display device. Shown in FIG.
The liquid crystal display device according to the third embodiment of the present invention is shown in FIG.
And a liquid crystal display according to the first embodiment of the present invention.
The difference is that the switching element T _CAOther electrode and control line C
B and storage capacity C₁Is provided, and the switching element T_{C B}
Between the other electrode and the control line CA._TwoProvided
It is a point that was done. In this configuration, each pixel is in the first implementation
It is driven in the manner of generating the control signal shown in FIG.

FIGS. 10 (a) and 10 (b) are diagrams similar to the diagrams showing the variation of the pixel potential in the first embodiment shown in FIG. 4, and FIG. 10 (c) shows the third embodiment of the present invention. FIG. 5 is a diagram illustrating a change in pixel potential according to the embodiment. As shown in FIG. 10A, at the time when the control signal CA rises,
As shown in FIG. 10B, the potential of the pixel P (i, j) drops by ΔV ₁ , and the voltage drops by the value ΔV ₂ at the time when the control signal CA falls. This phenomenon is
It is due to the feedthrough voltage due to the parasitic capacitance of the TFT constituting the switching element T _D.

The parasitic capacitance between the gate and the drain of the TFT is C _gd , the capacitance of the pixel L is C _lc , the voltage amplitudes of the control lines CA and CB are V _c , and the values of the storage capacitors C ₁ and C ₂ are C _X. if you did this,
The above value ΔV ₂ is given by the following equation.

ΔV ₂ = (C _gd −C _x ) / (C _gd + C _lc + C _x ) × V _c (1)

Therefore, the values C _X of the storage capacitors C ₁ and C ₂ are given by C _X =
By setting C _gd , the value ΔV ₂ can be made zero because the numerator of the above equation becomes zero. FIG. 10 (c)
FIG. 9 is a diagram illustrating pixel potentials when the values C _X of the storage capacitors C ₁ and C ₂ are set to C _X = C _gd . FIG.
The pixel potential does not change even at the fall of the voltage B). Therefore, even when the control signal generation mode shown in the first embodiment is used, power consumption does not increase, image sticking of the liquid crystal layer L, and generation of flicker do not occur.

[0040] Fourth Embodiment Next, a description will be given of a fourth embodiment of performing a display operation by changing the mode for generating an image signal of the signal line D _j. In the present embodiment, each signal is generated according to the generation mode shown in FIG. This corresponds to a case in which the generation mode of the gate signal and the control signal is the same as that of the first embodiment, and the image signals are supplied with different polarities between adjacent signal lines. This embodiment can be used for both the liquid crystal display according to the first embodiment of the present invention shown in FIG. 1 and the liquid crystal display according to the third embodiment of the present invention shown in FIG.

First, during one horizontal scanning period from time t _{6 to} time t ₇ , the control signal of the control line CA is set to the H level, and the pixels P (1, j) and P ( 1, j +
3) Write the image data. Then, the polarity of the image signal supplied at this time, in the signal line D ₁ as shown - in the D ₃ and the polarity of the +. Although not shown, the signal lines D ₅ , D ₇ , D ₉ , D ₁₁ ,... Have different polarities between adjacent signal lines, such as −, +, −, +,. Supply image signal.

Subsequently, the control line C in the second row from time t ₇
Pixels P (2, j) and P (2, j + 3) located on A side
Write image data to Then, at this time, the polarity of the image signal in each signal line is set to be opposite to the polarity in the first row. In this manner, the polarity of the image signal and different for each signal line during each line of the image data writing, in the display operation of the next field, the signal lines D _1,
In D ₃ , D ₅ , D ₇ , ...,-, +,-,
An image signal is supplied according to the polarity of +,.

In the display operation of the next field, it is assumed that the polarity of the image signal of each signal line in each row is inverted. That is, the signal lines D ₁ ,
In D ₃ , D ₅ , D ₇ , ..., respectively, +,-, +,
An image signal is supplied depending on the polarity of-,.
Thereafter, the polarity switching is similarly repeated to perform the inversion driving.

FIGS. 12A and 12B schematically show pixels to which image data is written in each field by the display operation described above. This figure also shows pixels to which image data is written in the same expression format as in FIGS. The polarity distribution shown in FIG. 12 is closer to dot inversion than the polarity distributions shown in FIGS. Therefore, according to the display operation in the present embodiment, the first and the first are described.
Flicker is less noticeable than the display operation in the second embodiment, and crosstalk is also reduced.

[Fifth Embodiment] In the common inversion driving, the polarities of the image signals at the same timing must be the same. Therefore, the potential of the common electrode fluctuates due to capacitive coupling between the signal line and the common electrode. This causes a decrease in contrast and an increase in crosstalk. Therefore, in the present embodiment, a cancel signal for canceling the fluctuation of the common electrode potential is superimposed on the control signal.

FIG. 13 shows how each signal is generated in this embodiment. Note that this is obtained by superimposing a cancel signal on the control signal in the first embodiment. This embodiment corresponds to the first embodiment of the present invention shown in FIG.
The present invention can be applied to both the liquid crystal display according to the embodiment and the liquid crystal display according to the third embodiment of the present invention shown in FIG. First, at time t ₈ , when the display of a certain display field is to be started, the control signal of the control line CA is set to the H level, and the pixels P (1, j) and P Image data is written to (1, j + 3) with a positive polarity (D ₁ , D ₃ ,...).

At this time, a cancel signal for canceling the fluctuation of the potential of the common electrode due to the image signal of the positive polarity is superimposed on the control signal of the control line CB which is set to the L level. That is, as shown in the control signal (CB) at time t ₈ ~t ₉ in the figure, the control signal of the control line CB, the normal L-level signal constant - we're assumed that overlapped with the polarity voltage . Thus, the sum of the control signals of the control lines CA and CB is set to have the opposite polarity to the image signal. still,
The term "-polarity voltage" as used herein means a voltage that has a negative polarity with respect to the counter electrode potential. Also, the amplitude of the reverse polarity with respect to the image signal is appropriately set (for example, 4 V to 10 V).
degree).

Then, the pixel P in the second row from time t ₉
When writing image data with negative polarity to (2, j) and P (2, j + 3), it is assumed that the control signal of the control line CB is obtained by superimposing a constant positive polarity voltage on a normal L level signal. The + polarity voltage mentioned here is also a voltage based on the potential of the common electrode. Thereafter, a voltage having a polarity opposite to that of the image signal is superimposed on the control signal of the control line CB in the same manner.

Next, in the display of the next display field from time t _10, the control signal of the control line CB and H level, and writes the image data into the pixel P (i, j + 1) and P (i, j + 2) . At this time, the same cancel signal as described above is superimposed on the control signal of the control line CA which is set to the L level.

As described above, the control signal is superimposed with the cancel signal for preventing the fluctuation of the potential of the common electrode,
It is possible to suppress a decrease in contrast and an increase in crosstalk. Here, the cancel signal may be any signal that causes the sum of the control signals of the control lines CA and CB to have the opposite polarity to the image signal. Therefore, the superimposition of the cancel signal is not limited to the above-described mode,
The control signal may be superimposed on the control signal to be set to the H level, or may be superimposed on one of the control signals.

[Sixth Embodiment] According to the fifth embodiment, the cancel signal prevents the potential of the common electrode from fluctuating. However, in the fifth embodiment, since the cancel signal is a constant + polarity voltage or a constant -polarity voltage, fluctuations in the counter electrode potential cannot be completely removed due to the influence of the image signal level. Therefore,
In the present embodiment, a means for specifically determining an appropriate cancel signal and superimposing it on a control signal will be described.

FIG. 14 is a block diagram showing the structure of the cancel signal calculation / superimposition means. In the figure, 1
Reference numeral 0 denotes an integration circuit, which integrates an image signal included in one horizontal scanning period, and sequentially integrates the integration value into a sample-and-hold circuit 1
Output to 1. The sample and hold circuit 11 samples and holds the sequentially output integrated values for one horizontal scanning period and continues to output the integrated values to the level conversion circuit 12. The level conversion circuit 12 converts the level of the control signal on the control line CB (or CA) based on the integrated value received from the sample and hold circuit 11.

Here, the level conversion in the level conversion circuit 12 is selected in accordance with the number and size (width) of the signal lines D _j and the control lines CA and CB so that the fluctuation of the common electrode potential can be appropriately removed. I do. For example, as shown in FIG. 1, the number of signal lines D _j, control line CA and CB are equal to the number of the combined, and when the width of their signal lines and control lines are all identical Calculating an average value of the image signal from the integrated value, and superimposing a voltage twice as large as the average value and having a polarity opposite to the polarity of the image signal on the control signal;
Is performed. In this case, the reason why the magnitude of the cancel signal is set to twice the average value is that the number of control lines on which the cancel signal is superimposed is の of the number of signal lines.
This is because

In such a configuration, as shown in FIG. 15, while the display of a certain i-th row is being performed, the image signal of the next (i + 1) -th row is integrated by the integration circuit 10 (see FIG. 15). Integration period). Here, since the image signal is supplied within the effective display period of one horizontal scanning period, the integration operation ends before the end of one horizontal scanning period as illustrated. When the integration operation is completed, the integrated value obtained at this time is output to the sample hold circuit 11 and starts to be output to the level conversion circuit 12.

As a result, the level conversion circuit 12 converts the level of the control signal based on the integrated value and starts outputting the level-converted control signal after the end of the effective display period of the i-th row (see FIG. CB 'output "). Subsequently, the display of the (i + 1) -th line is started (“data output” in the figure).

As described above, according to the present embodiment, since the cancel signal is calculated at any time in consideration of the level of the image signal, the influence of the image signal level can be eliminated, and the fluctuation of the common electrode potential can be completely reduced. It can be removed.

[0057]

【Example】

First Embodiment FIG. 16 shows a specific example of the liquid crystal display device according to the first embodiment of the present invention. This diagram is a layout diagram more specifically showing a configuration of a pixel in a part of the liquid crystal panel shown in FIG. 1, and is 480 (horizontal) × 64.
4 inch VG of 0 (vertical direction) x 3 (R, G, B) pixels
A (Video Graphic Array) is assumed.

In FIG. 16, reference numeral 20 denotes a pixel electrode;
In each pixel, liquid crystal is sealed between the pixel electrode 20 and the counter electrode. 21 is a gate wiring, corresponding to the scanning line G _i in the above embodiment. Reference numeral 22 denotes amorphous silicon, and reference numeral 23 denotes a contact hole, which constitutes a wiring including the above-described switch element T _D , switch element T _CA , and T _CB . 24 is a data line, corresponding to the signal lines D _j. 25 and 26 are control lines,
25 corresponds to the control line CA, and 26 corresponds to the control line CB. Reference numeral 27 denotes an opening in the pixel. The pixel pitch in FIG. 16 is 43 μm × 129 μm.

[Second Embodiment] FIG. 17 is a layout diagram showing a specific example of the liquid crystal display device according to the third embodiment of the present invention. The layout diagram of the second embodiment of the present invention shown in FIG. 17 is different from the layout diagram of the first embodiment of the present invention shown in FIG. 16 in that storage capacitors 50 and 52 are provided. is there. The electrode 54 electrically connected to the contact hole 23 and the electrode 5 electrically connected to the control line 26
6 form two electrodes of the storage capacitor 50, the electrode 58 electrically connected to the contact hole 23, and the control line 2.
The electrode 60 electrically connected to the storage capacitor 5
Form two electrodes. Between the electrodes 54 and 56,
An insulating film is formed between the electrode 58 and the electrode 60.

[Third Embodiment] FIG. 18 is a layout diagram showing a specific example of the liquid crystal display device according to the third embodiment of the present invention. The layout diagram of the third embodiment of the present invention shown in FIG. 18 is different from the layout diagram of the second embodiment of the present invention shown in FIG. Amorphous silicon 6 between the electrode 58 and the electrode 60
2 and 64 are formed. The switching elements T _D , T _CA , and T _CB in FIG. 9 are formed by TFTs of the amorphous silicon 62 and 64, and the TFTs are also formed of the amorphous silicon 22. 52 can be formed by the same manufacturing process as the TFT.

Further, since the sizes of the storage capacitors 50 and 52 can be appropriately set according to the dimensions of the amorphous silicon 62 and 64, a capacitor satisfying the above-mentioned expression (1) can be easily formed. Also, in this case,
Since the switching elements T _D , T _CA , and T _CB have the same structure (meaning that amorphous silicon is formed between the electrodes), the storage capacitors 50 and 52 and the switching elements T _D , Switch element T _CA ,
This is advantageous because the characteristics such as the voltage dependency of the switching element T _CB are the same.

[0062]

As described above, according to the present invention, the control lines parallel to the signal lines are provided on the liquid crystal panel, and the second switch element and the two switch elements are provided in correspondence with each other. Pixels to which image data is to be written can be selected by a signal applied to the control line, and the production yield can be improved. Also,
The effect is obtained that the number of signal lines with respect to the number of pixels can be reduced, and the narrow pitch of the terminal portion of the data driver can be avoided. In addition, since the number of signal lines can be reduced, power consumption can be reduced, the size of the entire liquid crystal display device can be prevented, and the cost of the liquid crystal display device can be significantly reduced. The effect that it can be obtained is obtained. In particular, since a predetermined set of control lines is alternately driven each time the driving of the scanning line is changed, the relative timing of the driving and the control line driving is the same for all the scanning lines. As a result, it is possible to avoid a situation in which the effective voltage of the applied signal is different for each pixel, and it is possible to obtain an effect that it is possible to prevent the occurrence of luminance unevenness when performing raster display. In addition, since adjacent signal lines are driven by signals of different polarities, inversion driving close to dot inversion can be performed, and an effect that flicker and crosstalk can be suppressed can be obtained. Furthermore,
Since a voltage for canceling the potential based on the signal line is superimposed on the control line, fluctuations in the counter electrode potential can be suppressed even when the common inversion drive is used, preventing a decrease in contrast and an increase in crosstalk. The effect is obtained. Further, since the voltage based on the average value of the voltage applied to the signal line is further superimposed, the influence of the signal level of the signal line can be eliminated, and the fluctuation of the common electrode potential can be completely removed. It becomes possible.
Also, since a storage capacitor is added to prevent the voltage applied to the pixel from fluctuating when the voltage of the control line fluctuates,
It is possible to improve the brightness unevenness and to reduce the power consumption because it is not necessary to apply a voltage for compensating the fluctuated voltage.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a liquid crystal panel of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a generation mode of each signal in the first embodiment.

FIG. 3 is a diagram schematically illustrating pixels to which image data is written according to the first embodiment.

FIG. 4 is a diagram illustrating a change in pixel potential according to the first embodiment.

FIG. 5 is a diagram illustrating a generation mode of each signal in a second embodiment.

FIG. 6 is a diagram schematically illustrating pixels to which image data is written according to a second embodiment.

FIG. 7 is a diagram illustrating a change in pixel potential according to a second embodiment.

FIG. 8 is a diagram showing a configuration for preventing a retention ratio from decreasing in a second embodiment.

FIG. 9 is a diagram illustrating a configuration of a liquid crystal panel of a liquid crystal display device according to a third embodiment.

FIGS. 10A and 10B are diagrams showing a change in pixel potential, and FIGS.
(B) is a figure similar to the figure in 1st Embodiment,
(C) is a diagram showing a change in pixel potential according to the third embodiment of the present invention.

FIG. 11 is a diagram illustrating a generation mode of each signal in a fourth embodiment.

FIG. 12 is a diagram schematically illustrating pixels to which image data is written according to a fourth embodiment.

FIG. 13 is a diagram illustrating a generation mode of each signal in a fifth embodiment.

FIG. 14 is a block diagram illustrating a configuration of a cancel signal calculation and superimposing unit according to a sixth embodiment.

FIG. 15 is a diagram for explaining the operation of a canceling signal calculating and superimposing means.

16 is a layout diagram more specifically showing a configuration of a pixel in a part of the liquid crystal panel shown in FIG.

17 is a layout diagram more specifically showing a configuration of a pixel in a part of the liquid crystal panel shown in FIG.

18 is another layout diagram more specifically showing a configuration of a pixel in a part of the liquid crystal panel shown in FIG.

FIG. 19 is a diagram illustrating a configuration of a conventional liquid crystal display device.

FIG. 20 is a diagram showing driving timings of scanning lines and signal lines in a conventional liquid crystal display device.

[Explanation of symbols]

CA, CB control line G _i scan lines D _j signal line L liquid crystal layer P (i, j) pixel T _CA, T _CB switching element T _D switching element 10 integrating circuit 11 sample-and-hold circuit 12 the level converting circuit C _1, C ₂ Retention capacity

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-202077 (JP, A) JP-A-3-71185 (JP, A) JP-A-61-290490 (JP, A) JP-A-5-290490 289635 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/136 G02F 1/133

Claims (8)

(57) [Claims] And 1. A plurality of scan lines provided in a matrix and a plurality of signal lines, and control lines provided in parallel alternately to the signal lines respectively, and the signal line and the control line adjacent provided corresponding to the first pixel are formed in a region <br/> surrounded by said scanning lines adjacent to, and connected to the pixel electrode of the control lines and the pixels on by the control line / a first switch element is turned off controlled, surrounded by the scanning lines adjacent to each other with the control line adjacent to at least the two of the first switching element in the pixel into two including a second region, wherein two adjacent to that contained in one and the second region of the adjacent scan lines
Connected to said signal line disposed between that pixel, the scan
It is turned on by a drive signal applied to the line , and the signal
A liquid crystal display device; and a second switch element of one supplying the signal from the line to the at least two first switching element. 2. A plurality of scan lines provided in a matrix and a plurality of signal lines, a plurality of control lines the provided and in parallel alternately with the signal lines, adjacent to the signal line and the signal lines The control line and the scanning line adjacent to the scanning line are provided corresponding to each of the pixel electrodes formed for every region surrounded by the adjacent scanning lines, and the pixel electrodes adjacent to each other across the signal line A switch element pair including two switch elements having one end connected to each other and the other end connected to each other, and turned on / off by a signal applied to the control line defining each area of the pixel electrode; Off controlled first
And switching element pairs, defining a region of said first switching element to said other end and said pixel electrode of said one end of said first switching element pairs
Are connected between the respective signal lines disposed between the pixel electrodes connected thereto, and are turned on by a driving signal applied to one of the scanning lines defining the pixel electrode region. And a second switch element for supplying a signal applied to the signal line to the first switch element pair , wherein the first switch element pair is connected to control lines on both sides adjacent to the signal line. A liquid crystal display device which is controlled to be turned on / off by control signals applied at staggered times to each other. 3. The control line is provided alternately with the signal line, an n-th control line (where n is an odd number) is commonly connected, and an m-th control line (where m is an integer). Are even numbers not including 0 and m = n ± 1), and the m-th control line and the n-th control line are alternately driven for each image display unit. 3. The liquid crystal display device according to claim 1, wherein: 4. The control line is provided alternately with the signal line, an n-th control line (where n is an odd number) is commonly connected, and an m-th control line (where m Is an even number not including 0 and m = n ± 1), and the n-th control line and the m-th control line are alternately switched every time the driving of the scanning line is changed. 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is driven. 5. The control line is provided alternately with the signal line, an n-th control line (where n is an odd number) is commonly connected, and an m-th control line (where m is an integer). Is an even number not including 0, and m = n ± 1), and the n-th control line and the m-th control line are alternately driven for each image display unit. 3. The liquid crystal display device according to claim 1, wherein said signal lines are driven by signals having different polarities between adjacent signal lines. 6. The liquid crystal display device according to claim 1, wherein a voltage for canceling a potential based on the signal line is superimposed on the control line. 7. The liquid crystal display device according to claim 6, wherein an average value of a voltage to be applied to each of the signal lines is calculated, and a voltage based on the average value is superimposed on the control line. 8. A storage capacitor provided between the n-th control line and the signal line, the second switch element provided between the n-th control line and the m-th control line, and a storage capacitor provided between the m-th control line and the m-th control line. 4. The semiconductor device according to claim 3, further comprising: the second switch element provided between the control line and the signal line, and a storage capacitor provided between the n-th control line. Liquid crystal display device.