JP5418388B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device used for a notebook type or desktop type personal computer or television, and various industrial monitors.

  In the liquid crystal display device, it is necessary to control a thin film transistor (hereinafter referred to as TFT) corresponding to each pixel in order to apply a voltage to a plurality of liquid crystal cells in the liquid crystal panel. For this reason, a source driver IC (hereinafter referred to as IC means an integrated circuit) for applying a liquid crystal applied voltage to the source wiring (data wiring) in the liquid crystal panel is required, and the gate wiring (scanning wiring) is similarly TFT. Therefore, a gate driver IC for applying a gate selection signal for controlling on / off is required.

  The source driver IC is particularly expensive among circuit members for driving the liquid crystal panel. In recent years, various demands for reducing the number of source driver ICs used have been made while the demand for cost reduction for liquid crystal display devices is increasing. As one of these reduction plans, a method of reducing the number of ICs used by increasing the number of outputs per IC is well known. However, when such an IC itself is newly developed, a high development cost is required.

  As another reduction plan, there is a method in which the source electrodes of the TFTs are arranged on the left and right sides of one source line, and the voltage corresponding to different display data is applied in a time-sharing manner to halve the number of source lines. (Patent Documents 1 to 3).

JP 2007-128035 A JP-A-10-171212 JP 2003-255911 A

  When the above-described method for halving the number of source lines is performed, the number of gate lines is correspondingly doubled. This means that the number of gate driver ICs is doubled, and the cost reduction effect due to the reduction of the source driver ICs is reduced. In order to maximize the cost reduction effect due to the reduction of the source driver IC, it is conceivable that a gate line driving circuit is formed in the liquid crystal panel and the gate driver IC is not used.

  Although efforts have been made to improve the driving capability of this gate line driving circuit, the driving capability of the gate line is inferior to an IC made of a crystalline silicon transistor. On the other hand, in the above configuration in which the source wiring is halved, it is necessary to perform writing to the pixel at a cycle twice that of a widely known active matrix circuit driving method, due to a decrease in the driving capability of the gate line. It becomes difficult to turn on / off the TFT at a high speed, resulting in insufficient writing to the pixel.

  In order to solve this problem, a gate activation period (meaning a voltage at which the connected TFT is turned on) is provided before the voltage to be originally written is applied, and as a result, driving is performed while overlapping the gate activation period. A method (overlap scan method) is well known (Patent Document 1). However, when this method is used, due to the coupling with the gate wiring, even if a uniform voltage is applied to all the pixels in the display area due to the difference in TFT arrangement, the charge voltage to the liquid crystal cell is different. As a result, a uniform display cannot be obtained.

  For example, as shown in FIG. 4 of Patent Document 2, even if the same gradation with the same polarity is written, the pixel connected to the G1 line with the TFT is parasitic with the G1 line at the timing when the gate selection signal is turned off. A voltage drop called feedthrough occurs for the capacity (not shown), and then feedthrough occurs again for the holding capacity generated with the G2 line at the timing when the G2 line is turned off. Voltage drop occurs in the pixel charging voltage. On the other hand, a pixel connected to the G2 line by TFT only has a feedthrough due to a parasitic capacitance with the G2 line (not shown) at the timing when the gate selection signal is turned off. Similarly, in subsequent G3, G4,..., A pixel in which feedthrough occurs twice and a pixel in which it occurs once occur depending on the arrangement position of the TFT with respect to the gate wiring, and uniform display cannot be obtained.

  In Patent Document 1, in order to perform uniform display by the overlap scan method, a source wiring drive voltage (pixel writing voltage) application period that is a source driver IC output is 1H (H is a horizontal period, and H is hereinafter referred to as a horizontal period). A method of controlling the length to be longer or shorter than ½ has been proposed. However, this method does not eliminate the difference in pixel charging voltage caused by the coupling effect with the gate wiring.

  Patent Document 3 proposes a method for increasing or decreasing the pixel writing voltage every 1H in order to compensate for the difference in the pixel charging voltage. However, the method described in Patent Document 3 only increases or decreases the amplitude of the drive voltage, does not correct the center voltage of the amplitude, and does not solve the problem of flicker and burn-in.

  In the liquid crystal display panel in which the number of source lines is reduced to half of the horizontal resolution × 3 (R, G, B) and the number of gate lines is doubled to the vertical resolution, driving is performed while overlapping the gate-on period. The purpose is to eliminate display defects such as display non-uniformity, flicker, and burn-in.

In the liquid crystal display device according to the present invention, a plurality of pixel electrodes surrounded by a plurality of scanning lines and a plurality of data lines are arranged in a matrix, and a plurality of thin film transistors connected to the pixel electrodes are supplied by the scanning lines. A matrix substrate that is controlled in conduction by a gate selection signal and supplies a pixel writing voltage supplied by the data wiring to the pixel electrode through the thin film transistor, and a liquid crystal layer sandwiched between the matrix substrate and the matrix substrate. A counter driver substrate, a gate driver circuit section that supplies the gate selection signal to the scanning wiring, a source driver circuit section that supplies the pixel writing voltage to the data wiring, and the source driver circuit section A display control data signal is output, and a horizontal scanning control signal is output to the gate driver circuit unit. And Lee timing controller, in this type the tone control signal from the timing controller, a liquid crystal display device including a gradation voltage setting circuit for outputting a gray scale reference voltage, to the source driver circuit portion, the matrix substrate, the line The plurality of pixel electrodes arranged in the direction are composed of a first pixel electrode and a second pixel electrode adjacent to each other in the row direction across the arbitrary data wiring, and the plurality of thin film transistors include the arbitrary data wiring A first thin film transistor that drives the first pixel electrode and a second thin film transistor that drives the second pixel electrode, and the plurality of scanning wirings are connected to one of the plurality of scanning wirings. It comprises a first and a scan line, the second and the scanning line connected to the second thin film transistor connected to the first thin film transistor, the first The pixel electrode has a storage capacitor connected to the second scan line, the second pixel electrode has a storage capacitor connected to the first scan lines, further the gate selection signal Consists of a first gate selection signal supplied to the first scanning wiring and a second gate selection signal supplied to the second scanning wiring, and the first gate selection signal is Activated prior to the activation of the second gate selection signal, the activation period of the first gate selection signal and the activation period of the second gate selection signal are activated simultaneously for a predetermined period. The first gate selection signal is deactivated prior to the deactivation of the second gate selection signal, and the gradation voltage setting circuit further comprises two kinds of levels. Adjustment reference voltage setting, synchronized with the overlap selection period The setting is switched to compensate for a change in the potential held in the first pixel electrode corresponding to the deactivation of the second gate selection signal .

In the present invention, the number of source lines is half of the horizontal resolution × 3 (R, G, B), and the pixel arrangement with respect to the scan lines even in the case of gate overlap scan driving in a liquid crystal display panel having a Cs on- gate pixel structure. It is possible to offset the difference in the feedthrough due to the difference in display quality and prevent the display quality from deteriorating.

1 is a configuration diagram of a liquid crystal display device according to Embodiment 1 of the present invention. Configuration diagram of the liquid crystal panel in FIG. Drive timing chart of liquid crystal panel in Embodiment 1 according to the present invention Grayscale voltage setting circuit configuration diagram shown in FIG. Timing chart for driving liquid crystal panel according to the second embodiment of the present invention Grayscale voltage setting circuit configuration diagram according to the second embodiment of the present invention The block diagram of the liquid crystal panel in the modification 1 of Embodiment 2 which concerns on this invention The block diagram of the liquid crystal display device in the modification 2 of Embodiment 2 which concerns on this invention

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In order to avoid redundant descriptions, the same reference numerals are given to elements having the same or corresponding functions in each drawing.

Embodiment 1 FIG.
FIG. 1 shows a system configuration diagram of a liquid crystal display device 1 according to Embodiment 1 of the present invention. In FIG. 1, a liquid crystal panel 10 includes an active matrix substrate in which a plurality of pixels are arranged in a matrix at a crossing portion with a plurality of source lines (data lines) 102 and a plurality of gate lines (scanning lines) 101 and 111 as one substrate. 11 and a counter substrate (not shown) which is the other substrate opposite to the substrate 11 are bonded together with a predetermined gap, and a liquid crystal layer (not shown) is sandwiched between the gaps.

Further, the gate wirings _{G 1} of the liquid crystal panel _{10, ‥‥, G y, G} y + 1, ‥‥, the gate driver IC group 12 is connected as the gate line drive circuit portion at the end of the _{G 2m,} the source line _S 1, .., S _x , S _{x + 1} ,..., S _{n / 2} are connected to a source driver IC group 13 as a source wiring drive circuit unit, and each IC group is controlled by a timing controller 14.

  Here, the timing controller 14 performs processing such as timing adjustment from a display data signal input from a display controller of an external device (not shown) and a display control signal composed of a display clock, a horizontal synchronization signal, a vertical synchronization signal, etc. This is a circuit that outputs a display control data signal 15 including display data to be displayed on the liquid crystal panel 10 and a timing control signal to the IC group 13 and outputs a horizontal scanning control signal 16 to the gate driver IC group 12.

  The gradation voltage setting circuit 17 receives gradation voltage power supply 19 from a DC / DC circuit 18 that supplies drive voltages to the gate driver IC group 12 and source driver IC group 13, and gradation control that is input from the timing controller 14. In response to the signal 20, the gradation reference voltage 21 is output to the source driver IC group 13. The source driver IC group 13 applies a pixel write voltage to the source line based on the gradation reference voltage 21 in accordance with the display data included in the display control data signal 15.

Next, FIG. 2 shows a detailed view of a partial display region in the liquid crystal panel 10 constituted by a pixel matrix of m rows and n columns. Here, for simplification of description, the gate wiring 101 (G _y , G _{y + 2} ) and the gate wiring 111 (G _{y + 1} , G _{y + 3} ) and the source wiring 102 (S _x , S _{x + 1} , S _{x + 2} ) are first connected. The configuration of the pixel group 103 including the specific two pixel electrodes 105 and 115 will be described in detail using the pixel matrix portion.

The pixel group 103 illustrated by a broken line in FIG. 2 includes two pixels, and is arranged so as to straddle _one source wiring 102 (S _{x + 1} ). The source wiring and two gate wirings 101 ( Located at the intersection of G _y ) and 111 (G _{y + 1} ), the TFT 104 and the pixel electrode 105 are arranged as switching elements on the left half of the pixel group 103, and the TFT 114 and the pixel electrode 115 are arranged on the right half. . A gate wiring 101 (G _y ) is connected to the gate electrode of the left TFT 104, a source wiring 102 (S _{x + 1} ) is connected to the source electrode, and a pixel electrode 105 is connected to the drain electrode. The pixel electrode 105 forms a liquid crystal capacitor with the liquid crystal layer 108 sandwiched between the counter electrode 107 which is an electrode of the counter substrate, and a gate selection signal applied to the gate wiring 101 (G _y ) is “High”. When the "level" (activation level) is reached, the TFT 104 is turned on, and the potential of the source wiring 102 (S _{x + 1} ) at that time, that is, the pixel write voltage is written to the pixel electrode 105. Activation level), the TFT 104 is turned off, and the written potential is held in the capacitor for one frame period or more.

On the other hand, the gate wiring 111 (G _{y + 1} ) is connected to the gate electrode of the right TFT 114, the source wiring 102 (S _{x + 1} ) is connected to the source electrode, and the pixel electrode 115 is connected to the drain electrode. Further, the pixel electrode 115 forms a liquid crystal capacitor with the liquid crystal layer 118 interposed between the counter electrode 117 which is an electrode of the counter substrate, and a gate selection signal applied to the gate wiring 111 (G _{y + 1} ) is “High”. The TFT 114 is turned on at the “level”, the potential of the source wiring 102 (S _{x + 1} ) at that time, that is, the pixel write voltage is written to the pixel electrode 115, and after 1H, the gate selection signal becomes the “Low” level, and the TFT 114 is turned off. The written potential is held in the capacitor for one frame period or more. Here, the pixel electrode 105 or 115 functions as a minimum unit for displaying an image on the liquid crystal panel 10.

  Further, as shown in FIG. 1, the liquid crystal panel 10 includes a matrix substrate 11 in which a plurality of pixel groups 103 including TFTs 104 and 114, pixel electrodes 105 and 115, gate wirings 101 and 111, and source wirings 102 are arranged in a matrix. And a counter substrate (not shown) provided with the counter electrodes 107 and 117 have a display area of m rows and n columns in which liquid crystal is sealed. The counter electrodes 107 and 117 are separately displayed for convenience as shown in FIG. 2, but are transparent electrodes arranged in a single body on the counter substrate.

  Next, the configuration of the liquid crystal panel 10 that is a feature of the present embodiment will be described in detail. In the matrix substrate 11 which is one substrate of the liquid crystal panel 10, the drain electrodes of the TFTs 104 and 114 corresponding to the pixel electrodes 105 and 115 constituting the pixel group 103 are connected to the source electrodes of the TFTs 104 and 114, respectively. Both are connected to the source wiring 102 (source wiring shared structure). In addition, the gate electrode of one TFT 104 is connected to the gate wiring 101, and the gate electrode of the other TFT 114 is connected to the gate wiring 111. Further, as apparent from FIG. 2, among the plurality of pixel electrodes in which the gate lines 101 and 111 are arranged in a matrix, the gate lines are arranged above and below the pixel electrodes 105 and 115 arranged in the row direction. The wiring does not intersect between the connection line to the gate electrode and the gate wiring 101 or 111.

  The pixel electrodes 105 and 115 are connected to the gate wiring to which the TFTs 104 and 114 are connected and the adjacent gate wiring on the opposite side across the pixel electrodes 105 and 115 (the gate electrode of the TFT 104 is connected to the upper gate wiring 101). The storage capacitors 106 and 116 are formed between the lower gate wiring 111 and the upper gate wiring 101 where the gate of the TFT 114 is connected to the lower gate wiring 111. Further, although not shown, parasitic capacitance (gate / drain capacitance: Cgd) exists between the pixel electrode 105 and the TFT 104 and between the pixel electrode 115 and the TFT 114 with respect to the gate wiring and electrode connected thereto. In this way, the pixel group 103 is configured, and similar pixel groups 103 are arranged in a matrix on the entire matrix substrate 11. With the above-described connection, each TFT in the pixel group can be independently controlled to be on or off.

That is, as shown in FIGS. 2 and 3, the liquid crystal panel 10 of the source wiring shared structure, different gate lines _{G 1} to one _{another, ‥‥, G y, G y} + 1, ‥‥, gates mutually different supplied from _{G 2m} independently is selected by the selection signal, the same source line S _1, ‥‥, provided with a plurality of _{S x, S x + 1,} ‥‥ S n / 2 pixel group 103 for charging by time division pixel writing potential from.

In FIG. 2, pixels (first pixels) arranged in odd columns are each odd gate wiring (first scanning wiring) 101 (G ₁ ,..., G _y , G _{y + 2} , G _{y + 4} ,... G _2m−1 ) and the TFT 104 (first TFT) connected to the left side of each source wiring 102 (S ₁ ,..., S _x , S _{x + 1} , S _{x + 2} ,..., S _{n / 2} ) , And odd-numbered first pixel electrodes 105 connected to the TFTs 104. The source electrode of the TFT 104 is branched and connected from the left side of each of the source lines 102, and the drain electrode is connected to the first pixel electrode 105. The gate electrode of the TFT 104 is connected to each odd-numbered gate wiring 101.

Pixels (second pixels) arranged in even columns are connected to each even gate wiring (second scanning wiring) 111 (G ₂ ,..., G _{y + 1} , G _{y + 3} ,..., G _2m ). A TFT 114 (second TFT) connected to the right side of each of the source wirings 102 and the second pixel electrodes 115 in even columns connected to the TFTs 114 are included. The source electrode of the TFT 114 is branched and connected from the right side of each source wiring 102, and the drain electrode is connected to the second pixel electrode 115. The gate electrode of the TFT 114 is connected to each even gate wiring 111.

As shown in FIG. 1, each gate wiring 101 and 111 (G ₁ , G ₂ ,..., G _y , G _{y + 1} , G _{y + 2} , G _{y + 3} , G _{y + 4} ,..., G _2m−1 , G _2m ) Is connected to an output terminal (not shown) of the gate driver IC group 12, and each source wiring 102 is connected to an output terminal (not shown) of the source driver IC group 13. In this way, an independent source line driving voltage (pixel writing voltage) can be applied to each of the gate line and the source line.

Next, a method for driving the liquid crystal panel of the present embodiment will be described in detail with reference to FIG. FIG. 3 is a drive timing chart of the liquid crystal panel according to the present embodiment. In this embodiment, the above-described gate overlap scan method is employed, and as shown in FIG. 3, each odd-numbered gate wiring 101 (G ₁ ,..., G _y , G _{y + 2} , G _{y + 4} ,. G _2m-1 ) includes an odd gate selection signal (first gate selection signal) VG ₁ ,..., VG _y ,. _{y + 2} ,..., VG _2m−1 are sequentially supplied. Each even gate wiring 111 (G ₂ ,..., G _{y + 1} , G _{y + 3} ,..., G _2m ) has an even gate selection signal that holds a 1H “High” TFT on voltage by the gate driver IC group 12. (second gate selection _{signal) VG 2, ‥‥, VG y} + 1, ‥‥ VG 2m) are sequentially supplied. There is no overlap period between odd gate selection signals (for example, between signals VG _y and VG _{y + 2} ) or even gate selection signals (for example, between signals VG _{y + 1} and VG _{y + 3} ), but adjacent odd gate selection signals. And an even gate selection signal (for example, between signals VG _y and VG _{y + 1,} between VG _{y + 1} and VG _{y + 2 and} between VG _{y + 2} and VG _{y + 3 in FIG. 3} ), there is an overlap period (overlap selection period) of only H / 2. Exists.

Next, driving of the source wiring 102 will be described. First, in order to drive, for example, a pixel in the y-th row of the liquid crystal panel 10, the gate selection signal VG _y is applied to the y-th output (gate wiring G _y ) of the gate wiring 101 to turn on the TFT 104 for at least the H / 2 period. Put it in a state. Actually, by adopting the above-described overlap scan method, the gate wiring G _y−1 ((pixel 105 writing period) = t ₃ −t ₄ period) precedes the original y row writing period (“pixel 105 writing period” = t ₃ −t ₄ period). The gate selection signal Vgy is activated at time t ₁ within the activation period (not shown), and the “High” time length is 1H period. After the gate selection signal _{VG y-1} becomes "Low" at _{t 2} when in this state, at the same time the gate selection signal _{VG y + 1} of the following even gate lines _{G y + 1} is "High", and the source at the next _{t 3} time points The driver IC group applies the source wiring drive voltage (pixel writing voltage) corresponding to each odd column pixel in the y row to all the source wirings 102 at the same time, and all the odd column pixel electrodes (first electrodes) in the y row. A pixel writing voltage is written into the pixel electrode). The gate selection signal VG _y becomes “Low” level at time t ₄ after H / 2 has elapsed from time t ₂ , the TFT 104 (first TFT) is turned off, and the odd column pixel electrode 105 disposed on the left side of the source wiring The written pixel writing voltage is held in the liquid crystal capacitor for one frame period or longer (see “potential waveform of the pixel 105” shown by a broken line in FIG. 3). At this time, as described above, the TFT 114 (second TFT) connected to all even-numbered column pixel electrodes (second pixel electrodes) in the y-th row also receives the gate selection signal VG _{y + 1} of the G _{y + 1} output of the gate wiring 111. Since it is “High”, it is in the ON state, but since the TFT 114 is in a transition period from OFF to ON, the potential of the even-numbered column pixel electrode 115 is indefinite (“the potential waveform of the pixel 115 shown by a broken line in FIG. "reference).

Next, after the gate selection signal VG _y becomes “Low” level at time t ₄ , the next even gate selection signal VG _{y + 1} becomes “High” at the same time, and the source wiring corresponding to each even column pixel 115 at time t _5. A driving voltage (pixel writing voltage) is applied all at once, and the pixel writing voltage is written to all even-numbered column pixel electrodes 115 (second pixel electrodes) in the y-th row (“pixel 115 writing period” = t ₅ −t ₆ periods). Then the gate selection signal _{VG y + 1} at _{t 6} the time of the H / 2 has elapsed from _{t 4} time becomes "Low" level, TFT 114 (second TFT) are turned off, the written pixel writing voltage one frame period or more liquid crystal The capacitance is held (see “the potential waveform of the pixel 115” indicated by a broken line in FIG. 3). In this way, all the pixels in the first row are driven in the 1H period. The above is repeated, and gate selection voltages are sequentially applied to the gate wirings 101 and 111 of the liquid crystal panel 10 while overlapping for the H / 2 period, thereby driving all the pixels (line sequential driving method).

  As a result, by using the above means, in the liquid crystal matrix panel having pixels of m rows and n columns, the number of gate lines is doubled (2 m) compared to the conventional example, and the number of source lines on one side is halved. (N / 2).

Next, the driving timing of the source wiring 102 of the liquid crystal panel 10 will be described in detail with reference to FIG. In FIG. 3, a signal VS _{x + 1} which is a driving waveform of the source wiring 102 (S _{x + 1} ) corresponds to the pixel group 103 arranged in the y-th line so as to straddle the source wiring. FIG. 3 shows a case where the same gradation and the same gradation are written on the entire screen on the liquid crystal panel 10 in order to simplify the description. FIG. 3 shows an example in which + polarity is written to all pixels in an odd frame, such as a frame inversion driving method. Although not shown, in the next frame, negative polarity is written in all pixels. As described above, the gate selection method of the gate wiring is set to “High” before H / 2 before the timing t _{2 when} writing should be started, and the two gate wirings always overlap each other for “H / 2” period. It is controlled to become "."

In FIG. 3, when the potential indicated by the alternate long and short dash line is a pixel write target voltage for display data, each odd-numbered gate wiring 101 (G ₁ ,..., G _y , G _{y + 2} , G _{y + 4} ,... G _2m−1 ). In the TFT 104 to which the gate electrode is connected, the voltage applied to the pixel electrode 105 connected to the drain electrode of the TFT 104 is apparent from the “potential waveform of the pixels 105 and 125” shown by a broken line. The first feedthrough voltage Vf ₁ due to the influence of the gate / drain capacitance Cgd (not shown) and the even gate wirings 111 (G ₂ ,..., G _{y + 1} , G _{y + 3} ,..., G _2m adjacent to the pixel electrode 105. ), The second feedthrough voltage Vf ₂ generated when the gate selection signal of the next stage falls to the “Low” level is generated.

On the other hand, at TFT114 is connected to the even gate lines 111, the voltage applied to the pixel electrode 115 connected to the drain electrode, the first feed-through voltage Vf ₁ is generated in the same manner, the pixel The second feedthrough due to the influence of the storage capacitor 116 provided between the odd-numbered gate wiring 101 adjacent to the electrode 115 does not occur (see “the potential waveform of the pixel 115” indicated by the broken line in FIG. 3). This is a capacitance in which the storage capacitor 116 of the pixel electrode 115 is provided between the odd-numbered gate wiring 101 in the previous stage, and the odd-numbered gate wiring 101 is “at time t ₄ before the pixel electrode 115 is driven”. This is because it becomes “Low” level and does not change for one frame period thereafter.

The first feedthrough voltage Vf ₁ is a voltage that has substantially the same value when the odd-numbered gate wiring 101 is activated and when the even-numbered gate wiring 111 is activated, and the common electrode voltage applied to the common electrode. It is compensated by a known method for shifting the DC voltage of Vcom.

On the other hand, in order to compensate for the second feedthrough voltage Vf ₂ indicated by “the potential waveform of the pixel 105” and “the potential waveform of the pixel 125” represented by broken lines in FIG. only the pixel electrode 105 that is driven by, may be applied to feedthrough compensation voltage for canceling the second feed-through voltage Vf _2. Therefore, a second feedthrough voltage compensation circuit is provided, and in addition to the pixel write target voltage on the source line 102 only when the pixel electrode 105 is driven, a voltage (feedthrough compensation voltage) substantially equivalent to the second feedthrough voltage Vf ₂ is provided. An increased pixel writing voltage is applied. The second feedthrough voltage compensation circuit is controlled by the gradation control signal 20 shown by the waveform Vsw in FIG. When the gradation control signal 20 is “High”, the second feedthrough voltage Vf ₂ is compensated. When the gradation control signal 20 is “Low”, no compensation is performed. Therefore, the gradation control signal 20 is a signal that becomes “High” in synchronization with the driving of the pixel electrode 105.

In the present embodiment, as shown in FIG. 4, each gradation voltage output unit Vref ₀ , Vref ₁ , Vref ₂ ,..., Vref is used by using a set of ladder resistors 201 in the gradation voltage setting circuit 17. _(Q-2) , Vref _(q-1) , and Vref _q are provided, and each gradation reference voltage 21 is output to the source driver IC group 13. Here, q is a natural number of 1 or more, and depends on the gradation specification of the source driver IC. Further, the analog switch 200 is used as a switch element controlled by the gradation control signal 20 (waveform Vsw), and selection as to whether or not to pull up from the middle point Vm of the ladder resistor 201 to the gradation voltage power source via a resistor. To be able to. Here, the analog switch 200 is turned on when the pixel electrode 105 is connected to the source wiring 102 by the activation of the odd-numbered gate wiring 101 and a pixel write voltage corresponding to the source wiring 102 is applied, and the even-numbered gate wiring 111. When the pixel electrode 115 is connected to the source wiring 102 by activation of the pixel and the pixel writing voltage corresponding to the source wiring 102 is applied, it is off.

When the gradation control signal 20 (waveform Vsw) becomes “High” and the analog switch 200 is turned on, that is, when the odd-numbered gate wiring 101 is activated, the compensation of the second feedthrough voltage Vf ₂ is taken into consideration. Each gradation reference voltage 21 is set to be higher by about the second feedthrough voltage Vf by ₂ . Here, in this embodiment, a normally white liquid crystal mode is adopted, and in the case of high gradation display (white display), the voltage from the gradation voltage output unit near the middle point Vm of the ladder resistor 201 is selectively used. On the other hand, when the gray scale display (black display) is used, a high drive voltage is required to select and use the voltage from the gray scale voltage output section in the vicinity of both ends of the ladder resistor 201.

Further, a second feed-through voltage Vf _2, the liquid crystal capacitance (have That gradation dependency) voltage to have a dependency applied to the pixel electrode, the second feed-through voltage Vf ₂ is, The voltage is set to be larger than that at the time of low gradation.

  In this way, by applying different feedthrough compensation voltages for the pixel electrode 105 and the pixel electrode 115 to each pixel, the alternating current component (amplitude) and direct current component (average value) of the final liquid crystal applied voltage are simultaneously aligned. It is possible to eliminate display non-uniformity, flicker, and burn-in.

In the configuration of the gradation voltage setting circuit 17, the analog switch 200 controlled by the gradation control signal 20 is used to pull up from the middle point Vm of the ladder resistor 201 to the gradation voltage power source via a resistor. Although the circuit configuration is adopted, as another embodiment, a circuit configuration in which the midpoint of the ladder resistor is pulled down from the midpoint of the ladder resistor to the ground power supply GND via a resistor is adopted, and the logic of the gradation control signal is the same as that of the first embodiment. An inverted configuration may be used. In this case, when the analog switch is turned off, the second feed-through voltage Vf ₂ is compensated, setting the resistance value of the ladder resistance and the pull-down resistor so as not compensated when on.

Embodiment 2. FIG.
In the present embodiment, a 1 × 2 column dot inversion driving method is employed as the pixel driving scheme of the liquid crystal panel 10. Other system configurations of the liquid crystal display device 1, the configuration of the liquid crystal panel 10, and the like are the same as those in the first embodiment.

A method for driving the liquid crystal panel of this embodiment will be described in detail with reference to FIG. FIG. 5 is a drive timing chart of the liquid crystal panel according to the present embodiment. This embodiment also adopts a gate overlap scan method as in the second embodiment described above, the gate lines _{G 1, ‥‥, G y,} G y + 1, ‥‥, is applied to the G _2m The gate selection signals VG ₁ ,..., VG _y , VG _{y + 1} , VG _{y + 2} , VG _{y + 3} ,..., _VG2m are the same as those in FIG.

Next, driving of the source wiring 102 will be described. As described above, since the 1 row × 2 column dot inversion driving method is adopted, the polarity of the source wiring 102 (S _{x + 1} ) is positive / negative for every 1H as shown by the waveform VS _{x + 1} in FIG. Driven to invert. In addition, the pixel switching voltage signal switching timing and the like are the same as those in the first embodiment, and the details are omitted.

In FIG. 5, when the potential indicated by the alternate long and short dash line is a pixel write target voltage for display data, each odd-numbered gate wiring (first scanning wiring) 101 (G ₁ ,..., G _y , G _{y + 2} , G _{y + 4} , The voltage written to the pixel electrode 105 connected to the drain electrode via the TFT 104 to which the gate electrode is connected to G _2m-1 ) is the first due to the influence of the gate / drain capacitance Cgd of the TFT 104. Provided between the feedthrough voltage Vf ₁ and each even-numbered gate wiring (second scanning wiring) 111 (G ₂ ,..., G _{y + 1} , G _{y + 3} ,..., G _2m ) adjacent to the pixel electrode. second feed-through voltage Vf ₂ occurs occurring during the falling of the "Low" level of the next even-numbered gate lines under the influence of the storage capacitor 106 (shown in dashed lines in FIG. 5 "pixel 105 125 of the potential waveform "reference).

On the other hand, the voltage written to the pixel electrode 115 connected to the drain electrode via the TFT 114 connected to the even-numbered gate wiring 111 is generated in the same manner as the first feedthrough voltage Vf _1. The second feedthrough due to the influence of the storage capacitor 116 provided between the odd-numbered gate wiring 101 adjacent to the electrode does not occur (see “the potential waveform of the pixels 115 and 135” shown by the broken line in FIG. 5). This is a capacitor in which the storage capacitor 116 of the pixel electrode 115 is provided between the adjacent odd-numbered gate wiring 101 and the odd-numbered gate wiring 101 before the pixel electrode 115 is driven, at time t _4. This is because the signal becomes “Low” level and does not change for one frame period thereafter.

The first feedthrough voltage Vf ₁ is a voltage having substantially the same value when the odd-numbered gate wiring 101 is activated and when the even-numbered gate wiring 111 is activated, as in the first embodiment. It is compensated by a known method of shifting the DC voltage of the counter electrode voltage Vcom applied to the electrodes.

On the other hand, in order to compensate for the second feedthrough voltage Vf ₂ indicated by “the potential waveform of the pixel 105” and “the potential waveform of the pixel 125” represented by broken lines in FIG. only in the pixel electrode 105 that is driven by, it may be applied to the second feed-through compensation voltage for canceling the second feed-through voltage Vf _2. For this reason, a second feedthrough voltage compensation circuit is provided, and increases only by a voltage (feedthrough compensation voltage) corresponding to the second feedthrough voltage Vf ₂ in addition to the pixel write target voltage on the source line 102 only when the pixel electrode 105 is driven. Apply the pixel writing voltage. The second feedthrough voltage compensation circuit is controlled by the above-described gradation control signal 20 indicated by the signal Vsw in FIG. When the gradation control signal 20 is “High”, the second feedthrough voltage Vf ₂ is compensated. When the gradation control signal 20 is “Low”, no compensation is performed. Therefore, the gradation control signal 20 is a signal that becomes “High” in synchronization with the driving of the pixel electrode 105.

FIG. 6 shows a configuration diagram of the gradation voltage setting circuit 17 in the present embodiment. As shown in FIG. 6, two sets of ladder resistors 201 and 202 are arranged in the gradation voltage setting circuit 17, and each gradation voltage output unit Vref ₀ , Vref ₁ ,. An analog switch 200 is inserted as a switch element controlled by the gradation control signal 20 (Vsw) in Vref _(q-1) and Vref _q , and the gradation voltage generated by either the ladder resistor 201 or the ladder resistor 202 The gradation voltage is switched by selecting, and two different kinds of gradation reference voltages 21 are set. Here, q is a natural number of 1 or more, and depends on the gradation specification of the source driver IC. The ladder resistor 201 side is for the pixel electrode 105 driven by the activation of the odd-numbered gate wiring 101, and the ladder resistance 202 side is for the pixel electrode 115 driven by the activation of the even-numbered gate wiring 111.

Ladder resistor 202, taking into account the second compensation of feedthrough voltage Vf ₂ described above, the gradation setting voltage is set to a second feed-through voltage Vf ₂ minutes increased compared to that of the ladder resistor 201. Second feed-through voltage Vf _2, since the liquid crystal capacitance has a dependence on the voltage applied to the pixel electrode (i.e. has a gradation dependency) are different for each gradation, correspondingly If the resistance values of the ladder resistors 201 and 201 are appropriately set, the optimum voltage setting of the gradation reference voltage 21 and the second feedthrough voltage Vf ₂ compensation can be performed. As a result, the alternating current component (amplitude) and direct current component (average value) of the final liquid crystal applied voltage can be aligned at the same time, and display non-uniformity, flicker, and image sticking can be eliminated.

Modification 1
FIG. 2 is merely an example of the pixel arrangement configuration of the active matrix substrate 11. The arrangement of TFTs in the pixel may be regularly arranged alternately in an upper arrangement and a lower arrangement as shown in FIG. As in (a) and (b), there are cases where they are aligned with the lower side, the lower side, the upper side, and the upper side, and are not limited.

Modification 2
FIG. 8 illustrates an embodiment in which a gate wiring driving circuit 120 is formed as a gate driver circuit portion in the liquid crystal panel 10 and no gate driver IC is used. If the configuration of the matrix wiring that reduces the number of source wirings by halving the number of source wirings by using one source wiring shown in Embodiments 1 and 2 in common with two pixels, the number of gate wirings is doubled. This means that the number of gate driver ICs is doubled, and the cost reduction effect due to halving of the source driver ICs is reduced. In order to make the most of the cost reduction effect of the source driver IC reduction, it is conceivable to form the gate wiring drive circuit 120 in the liquid crystal panel 10 as shown in FIG. Various efforts have been made to improve the driving capability of the gate wiring driving circuit 120, but the driving capability is reduced as compared with an IC made of crystalline silicon. By adopting the gate overlap driving method described above, even if writing to the pixel is performed twice as long as the conventional method (writing period is H / 2), insufficient writing to the pixel is avoided. can do.

  In the first embodiment, the frame inversion driving method is exemplified as an example of the pixel driving scheme of the liquid crystal panel. Furthermore, in the second embodiment, the 1 × 2 dot inversion driving method is exemplified, but the present invention can be applied to other driving schemes, and the pixel writing voltage itself written to each pixel is displayed on the liquid crystal panel. Needless to say, it depends on the display data.

  In the first and second embodiments described above, the configuration of the liquid crystal panel in which the counter electrode opposed to the pixel electrode is disposed on the counter substrate is illustrated. However, the counter electrode is not necessarily disposed on the counter substrate. A configuration in which the counter electrode is disposed on the active matrix substrate side, such as an FFS structure, may be employed.

  In the above-described first and second embodiments, the pixel electrode is exemplified by the Cs on-gate pixel structure in which the storage capacitor Cs is formed between the pixel electrode and the adjacent gate wiring located on the opposite side of the TFT. The present invention also relates to a pixel structure of a storage capacitor electrode common wiring system in which a common wiring connected in common to a capacitor is arranged in parallel with a gate wiring or a source wiring and a common electrode potential Vcom is supplied to the common wiring. It can be adopted. In this case, since the second feedthrough voltage is mainly caused by the parasitic capacitance between the next-stage gate wiring adjacent to the pixel electrode, the voltage to be corrected is smaller than that in the case of the Cs on-gate method.

  In the above-described overlap scan method, the period of overlapping activation between the odd-numbered gate wiring and the even-numbered gate wiring has been described as H / 2. However, this period is not particularly required to be H / 2, and the TFT The period may be longer than a predetermined length that can sufficiently drive the pixel electrode.

10 Liquid crystal panel 11 Matrix substrate 12 Gate driver IC group 13 Source driver IC group 14 Timing controller 15 Display control data signal 16 Horizontal scanning control signal 17 Gradation voltage setting circuit 20 Gradation control signal (Vsw)
21 Gradation reference voltage (Vref)
_{101, G 1, G y,} G y + 2, G y + 4, G 2m-1 odd gate lines (odd gate lines)
102 Source wiring (data wiring)
103 Pixel group 104, 114 Thin film transistor (TFT)
105, 115 Pixel electrodes 106, 116 Retention capacitance (Cs)
107, 117 Counter electrode 108, 118 Liquid crystal layer 111, G ₂ , G _{y + 1} , G _{y + 3} , G _2m Even gate wiring (even gate wiring)
120 gate line drive circuit 200 analog switch 201, 202 ladder resistor _{VG 1, VG y, VG y} + 1, VG y + 2, VG y + 3, VG 2m-1, VG 2m gate selection signal _{VS x + 1} pixel write voltage

Claims (4)

A plurality of pixel electrodes surrounded by a plurality of scan lines and a plurality of data lines are arranged in a matrix, and a plurality of thin film transistors connected to the pixel electrodes are conductively controlled by a gate selection signal supplied by the scan lines, A matrix substrate configured to supply a pixel writing voltage supplied by the data wiring to the pixel electrode through the thin film transistor;
A counter substrate disposed opposite to the matrix substrate with a liquid crystal layer interposed therebetween ;
A gate driver circuit section for supplying the gate selection signal to the scanning wiring;
A source driver circuit section for supplying the pixel writing voltage to the data wiring;
A timing controller that outputs a display control data signal to the source driver circuit unit and outputs a horizontal scanning control signal to the gate driver circuit unit;
In a liquid crystal display device comprising: a gradation voltage setting circuit that inputs a gradation control signal from the timing controller and outputs a gradation reference voltage to the source driver circuit unit;
The matrix substrate is composed of a first pixel electrode and a second pixel electrode, in which a plurality of the pixel electrodes arranged in a row direction are adjacent to each other across the arbitrary data wiring in the row direction,
The plurality of thin film transistors are commonly connected to one of the arbitrary data lines, and a first thin film transistor that drives the first pixel electrode and a second thin film transistor that drives the second pixel electrode And consist of
The plurality of scanning wirings include a first scanning wiring for controlling the first thin film transistor and a second scanning wiring for controlling the second thin film transistor,
The first pixel electrode has a storage capacitor connected to the second scanning line, and the second pixel electrode has a storage capacitor connected to the first scanning line;
The gate selection signal includes a first gate selection signal supplied to the first scanning wiring and a second gate selection signal supplied to the second scanning wiring,
The first gate selection signal is activated prior to the activation of the second gate selection signal;
The activation period of the first gate selection signal and the activation period of the second gate selection signal have an overlapping selection period activated simultaneously for a predetermined period,
The first gate selection signal is deactivated prior to the deactivation of the second gate selection signal;
The gradation voltage setting circuit has two kinds of gradation reference voltage settings, and switches the setting in synchronization with the overlap selection period to cope with the deactivation of the second gate selection signal. A liquid crystal display device that compensates for a change in potential held by the first pixel electrode . The first scanning wiring is an odd scanning wiring, the second scanning wiring is an even scanning wiring, and the first scanning wiring is for a pixel column arranged in a row direction of pixel electrodes arranged in a matrix. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is disposed on an upper side, and the second scanning wiring is disposed on a lower side. 3. The liquid crystal display device according to claim 1, wherein the setting of the gradation reference voltage is switched by the gradation control signal output from the timing controller. 4. The liquid crystal display according to claim 1 , wherein a change in the potential held in the second pixel electrode corresponding to the deactivation of the first gate selection signal is not compensated. 5. apparatus.

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