JP4270442B2 - Display device and driving method thereof - Google Patents

Description

  The present invention relates to a display device such as an active matrix liquid crystal display device used in a display screen section of a mobile phone device, a liquid crystal television, a personal computer, and the like, and a driving method thereof.

  An active matrix liquid crystal display device will be described as a conventional active matrix display device of this type.

  FIG. 9 is a block diagram showing a configuration example of a main part of a conventional active matrix liquid crystal display device.

  As shown in FIG. 9, the active matrix liquid crystal display device 100 includes a data driver 101, a gate driver 102, and a display unit 103 on a transparent substrate such as a glass substrate or a quartz substrate.

  The data driver 101 receives a start pulse SPS and a clock signal CKS as control signals, and further receives a video signal Video.

  The gate driver 102 receives a start pulse SPG, a clock signal CKG, and the like as control signals.

The display unit 103 includes source bus lines Sbus ₁ , Sbus ₂ ,... Sbus _n as a plurality of data signal lines crossing each other (orthogonal) and gate bus lines G ₁ , G ₂ ,. ... and _{G m} are arranged, for each intersection position near these source bus lines Sbus and the gate bus line G, a thin film transistor 104 (hereinafter, referred to as TFT 104) and, connected to the pixel capacitor 105 is provided to It has been. A plurality of these TFTs 104 and pixel capacitors 105 are arranged in a matrix as a pixel portion.

That is, the gate terminal of each TFT 104 is connected to the gate bus lines G ₁ , G ₂ ,... G _n connected to the signal output unit of the gate driver 102, respectively. The source terminals of the TFTs 104 are connected to source bus lines Sbus ₁ , Sbus ₂ ,... Sbus _n connected to the signal output unit of the data driver 101, respectively. Furthermore, the drain terminal of each TFT 104 is connected to a pixel capacitor 105 comprising a liquid crystal capacitor as a display medium sandwiched between a pixel electrode made of a transparent electrode and its counter electrode, and an auxiliary capacitor (holding capacitor) not shown. Has been.

As shown in FIG. 10, the data driver 101 includes a sampling pulse generation circuit 101 a that sequentially outputs sampling signals Sam ₁ , Sam ₂ ... Sam _n based on the input control signal start pulse SPS and the drive signal CKS, Sampling signals Sam ₁ , Sam ₂ ... Sam _n output from the sampling pulse generation circuit 101 a are respectively input, and a sampling circuit 101 b that sequentially samples the input video signal Video based on each sampling signal Sam is provided. is doing.

  The operation of the conventional active matrix liquid crystal display device 100 configured as described above will be described below.

  FIG. 11 is a signal waveform diagram in a main part of the conventional active matrix liquid crystal display device 100 of FIG.

As shown in FIG. 11, first, when a start pulse SPS and a clock signal CKS, which are control signals, are input to the sampling pulse generation circuit 101a constituting the data driver 101, the video signal Video is sequentially transmitted from the sampling pulse generation circuit 101a. In order to perform sampling, sampling pulses Sam ₁ , Sam ₂ ... Sam _n are sequentially output to the sampling circuit 101b according to the clock signal CKS.

In this way, the sampling circuit 101b constituting the data driver 101, a video signal Video and are sequentially input, by the sampling pulses _{Sam 1, Sam 2 ··· Sam n} , the sampling circuit 101b and a display unit 103 A sample-and-hold circuit is formed in which the capacity of the source bus lines Sbus ₁ , Sbus ₂ ,... Sbus _n to be configured is a hold capacity (Cbus ₁ , Cbus ₂ ... Cbus _{n in} FIG. 9). Each display image data obtained by sequentially sampling the input video signal Video is written into the source bus line capacity (Cbus ₁ , Cbus ₂ ... Cbus _{n in} FIG. 1) as the hold capacity.

Each sampling pulse _{Sam 1,} Sam 2 respectively by · · · Sam _n, the source bus lines Sbus _1, Sbus _2, each display image data on · · · Sbus _n is sequentially written, further, the signal output of the gate driver 102 The gate bus line Gn connected to is active (Hi level). Each display image data written to the source bus lines Sbus ₁ , Sbus ₂ ,... Sbus _n through the TFT 104 connected to the gate bus line G _n is the row (selected) that forms the display unit 103. The data is sequentially stored in a plurality of pixel capacitors 105 in a row of gate bus lines (for one horizontal scanning period).

As described above, after the sampling of each display image data for one horizontal scanning period is completed and the display image data is written in each pixel capacitor 105, the gate bus line _Gn is inactive (Low level, G _{When n} becomes inactive, G _{n + 1} becomes active next, and display image data written in each pixel capacitor 105 is held until display image data for the next frame period is written. The

By repeating the same operation on the gate bus lines G _2, ... G _m , one frame of image display is performed on the display unit 103 of the liquid crystal display device.

  In the liquid crystal display device configured as described above, the liquid crystal molecules constituting the liquid crystal capacitor among the pixel capacitors 105 of the display unit 103 undergo polarization and deteriorate characteristics when a DC voltage is applied for a long time. For this reason, in general, the voltage applied to the liquid crystal capacitor has an alternating voltage waveform.

  FIG. 12 is a video signal waveform diagram showing an example of the video signal Video input to the data driver 101 when the polarity is inverted in one horizontal scanning period (during 1H inversion driving).

  As shown in FIG. 12, in the video signal Video, the original video signal is switched between positive polarity and negative polarity centering on the counter electrode potential Vc every horizontal period. The amplitude (voltage difference between Vp and Vn) is also amplified from the amplitude V in accordance with the characteristics of the liquid crystal.

  By such a driving operation, image display of the active matrix type liquid crystal display device 100 is performed. Here, the display image data written in the pixel capacitor 105, that is, the holding potential of the pixel capacitor 105 at the time of 1H inversion driving as shown in FIG.

As shown in FIG. 13, the display image data of the source bus line Sbus _x that is inverted by 1H to the pixel capacitance Cpix of the pixels Pix (x, y) and Pix (x, y + 1) adjacent in the vertical direction (column direction). Pixels Pix (x, y) and Pix (x, y + 1) when Vp and Vn (Vp and Vn have different polarities but display image data having the same voltage amplitude from the counter electrode potential Vc) are written. The pixel potential waveform is shown in FIG.

FIG. 14 shows pixel potential waveforms of Pix (x, y) of the pixel portion (1) and Pix (x, y + 1) of the pixel portion (2) adjacent to each other in the vertical direction (column direction) and the source bus line Sbus _x . A potential waveform is shown.

  In the active matrix liquid crystal display device 100, the drain terminal D of the TFT 104 constituting the display unit 103 is connected to the drain terminal D of the TFT 104 and the source bus line in addition to the pixel capacitor Cpix (pixel capacitor 105) as shown in FIG. There is a parasitic capacitance Csd between Sbus and a parasitic capacitance Cgd between the drain terminal of the TFT 104 and the gate bus line. Here, the pixel capacitance after the display image data Vp and Vn are written to the pixel capacitance Cpix of the pixel portion Pix (x, y) and the pixel portion Pix (x, y + 1) is because the TFT 104 is in the OFF state. In a floating state.

Therefore, the holding potential of the pixel capacitor varies by ΔV under the influence of the potential change (Vp−Vn) of the source bus lines Sbus _x and Sbus _{x + 1} for each horizontal scanning period. Where ΔV is approximately
ΔV = (Vp−Vn) × (Csd + Csd) / (Cpix + Csd + Csd + Cgd)
It becomes.

When the display period of one frame ends and the vertical blanking period starts, the potential of the source bus line Sbus _x in the final horizontal scanning period of the frame (the potential of Vn in the case of FIG. 14) is changed to the display period of the next frame. Holds until it begins. Therefore, the holding potential of the pixel capacitor Cpix in the pixel portion Pix (x, y) and the pixel portion Pix (x, y + 1) adjacent in the column direction is positive and negative by ΔV when viewed from the counter electrode potential Vc. Thus, the biased display image data is held.

  Such a problem occurs when the pixel holding potential is affected by the potential fluctuation of the source bus line Sbus during the display period via the parasitic capacitance Csd existing in each pixel portion constituting the display portion 103.

  In addition to this, as shown in FIG. 13, there is also a problem that the pixel holding potential is lowered due to the leakage current Ioff from the TFT 104 constituting each pixel portion.

As described above, in the vertical blanking period which is a period from the end of the last horizontal scanning period of the frame to the start of the display period of the next frame, the pixel units Pix (x, y) adjacent in the column direction and Looking at the relationship between the holding potential of each pixel capacitor Cpix and the potential of the source bus line Sbus _{x in} the pixel unit Pix (x, y + 1), as shown in FIG. 14, the pixel holding of each pixel unit Pix (x, y). A potential difference of Vp−ΔV−Vn is generated between the potential and the potential of the source bus line Sbus _x . For this reason, the leakage current Ioff from the TFT 104 constituting the pixel portion flows in the vertical blanking period, and the pixel holding potential is lowered.

On the other hand, there is no potential difference between the holding potential of the pixel capacitor Cpix and the potential of the source bus line Sbus _{x in} the pixel portion Pix (x, y + 1) as shown in FIG. For this reason, the leakage current Ioff of the TFT 104 constituting the pixel portion does not flow during the vertical blanking period, and the pixel holding potential does not decrease.

  In response to the potential fluctuation of the source bus line Sbus as described above, the problem of a decrease in the pixel holding potential caused by the parasitic capacitance Csd of the pixel portion and the leakage current Ioff from the TFT 104 constituting the pixel portion is Not only the holding potential of the pixel capacitor Cpix in the pixel unit Pix (x, y) and the pixel unit Pix (x, y + 1) but also every pixel connected to one gate bus line. Therefore, for example, when halftone solid display is performed, problems such as the occurrence of shading in the display image occur for each horizontal line.

  As conventional techniques for reducing such problems, for example, in Patent Documents 1 to 3, as shown in FIGS. 15 to 17, the average voltage of the source bus line potential is approximately equal to the counter voltage Vc during the blanking period. There has been proposed a method for alleviating the above problem by applying a potential to the source bus line so as to be a value.

In FIG. 15, in the vertical blanking period, the potential of the source bus line Sbus _x is set to the counter voltage Vc. At this time, in the vertical blanking period, a potential difference of Vp−ΔV / 2−Vc is generated between the pixel holding potential of the pixel portion Pix (x, y) and the potential of the source bus line Sbus _x , and the pixel portion Pix (x, A potential difference of Vc + ΔV / 2−Vn is generated between the pixel holding potential of y + 1) and the potential of the source bus line Sbus _x . Therefore, in the vertical blanking period, the decrease in the pixel holding potential caused by the parasitic capacitance Csd of the pixel portion and the leakage current of the TFT 104 as described above is reduced, and the decrease in the pixel holding potential is reduced for each horizontal line. It is possible to prevent the occurrence of bias.

In FIG. 16, in the vertical blanking period, the potential of the source bus line Sbus _x is inverted between Vp and Vn every horizontal scanning period, and the average voltage is the counter voltage Vc. At this time, in the vertical blanking period, the pixel holding potential of the pixel portion Pix (x, y) alternately changes between Vp and Vp−ΔV every horizontal scanning period, and the potential of the source bus line Sbus _x Is alternately changed between 0 and Vp−ΔV−Vn every horizontal scanning period. Further, the pixel holding potential of the pixel portion Pix (x, y + 1) alternately changes between Vn + ΔV and Vn every horizontal scanning period, and the potential difference with the potential of the source bus line Sbus _x is changed every horizontal scanning period. It alternates between Vp + ΔV−Vn and 0. Therefore, in the vertical blanking period, the decrease in the pixel holding potential caused by the parasitic capacitance Csd of the pixel portion and the leakage current of the TFT 104 as described above is reduced, and the decrease in the pixel holding potential is reduced for each horizontal line. It is possible to prevent the occurrence of bias.

In FIG. 17, in the vertical blanking period, the polarity of the source bus line potential is inverted once from Vp to Vn, and the counter voltage Vc (counter electrode voltage) is averaged. At this time, in the vertical blanking period, the pixel holding potential of the pixel unit Pix (x, y) changes from Vp to Vp−ΔV, and the potential difference from the potential of the source bus line Sbus _x changes from 0 to Vp−ΔV−Vn. Change. Further, the pixel holding potential of the pixel portion Pix (x, y + 1) changes from Vn + ΔV to Vn, and the potential difference from the potential of the source bus line Sbus _x changes from Vp + ΔV−Vn to 0. Therefore, in the vertical blanking period, the decrease in the pixel holding potential caused by the parasitic capacitance Csd of the pixel and the leakage current of the TFT as described above is reduced, and the decrease in the pixel holding potential is uneven for each horizontal line. Can be prevented.
JP-A-5-313607 JP 2001-202066 A JP 2002-40993 A

  However, the following problems remain even when the conventional techniques proposed in Patent Documents 1 to 3 are used.

  For example, in the case of performing black / halftone display for each horizontal line on the halftone solid display screen as shown in FIG. 18, (x, y) of the pixel portion (1), (x of the pixel portion (2) , Y + 1), (x + 1, y) of pixel (1) ′, and (x + 1, y + 1) of pixel portion (2) ′.

As shown in FIG. 18, the potentials of (x, y) of the pixel portion (1) and (x, y + 1) of the pixel portion (2) are charged to the halftone potentials VMp and VMn at the writing timing of each pixel portion. After that, it is changed by ΔVM due to the potential change of the source bus line Sbus _x .

On the other hand, the potentials of (x + 1, y) of the pixel portion (1) ′ and (x + 1, y + 1) of the pixel (2) ′ are halftone potentials VMp at the writing timing of each pixel portion as shown in FIG. And VMn are charged, and ΔVM and ΔV ′ are changed by the potential change of the source bus line Sbus _{x + 1} .

Here, ΔVM and ΔV ′ are ΔVM = (VMp−VMn) × (Csd + Csd) / (Cpix + Csd + Csd + Cgd)
ΔV ′ = (VMp−Vn) × (Csd + Csd) / (Cpix + Csd + Csd + Cgd)
It becomes.

  Originally, the pixel portion (1) and the pixel portion (2) and the pixel portion (1) ′ and the pixel portion (2) ′ should have the same pixel potential (display information), but have different pixel potentials. Crosstalk occurs in the vertical direction at the boundary between the pixel portion (1) and the pixel portion (2) and the pixel portion (1) ′ and the pixel portion (2) ′.

  As described above, the variation amount of the pixel potential is determined by the potential variation state of the source bus line in the display period, and the source bus line potential in the display period can take various values.

  Accordingly, the average potential of the source bus lines cannot always be equal to the counter electrode potential Vc, and the bias occurs, so that the pixel holding potential is also biased accordingly, and the vertical crosstalk occurs. To do.

  Such vertical crosstalk occurs when the pixel holding potential fluctuates due to potential fluctuation of the source bus line during the display period. Therefore, as disclosed in Patent Documents 1 to 3, it cannot be prevented by the conventional technique that controls the average potential of the source bus line to be approximately the value of the counter voltage Vc in the vertical blanking period. It is a bug.

In general, when comparing the display period to the blanking period in the vertical period,
Display period >> Blanking period.

  Therefore, the display period is longer than the period (blanking period) in which the pixel potential fluctuation reduction effect can be expected by the conventional techniques disclosed in Patent Documents 1 to 3, and the source bus line in the display period It is considered that the influence of the potential fluctuation on the image display is large.

  As a method for reducing such a problem, as shown in FIG. 19, the blanking period of the video signal Video is extended, and the holding potential of the pixel portion is affected by the potential fluctuation of the source bus line (effective display period). ) Can be shortened.

  However, when such a method is used, a load is imposed on the peripheral circuit for driving the liquid crystal display device, such as a separate memory is required for the drive circuit of the liquid crystal display device in order to extend the blanking period of the video signal Video. There is a problem that the manufacturing cost increases significantly.

  Further, as shown in FIG. 19, since the effective display period is shortened by the extension of the blanking period of the video signal Video, the sampling period of the video signal in the data driver is shortened accordingly, and the data driver It is necessary to increase the operation speed as compared with the prior art. For this reason, the power consumption of the data driver is increased by the increase of the operating frequency, and further problems such as insufficient operation speed of the data driver can occur.

  The present invention solves the above-described conventional problems, and is a pixel holding potential holding period without increasing peripheral circuit loads, power consumption of the data driver, and increasing the operating speed of the data driver. It is an object of the present invention to provide a display device and a driving method thereof that can reduce the variation in the pixel holding potential caused by the variation in the source bus line potential in the effective display period by apparently lengthening the ranking period.

In the display device of the present invention, a plurality of data signal lines and a plurality of scanning signal lines are provided so as to cross each other, and a pixel portion is provided for each crossing part of the data signal lines and the scanning signal lines. Are arranged in a matrix , and the display section is divided into a plurality of display areas in the longitudinal direction of the data signal lines , and a display potential is supplied to the pixel section for each of the divided display areas to hold it. A display device having display control means for performing display control by the display control means, the display control means within the blanking period of at least one of the plurality of display areas in order to suppress fluctuations in the pixel holding potential. At least one other than at least one is provided with an effective display period to perform display control , and the display control means reverses the polarity of the potential of each data signal line at least once in the blanking period. like And a Gosuru things, the objects can be achieved. In the display device of the present invention, a plurality of data signal lines and a plurality of scanning signal lines are provided to cross each other, and a pixel portion is provided for each crossing part of the data signal lines and the scanning signal lines. The plurality of pixel portions are arranged in a matrix, the display portion is divided into a plurality of display regions in the longitudinal direction of the data signal lines, and a display potential is supplied to the pixel portion for each of the divided display regions. A display device having display control means for performing display control by holding, wherein the display control means is within a blanking period of at least one of a plurality of display areas in order to suppress fluctuations in pixel holding potential. In addition, at least one other than the at least one is provided with an effective display period to perform display control, and the display control means applies the potential of each data signal line for each horizontal scanning period in the blanking period. Reverse polarity It is intended to controlled so, the object is achieved.

Also, have you to the display device of the present invention, the pixel unit based on the scanning signal from the scanning signal line, a switching element which can be supplied to the data signal from the data signal line to the pixel electrode, the switching And a pixel capacitor portion which sandwiches a display medium between the pixel electrode connected to the element and the counter electrode.

  Further preferably, the display control means in the display device of the present invention includes a data driver that selectively supplies a data signal to the data signal line sequentially, a gate driver that selectively supplies a scanning signal to the scanning signal line, A control signal supply circuit for supplying a display drive control signal to the data driver and the gate driver.

  Further preferably, in the display device of the present invention, data drivers are provided on both sides of the display portion, the data signal line is divided into two in the longitudinal direction, and one of the divided data signal lines is one of the data signals. The other data signal line is connected to the other data driver, and the display control means is connected to the other display area including the other data signal line from the one data driver. An effective display period of one display area including the one data signal line is provided within the ranking period, and an average potential of the one data signal line is set to the counter electrode in the blanking period of the one display area. A signal is supplied to the one data signal line so as to be equal to the average value of the potential, and the other data driver receives the other within the blanking period of the one display area. An effective display period of the display area is provided, and the other data signal is set so that the average potential of the other data signal line becomes equal to the average value of the potential of the counter electrode during the blanking period of the other display area. Supply a signal to the line.

And have your display device of the present invention, the display area as dividing the length of the data signal lines are different is divided into two.

  Further preferably, the display control means in the display device of the present invention is configured so that the data signal line from each data driver is set equal to the potential of the counter electrode in the blanking period. Signal.

  Further preferably, the display control means in the display device according to the present invention is configured such that the potential of each data signal line in the blanking period is a maximum value and a minimum value that can be taken by the potential of the data signal line in the effective display period. A signal is supplied from each of the data drivers so as to obtain an average value.

  Further preferably, each display area in the display device of the present invention is a half area of the display section.

  Further preferably, the display control means in the display device of the present invention controls the blanking period to be longer than the effective display period.

  Further preferably, the display control means in the display device of the present invention supplies each data driver with a timing control signal for switching a signal supplied from each data driver to the data signal line during the effective display period and the blanking period. .

  Further preferably, the display medium in the display device of the present invention is a liquid crystal material.

  Further preferably, in the display device of the present invention, at least the display section, the data driver, and the gate driver are provided on the same substrate.

In the driving method of the display device of the present invention, a plurality of pixel portions are two-dimensionally arranged in the display portion, the display portion is divided into two display regions, and the pixel portion is divided into each of the divided display regions. A driving method of a display device that performs display control by supplying a display potential to a pixel capacitor unit including a pixel electrode and a counter electrode and holding the potential, and data drivers are provided on both sides of the display unit, The data signal line is divided into two in the longitudinal direction, one of the divided data signal lines is connected to one data driver, and the other data signal line is connected to the other data driver. An effective display period of one display area including the one data signal line is provided within a blanking period of the other display area including the other data signal line, and the blanking of the one display area is performed. A signal is supplied to the one data signal line so that the average potential of the one data signal line becomes equal to the average value of the potential of the counter electrode during a period, and the other data driver An effective display period of the other display area is provided within the blanking period of the second display area, and the average potential of the other data signal line is equal to the average value of the potential of the counter electrode during the blanking period of the other display area. A signal is supplied to the other data signal line so as to be equal , and the potential of each of the one and other data signal lines is inverted at least once in the blanking period, or every horizontal scanning period all SANYO be controlled to polarity inversion, the above objects can be achieved.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, the data signal lines (source bus lines) constituting the display unit are divided in the direction of the data driver arranged on both sides (for example, up and down) across the display unit, and each divided source For example, the bus line is connected to and driven by the upper data driver and the lower data driver.

  The effective display period of one display area including one (for example, the upper side) data signal line (source bus line) obtained by dividing the display area into two is the other (for example, the lower side) including the other source bus line. It is driven within the blanking period of the display area so that the average potential of the lower source bus line is substantially equal to the average value of the counter electrode potential Vc. For example, the effective display period of the display area including the lower source bus line is, for example, within the blanking period of one display area including the upper source bus line, and the average potential of the upper source bus line is It is driven so as to be approximately equal to the average value of the counter electrode potential Vc.

  In the effective display period, the pixel holding potential varies via the pixel parasitic capacitance Csd due to the influence of the source bus line potential variation, and the TFT leakage current Ioff occurs due to the potential difference between the pixel holding potential and the source bus line. A decrease in pixel holding potential occurs.

  In general, the vertical blanking period in one vertical period is very short compared to the effective display period. Therefore, as in the prior art described in Patent Documents 1 to 3, in the method of making the average potential of the source bus lines substantially equal to the counter electrode potential during the blanking period (vertical blanking period), the pixel holding potential is lowered. The period during which the prevention can be performed was short and the effect was small.

  On the other hand, according to the present invention, as in the prior art, a blanking period in both display regions is provided without providing a memory in a peripheral circuit for driving a liquid crystal display device or increasing the operation speed of the data driver. Can be extended. Therefore, since the period (effective display period) in which the pixel holding potential fluctuates or decreases can be shortened, the load on the peripheral circuit, the power consumption of the data driver, and the operation speed of the data driver can be reduced as in the past. It is possible to reduce fluctuations in pixel holding potential due to fluctuations in source bus line potential during the effective display period without increasing the speed, thereby reducing problems such as shading and vertical crosstalk for each horizontal line. be able to.

  According to the present invention, a display region including a data signal line (source bus line) constituting a display unit, for example, a period in which image display is performed using one source bus line (upper display period). By making the average potential of the other source bus line substantially equal to the counter electrode potential, the peripheral circuit for driving the display device is not provided with a dedicated memory or the like, and the operation speed of the data driver is increased. Without this, the blanking period of each of the divided image display areas can be secured longer than before.

  As a result, due to the pixel parasitic capacitance Csd in the effective display period and the leakage current Ioff of the TFT constituting the pixel portion, the pixel holding potential is lowered due to the potential fluctuation of the source bus line, and vertical crosstalk or one horizontal line is generated. It is possible to improve the occurrence of display defects such as shading.

  Hereinafter, a case where the display device and the driving method thereof according to Embodiments 1 and 2 of the present invention are applied to an active matrix liquid crystal display device and a driving method thereof will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a main configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention.

  As shown in FIG. 1, the active matrix liquid crystal display device 10 includes data drivers 11A and 11B, a gate driver 12, and a display unit 13 formed on a transparent substrate such as a glass or quartz substrate. The data drivers 11 </ b> A and 11 </ b> B are arranged up and down with the display unit 13 sandwiched between the center units, and the gate driver 12 is arranged on the left side of the display unit 13. These data drivers 11A and 11B, the gate driver 12, and a control signal supply circuit that supplies various control signals for display driving to the data drivers 11A and 11B and the gate driver 12 (not shown) constitute display control means. Has been.

Source bus lines _{SbusA (SbusA 1, SbusA 2,} ··· SbusA n) constituting the display unit 13 and _{SbusB (SbusB 1, SbusB 2,} ··· SbusB n) is, in the conventional liquid crystal display device 100 one at A certain source bus line is divided between the gate bus line G _{m / 2} and the gate bus line G _{m / 2 + 1} in the upper and lower directions (display areas A and B). Other configurations are the same as those of the conventional liquid crystal display device 100 shown in FIG. 9, and in the display area A, source bus lines SbusA (SbusA ₁ , SbusA ₂ ,...) As a plurality of data signal lines. SbusA _n ) and gate bus lines G ₁ , G ₂ ,... G _{m / 2} as a plurality of scanning signal lines are arranged so as to cross each other (or orthogonally). In the display area B, source bus lines SbusAB (SbusB ₁ , SbusB ₂ ,... SbusB _n ) as a plurality of data signal lines and gate bus lines G _{m / 2 + 1} , G as a plurality of scanning signal lines. _{2m /} 2 + 2, and a · · · _{G m} being cross (or perpendicular) to each other. A plurality of thin film transistors (TFTs; not shown) are provided in a matrix in the vicinity of the intersections of both bus lines. The gate terminal of each TFT is connected to one of gate bus lines G ₁ , G ₂ ,... G _n connected from the signal output unit of the gate driver 12. In the display area A, the source terminal of each TFT is connected to one of the source bus lines SbusA ₁ , SbusA ₂ ,... SbusA _n connected from the signal output section of the data driver 11A. In the display area B, the source terminal of each TFT is connected to any one of the source bus lines SbusB ₁ , SbusB ₂ ,... SbusB _n connected from the signal output unit of the data driver 11B. Further, the drain terminal of each TFT is connected to a pixel capacitor (not shown) having a liquid crystal capacitor as a display medium sandwiched between the pixel electrode made of a transparent electrode and the counter electrode, and an auxiliary capacitor (not shown). Yes.

In the display unit 13, respectively. The source bus line SbusA _n and SbusB _n divided into respective display areas A and B, are connected to the data driver A and B. One data driver 11A includes a start pulse SPS and a clock signal CKS that are control signals, a video signal Video that is a data signal during an effective display period, a signal Vpr that is a signal applied to a source bus line during a blanking period, A signal SpectlA that controls timing for switching the signal applied to the source bus line from the video signal Video to the signal Vpr is input. The other data driver 11B has a start pulse SPS and a clock signal CKS that are control signals, a video signal Video that becomes a data signal during an effective display period, and a signal that becomes a signal applied to the source bus line during a blanking period. Vpr is input with a signal SpectlB that controls the timing of switching the signal supplied to the source bus line from the video signal Video to the signal Vpr.

Further, the gate bus lines G ₁ , G ₂ ... G _m of the display unit 13 are connected to the gate driver 12. The gate driver 12 receives a start pulse SPG and a clock signal CKG that are control signals.

  In the active matrix liquid crystal display device 10, the video signal Video, the signal Vpr that is a signal applied to the source line during the blanking period, and the timing for switching the signal supplied to the source bus line from the video signal Video to the signal Vpr are set. The timing control signals SpectlA and SpectlB to be controlled are respectively input to the data drivers A and B at the timing shown in FIG.

  As shown in FIG. 2, the video signal Video has an effective display period in which the polarity changes between Vp and Vn in one vertical period, and a vertical blanking period in which the counter electrode potential Vc is set. The signal Vpr is set to the counter electrode potential Vc. In addition, the timing control signal PectlA has a low level in the first half of the effective display period of the video signal Video, and a high level in the second half of the effective display period, and the timing control signal PectorB displays the effective display of the video signal Video. The first half of the period is set to the high level, and the second half of the effective display period is set to the low level.

  Therefore, the effective display period of the display area A and the effective display period of the display area B are combined to form an effective display period of the video signal Video (effective display period of the display unit 13). Apparently, a period obtained by subtracting the effective display period of the video signal Video from one vertical period of the video signal Video is a vertical blanking period of the video signal Video, but a part of the vertical blanking period of the display area A is Since it overlaps with the effective display period of the display area B and a part of the vertical blanking period of the display area B overlaps with the effective display period of the next display area A, each vertical blanking period of the display areas A and B Can take longer.

  The operation of the active matrix liquid crystal display device 10 according to the first embodiment will be described with the above configuration.

A period in which the gate bus lines G ₁ , G ₂ ... G _{2 / m in the} display area A shown in FIG. 1 are selected is an effective display period in the display area A shown in FIG. The spectleA is set to the low level (selection level). During the effective display period of the display area A, the potential at which the video signal Video is sampled by the sampling signals Sam ₁ , Sam ₂ ... Sam _n generated by the start pulse SPS and the clock signal CKS is output from the data driver 11A. To the source bus line SbusA.

The period in which the gate bus lines G _{m / 2 + 1} ... G _{m in the} display area B shown in FIG. 1 are selected is an effective display period in the display area B shown in FIG. 2, and the timing control signal spectlB is Low. Level (selection level). As shown in FIG. 2, the effective display period of the display area B overlaps with the vertical blanking period of the display area A. At this time, the timing control signal spectlA is at the Hi level (selection level). In the vertical blanking period of the display area A, the data driver 11A selects the signal Vpr and supplies the same potential as the counter electrode potential Vc to the source bus line SbusA.

In the effective display period of the display area B in which the gate bus lines G _{m / 2 + 1} ... G _{m of the} display area B shown in FIG. 1 are selected, the sampling signal Sam ₁ generated by the start pulse SPS and the clock signal CKS. , Sam ₂ ... Sam _n, the potential obtained by sampling the video signal Video is output from the data driver 11B and supplied to the source bus line SbusB.

  The vertical blanking period of the video signal Video and the effective display period of the next display area A are vertical blanking periods of the display area B as shown in FIG. 2, and at this time, the timing control signal spectlB is at the Hi level. (Selection level). In the vertical blanking period of the display area B, the data driver 11B selects the signal Vpr and supplies the same potential as the counter electrode potential Vc to the source bus line SbusB.

  By the above operation, the potential state of the source bus lines SbusA and SbusB is such that the apparent blanking period is half the effective display period in the video signal Video as compared with the conventional active matrix liquid crystal display device. It is getting longer. By setting the potential of the source bus line to the same potential Vc as the counter electrode potential during this blanking period, the period that is affected by the potential fluctuation of the source bus line during the effective display period in the holding period of the pixel holding potential is set to 1 / 2.

  Furthermore, according to the active matrix type liquid crystal display device 10 of the first embodiment, unlike the prior art shown in FIG. 19, no memory is required for the liquid crystal display drive circuit, and the operation speed of the data driver is increased. Therefore, it is not necessary to increase power consumption and increase the operation speed of the data driver.

Compared with the display period and the blanking period in the vertical period as in the prior art described above,
Blanking period << Effective display period in many cases.

On the other hand, in the active matrix type liquid crystal display device 10 of the first embodiment,
Blanking period = effective display period / 2 + conventional blanking period. Compared with the conventional blanking period, it is possible to greatly extend the period during which the pixel potential fluctuation reduction effect can be expected.

  As described above, according to the first embodiment, in the active matrix display device 10, the data drivers 11A and 11B are provided above and below across the display unit 13, and each source bus line is divided into two vertically and divided into upper and lower data. Connected to the driver. The effective display period of each display area A and B is provided within the blanking period of the other display area B and A, and the average potential of the source bus line of each area is displayed during the blanking period of each display area A and B. Is driven to be substantially equal to the average value of the counter electrode potential. As a result, the blanking period can be apparently lengthened, and display defects due to fluctuations in the pixel holding potential caused by fluctuations in the source bus line potential during the effective display period can be reduced.

  In the first embodiment, the source bus line potential in the vertical blanking period of the display areas A and B is driven to be equal to the counter electrode potential Vc, but the vertical blanking period of the display areas A and B is used. The source bus line potential at is not limited to the counter electrode potential Vc, but is a potential at which the average potential of the source bus line becomes equal to the average value of the counter electrode potential Vc in the vertical blanking period of the display areas A and B. If it is good. For example, as shown in FIG. 3, in the vertical blanking period of the display areas A and B, between the maximum value Vp and the minimum value Vn that can be taken by the potential of the data signal line every horizontal scanning period. The polarity may be reversed. Further, as shown in FIG. 4, in the vertical blanking period of the display areas A and B, once (or twice) between the maximum value Vp and the minimum value Vn that the potential of the data signal line can take. As described above, the polarity may be reversed. In the above case, the video signal Video is switched from the video signal Video to the signal Vpr which is a signal applied to the source bus line during the blanking period. This signal Vpr is a potential equal to the counter electrode potential Vc, a polarity inversion signal having a predetermined frequency, and one or several polarity inversion signals.

Furthermore, in Embodiment 1, but is divided into upper and lower half on the display unit 13 to the source bus line in the longitudinal direction, divided in the longitudinal direction of the source bus lines limited above and below half of the display unit 13 (The source bus line may be divided in the longitudinal direction by dividing the display area into left and right parts, which may be added to the upper and lower parts of the display area ) .

(Embodiment 2)
In the first embodiment, the number of the plurality of source bus lines is divided into two equal parts in the vertical direction. However, in the second embodiment, the number of the source bus lines is biased up and down (the number is different). ) A case of dividing into two will be described.

  FIG. 5 is a block diagram showing a main configuration of the active matrix liquid crystal display device according to the second embodiment of the present invention.

  As shown in FIG. 5, in the active matrix liquid crystal display device 20, data drivers 21A and 21B, a gate driver 22, and a display unit 23 are formed on a transparent substrate such as a glass substrate or a quartz substrate. The data drivers 21 </ b> A and 21 </ b> B are arranged up and down with the display unit 23 sandwiched between the center units, and the gate driver 22 is arranged on the left side of the display unit 23. The data drivers 21A and 21B output data signals having different effective display periods and blanking periods. These data drivers 21A and 21B, the gate driver 22, and a control signal supply circuit that supplies various control signals for display driving to the data drivers 21A and 21B and the gate driver 22 (not shown) constitute display control means. Has been.

Source bus lines SbusA constituting the display section _{23 (SbusA 1, SbusA 2,} ··· SbusA n) and _{SbusB (SbusB 1, SbusB 2,} ··· SbusB n) is, in the conventional liquid crystal display device which is one source bus lines are disposed in vertically divided (the display regions a and B) between the gate bus line GA _n and the gate bus line GB _1. The other configuration is the same as that of the conventional liquid crystal display device 100 shown in FIG. 9, and in the display area A, source bus lines SbusA (SbusA ₁ , SbusA ₂ ,... SbusA) as a plurality of data signal lines. _n ) and gate bus lines GA ₁ , GA ₂ ,... GA _n as a plurality of scanning signal lines are arranged so as to cross (orthogonal) each other. In the display area B, source bus lines SbusAB (SbusB ₁ , SbusB ₂ ,... SbusB _n ) as a plurality of data signal lines and gate bus lines GB ₁ , GB ₂ as a plurality of scanning signal lines, ... GB _m are arranged so as to cross each other (orthogonal). Thin film transistors (TFTs) (not shown) are arranged in the vicinity of the intersections of both bus lines, and a plurality of TFTs are provided in a matrix (or two-dimensional). The gate terminal of each TFT is connected to one of gate bus lines GA ₁ , GA ₂ ,... GB _m−1 , GB _m connected from the signal output unit of the gate driver 22. In the display area A, the source terminal of the TFT is connected to one of the source bus lines SbusA ₁ , SbusA ₂ ,... SbusA _n connected from the signal output unit of the data driver 21A. In the display area B, the source terminal of the TFT is connected to one of the source bus lines SbusB ₁ , SbusB ₂ ,... SbusB _n connected from the signal output unit of the data driver 21B. Further, the drain terminal of the TFT is connected to a pixel capacitor (not shown) having a liquid crystal capacitor as a display medium sandwiched between the pixel electrode made of a transparent electrode and the counter electrode, and an auxiliary capacitor (not shown). .

In the display unit 23, respectively. The source bus line SbusA _n and SbusB _n divided into respective display areas A and B, are connected to the data driver A and B. One data driver 21A includes a start pulse SPS and a clock signal CKS that are control signals, a video signal VideoA that is a data signal during an effective display period, a signal Vpr that is a signal applied to a source bus line during a blanking period, and a source A signal SpectlA that controls timing for switching the signal applied to the bus line from the video signal Video to the signal Vpr is input. In addition, the other data driver 21B includes a start pulse SPS and a clock signal CKS that are control signals, a video signal VideoB that is a data signal during an effective display period, and a signal Vpr that is a signal applied to the source bus line during a blanking period. The signal SpectlB for controlling the timing for switching the signal supplied to the source bus line from the video signal Video to the signal Vpr is input.

Further, the gate bus lines GA ₁ , GA ₂ ... GB _m−1 , GB _m of the display unit 23 are connected to the gate driver 22. The gate driver 22 is supplied with a start pulse SPG and a clock signal CKG that are control signals.

  In this active matrix type liquid crystal display device 20, the video signals VideoA and VideoB, the signal Vpr that is applied to the source line during the blanking period, and the timing at which the signal supplied to the source bus line is switched from the video signal Video to the signal Vpr. The timing control signals SpectlA and SpectlB for controlling the data are respectively input to the data drivers 21A and 21B at the timings shown in FIG.

  As shown in FIG. 6, each of the video signals VideoA and VideoB has an effective display period in which the polarity changes between Vp and Vn in one vertical period, and a vertical blanking period in which the counter electrode potential Vc is set. is doing. The signal Vpr is set to the counter electrode potential Vc. In addition, the timing control signal PectlA has a valid display period of the display area A at a low level, and the vertical blanking period of the display area A has a high level. The display period is set to the low level, and the vertical blanking period of the display area B is set to the high level.

  Therefore, the effective display period of the display area A and the effective display period of the display area B are combined to form an effective display period of the video signal Video (effective display period of the display unit 13). Apparently, a period obtained by subtracting the effective display period of the video signal Video from one vertical period of the video signal Video is a vertical blanking period of the video signal Video, but a part of the vertical blanking period of the display area A is The display area B overlaps with the effective display period, and a part of the vertical blanking period of the display area B overlaps with the next effective display period of the display area A and a period including several cycles of the vertical blanking period. The vertical blanking periods of the display areas A and B can be made longer.

  The operation of the active matrix liquid crystal display device 20 of the second embodiment will be described with the above configuration.

  First, the operation of the gate driver 22 will be described.

The gate driver 22 is configured so that the start pulse SPG inputted to the gate driver 22 is synchronized with the clock signal CKG and the gate connected to the output part of the gate driver 22 during a period in which the timing control signal PectlA or PectlB is at the low level. Sequentially output as selection pulses to the bus line. For example, in the period A * B shown in FIG. 6, the selection pulses are sequentially output in the order of GA ₁ → GA ₂ →... GA _n → GB ₁ → GB ₂ →... GB _m in synchronization with the clock signal CKG. Is done. In the period A shown in FIG. 6, the selection pulses are sequentially output from GA ₁ → GA ₂ →... GA _n in synchronization with the clock signal CKG. Therefore, at the drive timing as shown in FIG. 6, the selection pulse GB1 → GB2 →... GB _m is 1/6 cycle (1/5 sec) of GA ₁ → GA ₂ →... GA _n (1/30 sec cycle). (Period).

  Next, operations of the data drivers 21A and 21B will be described.

A period in which the gate bus lines GA ₁ , GA ₂ ... GA _{n in the} display area A shown in FIG. 5 are selected is an effective display period in the display area A shown in FIG. Low level (selection level). During the effective display period of the display area A, the potential at which the video signal VideoA is sampled by the sampling signals Sam ₁ , Sam ₂ ... Sam _n generated by the start pulse SPS and the clock signal CKS is output from the data driver 21A. And supplied to the source bus line SbusA.

Further, the period in which the gate bus lines GB ₁ ... GB _m−1 and GB _{m in the} display area B shown in FIG. 5 are selected is the effective display period of the display area B shown in FIG. It is a vertical blanking period. During this period, as shown in FIG. 6, the timing control signal spectlA is at the Hi level (non-selection level). During the vertical blanking period of the display area A, the data driver 21A selects the signal Vpr and supplies the same potential as the counter electrode potential Vc to the source bus line SbusA.

On the other hand, in the effective display period in which the gate bus lines GB ₁ ... GB _m−1, GB _{m in the} display area B shown in FIG. 5 are selected, the timing control signal spectlB shown in FIG. It is said that. In the effective display period of the display area B, the potential at which the video signal VideoB is sampled by the sampling signals Sam ₁ , Sam ₂ ... Sam _n generated by the start pulse SPS and the clock signal CKS is output from the data driver 11B. To the source bus line SbusB.

The gate bus lines GA ₁ , GA ₂ ... GA _{n in the} display area A shown in FIG. 5 and the vertical blanking period of the video signal Video are displayed in the display area B as shown in FIG. And the timing control signal spectlB is at the Hi level (non-selection level). During the vertical blanking period of the display area B, the data driver 21B selects the signal Vpr and supplies the same potential as the counter electrode potential Vc to the source bus line SbusB.

  As a result of the above operation, the apparent blanking period of the potential states of the source bus lines SbusA and SbusB is longer than that of the conventional active matrix liquid crystal display device 100. By setting the source bus line potential to the counter electrode potential Vc during the blanking period, the pixel holding potential holding period in the display area A is affected by the potential fluctuation of the source bus line in the effective display period of the display area B. Nothing will happen. Further, the holding period of the pixel holding potential in the display area B is not affected by the potential fluctuation of the source bus line in the effective display period of the display area A. Further, unlike the prior art shown in FIG. 19, the liquid crystal display drive circuit does not require a memory, and it is not necessary to increase the operation speed of the data driver. It is not necessary to increase the speed.

  As described above, according to the second embodiment, for example, when the moving image display is performed in the display region A by 30 Hz driving and the still image display is performed in the display region B by 5 Hz driving, the vertical blanking of the display region B is performed. By setting the source bus line potential to the Vc potential in the period, it is possible to significantly improve the influence of the variation in the source bus line potential in the pixel potential holding period. In addition, since the blanking period of the display area A is increased by the effective display period of the display area B as compared with the case where the entire screen is driven at 30 Hz, the pixel holding potential of the display area A during the period is the source bus line. It is possible to reduce the influence caused by the potential fluctuation. Furthermore, compared to a case where the entire screen is driven at 30 Hz, a part of the source bus line is driven at 5 Hz, and the source bus line is divided at the top and bottom of the display unit 23, so that the source bus line serving as a load on the data driver is obtained. The capacity can also be reduced, and power consumption can be reduced.

  In the second embodiment, the source bus line potential in the vertical blanking period of the display areas A and B is driven to be equal to the counter electrode potential Vc, but the vertical blanking period of the display areas A and B is used. The source bus line potential at is not limited to the counter electrode potential Vc, but is a potential at which the average potential of the source bus line becomes equal to the average value of the counter electrode potential Vc in the vertical blanking period of the display areas A and B. If it is. For example, as shown in FIG. 7, in the vertical blanking period of the display areas A and B, between the maximum value Vp and the minimum value Vn that the potential of the data signal line can take every horizontal scanning period. The polarity may be reversed. Also, as shown in FIG. 8, in the vertical blanking period of the display areas A and B, once (or several times) between the maximum value Vp and the minimum value Vn that the potential of the data signal line can take. ) The polarity may be reversed.

  In the first and second embodiments, the active matrix liquid crystal display device 10 or 20 includes the display unit 13 or 23, the data driver 11A, 11B or 21A, 21B, and the gate driver 12 or 22 provided on the same substrate. A driver monolithic type may be used, or a driver using amorphous Si may be manufactured separately from the display unit 13 or 23 and attached externally. The data drivers 11A, 11B or 21A, 21B may be selectively driven by either a dot sequential method or a line sequential method.

Further, in the present embodiment 1 and 2, are divided into up and down in the display unit of the source bus lines, the division of the source bus lines is not limited to the case of 2 divides the display unit up and down, a source As for the division of the bus line in the longitudinal direction, the display area may be divided into left and right parts, and this may be added to the upper and lower parts of the display area . Further, a plurality divided up and down in the longitudinal direction on the display unit source bus lines (n divided by n is a natural number of 3 or more) may also, or split in the longitudinal direction of the source bus lines in a plurality dividing the display area on the left and right This may be added to the upper and lower divisions.

  For example, in the field of display devices such as active matrix type liquid crystal display devices used for display screens of mobile phone devices, liquid crystal televisions, personal computers, etc., peripheral circuit loads and data driver power consumption increase, data driver operation By making the blanking period, which is the holding period of the pixel holding potential, apparently longer without increasing the speed or the like, fluctuations in the pixel holding potential due to fluctuations in the source bus line potential in the effective display period can be reduced. As a result, an active matrix display device with a good display state and low power consumption can be manufactured at low cost, so that the performance and low performance of an electronic device equipped with a display device such as an active matrix liquid crystal display device can be reduced. Cost reduction can be realized.

It is a block diagram which shows the principal part structure in Embodiment 1 of the active matrix type liquid crystal display device of this invention. FIG. 2 is a signal waveform diagram illustrating an example for explaining a signal input to a data driver and a source bus line potential in the active matrix liquid crystal display device of FIG. 1. FIG. 7 is a signal waveform diagram illustrating another example for explaining a signal input to a data driver and a source bus line potential in the active matrix liquid crystal display device of FIG. 1. FIG. 7 is a signal waveform diagram showing still another example for explaining a signal input to a data driver and a source bus line potential in the active matrix liquid crystal display device of FIG. 1. It is a block diagram which shows the principal part structure in Embodiment 2 of the active matrix type liquid crystal display device of this invention. FIG. 6 is a signal waveform diagram illustrating an example for explaining a signal input to a data driver and a source bus line potential in the active matrix liquid crystal display device of FIG. 5. FIG. 6 is a signal waveform diagram illustrating another example for explaining a signal input to a data driver and a source bus line potential in the active matrix liquid crystal display device of FIG. 5. FIG. 6 is a signal waveform diagram showing still another example for explaining a signal input to a data driver and a source bus line potential in the active matrix liquid crystal display device of FIG. 5. It is a block diagram which shows the example of a principal part structure of the conventional active matrix type liquid crystal display device. It is a block diagram which shows the principal part structure of the data driver of FIG. It is a wave form diagram in the principal part of the conventional active matrix type liquid crystal display device of FIG. 6 is a video signal waveform diagram showing an example of a video signal Video input to the data driver 101 when polarity is inverted in one horizontal scanning period (during 1H inversion driving). FIG. It is a figure for demonstrating the fall of the pixel capacity | capacitance of the display part of FIG. It is a signal waveform diagram for demonstrating the source bus line electric potential and pixel electric potential in the conventional active matrix type liquid crystal display device. In another conventional active matrix type liquid crystal display device, when the source bus line potential in the vertical blanking period is the counter electrode potential Vc, it is a signal waveform diagram for explaining the source bus line potential and the pixel potential. Further, in another conventional active matrix liquid crystal display device, a signal waveform diagram for explaining the source bus line potential and the pixel potential when the source bus line potential in the vertical blanking period is inverted by 1H with the potentials Vp and Vn. It is. In another conventional active matrix liquid crystal display device, the source bus line potential and the source bus line potential in the case of inverting the source bus line potential in the vertical blanking period with the potentials Vp and Vn in half the vertical blanking period. It is a signal waveform diagram for explaining a pixel potential. It is a figure for demonstrating the cause which vertical crosstalk generate | occur | produces in the conventional active matrix type liquid crystal display device. It is a figure for demonstrating the drive method which reduces vertical crosstalk in another conventional active matrix type liquid crystal display device.

Explanation of symbols

10, 20 Active matrix type liquid crystal display device 11A, 11B, 21A, 21B Data driver 12, 22 Gate driver 13, 23 Display unit

Claims (14)

A plurality of data signal lines and a plurality of scanning signal lines are provided so as to cross each other, a pixel portion is provided for each crossing portion of the data signal lines and the scanning signal lines, and the plurality of pixel portions are arranged in a matrix. A display that performs display control by dividing the display unit into a plurality of display regions in the longitudinal direction of the data signal lines, supplying a display potential to the pixel unit for each of the divided display regions, and holding the display potential. A display device having a control means,
The display control means includes an effective display period provided in at least one of the plurality of display regions within at least one blanking period in order to suppress fluctuations in the pixel holding potential. Display control is performed ,
The display control unit controls the polarity of the potential of each data signal line to be inverted at least once in the blanking period . A plurality of data signal lines and a plurality of scanning signal lines are provided so as to cross each other, a pixel portion is provided for each crossing portion of the data signal lines and the scanning signal lines, and the plurality of pixel portions are arranged in a matrix. A display that performs display control by dividing the display unit into a plurality of display regions in the longitudinal direction of the data signal lines, supplying a display potential to the pixel unit for each of the divided display regions, and holding the display potential. A display device having a control means,
The display control means includes an effective display period provided in at least one of the plurality of display regions within at least one blanking period in order to suppress fluctuations in the pixel holding potential. Display control is performed ,
The display control unit controls the polarity of the potential of each data signal line to be inverted every horizontal scanning period in the blanking period . The pixel section, based on a scanning signal from the scanning signal line, a switching element which can be supplied to the data signal from the data signal line to the pixel electrode, the pixel electrode and the counter electrode connected to the switching element The display device according to claim 1, further comprising a pixel capacitor portion having a display medium sandwiched therebetween. Wherein the display control unit, and selectively sequentially supplies data driver data signal to the data signal line, and selectively supplies the gate driver scanning signals to the scanning signal lines, displayed on the data driver and the gate driver The display device according to claim 1, further comprising a control signal supply circuit that supplies a control signal for driving. Data drivers are provided on both sides of the display portion, the data signal line is divided into two in the longitudinal direction, one of the divided data signal lines is connected to one data driver, and the other data signal line Is connected to the other data driver,
The display control means includes
The one data driver provides an effective display period for one display area including the one data signal line within a blanking period for the other display area including the other data signal line, and A signal is supplied to the one data signal line so that the average potential of the one data signal line becomes equal to the average value of the potential of the counter electrode during the blanking period of the display area;
The other data driver provides an effective display period for the other display area within the blanking period for the one display area, and the other data signal line for the blanking period for the other display area. The display device according to claim 4, wherein a signal is supplied to the other data signal line so that an average potential of the second electrode is equal to an average value of the potential of the counter electrode. The display device according to claim 1 , wherein the display area is divided into two so that the division lengths of the data signal lines are different .   5. The display control unit according to claim 4, wherein the display control means supplies a signal from each data driver to each data signal line so that the potential of each data signal line is equal to the potential of the counter electrode in the blanking period. Display device.   In the blanking period, the display control unit is configured to set the potential of each data signal line to an average value of a maximum value and a minimum value that can be taken by the potential of the data signal line in an effective display period. The display device according to claim 4, wherein a signal is supplied from a driver.   The display device according to claim 4, wherein each of the display areas is a half area of the display unit.   The display device according to claim 4, wherein the display control unit controls the length of the blanking period to be longer than the effective display period.   5. The display device according to claim 4, wherein the display control means supplies each data driver with a timing control signal for switching a signal to be supplied from each data driver to a data signal line during the effective display period and the blanking period.   The display device according to claim 2, wherein the display medium is a liquid crystal material.   The display device according to claim 3, wherein at least the display unit, the data driver, and the gate driver are provided on the same substrate. A plurality of pixel portions are two-dimensionally arranged on the display portion, the display portion is divided into two display regions, and a pixel capacitor portion including a pixel electrode and a counter electrode of the pixel portion for each of the divided display regions A display device driving method for performing display control by supplying a display potential to and holding the display potential,
Data drivers are provided on both sides of the display portion, the data signal lines are divided into two in the longitudinal direction, one of the divided data signal lines is connected to one data driver, and the other data signal line is connected to the other Connected to the data driver
The one data driver provides an effective display period for one display area including the one data signal line within a blanking period for the other display area including the other data signal line, and A signal is supplied to the one data signal line so that the average potential of the one data signal line becomes equal to the average value of the potential of the counter electrode during the blanking period of the display region;
The other data driver provides an effective display period for the other display area within the blanking period for the one display area, and the other data signal line for the blanking period for the other display area. A signal is supplied to the other data signal line so that the average potential of the second electrode becomes equal to the average value of the potential of the counter electrode,
A driving method of a display device, wherein the polarity of the potential of each of the one and other data signal lines is controlled at least once or inverted every horizontal scanning period in the blanking period .

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