JP2002099256A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device in which no writing shortage is generated by gate signals even though the size of a screen is increased. SOLUTION: A gate driver 28 of a liquid crystal display device 10 temporarily boosts gate signals to an intermediate voltage VDD from a reference voltage VO and then, boosts the voltage VDD to a writing voltage Vgh so that the size of the residual is made small and no writing shortage is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device such as a liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device, which is one of the liquid crystal display devices, has an increased number of scanning lines and a thin film transistor (TFT) connected to one scanning line with the increase in size and definition. The number is increasing and the resistance and capacitance of the scanning lines are steadily increasing.

As described above, the increase in the resistance and capacitance of the scanning line causes the voltage waveform of the gate signal Vg shown in FIG. 4 to be delayed on the terminal side of the scanning line like the voltage waveform of the gate signal Vg shown in FIG. .

As described above, as the delay time in the end direction of the scanning line increases, the TFT does not turn off, a leak current flows, and the pixel voltage decreases.

Therefore, as shown in FIGS. 4 and 5, a gate delay time t2 is conventionally provided in consideration of the rounding of the voltage waveform, and the gate signal V is equal to the gate delay time t2.
g is falling quickly.

Further, even at the time of the rise of the gate signal Vg, rounding occurs due to the influence of the resistance and capacitance of the scanning line, the writing time to the pixel electrode becomes longer, and the flicker phenomenon occurs.

Therefore, conventionally, in order to prevent the occurrence of the flicker, the rising time of the gate signal Vg is delayed by a certain time to provide the output inhibition time t1.

[0008]

However, by providing the period of the output inhibition time t1 as described above, the gate signal V
Even if the rounded portion of g is pre-cut, there is a problem in that insufficient writing occurs due to the recent increase in screen size, which adversely affects image quality.

As a method of improving such insufficient writing on a large screen, there is a double gate driving method.

In this double-gate driving method, before a main write is performed on a pixel electrode by a gate signal, a pixel signal of another line is written by a preliminary write to improve insufficient writing.

However, even this method has an adverse effect on image quality depending on display data at the time of preliminary writing.

In view of the above problems, the present invention provides a flat display device in which insufficient writing due to a gate signal does not occur even when the screen size becomes large.

[0013]

According to a first aspect of the present invention, there are provided a plurality of signal lines and scanning lines arranged orthogonally to each other, and a switching element disposed near an intersection between the signal lines and the scanning lines. A signal line driving circuit connected to the signal line and supplying an image signal; and a switching element connected to the scanning line and connected to the switching element.
A scanning line driving circuit for supplying a gate signal for writing the image signal to the pixel electrode in the N state, wherein the scanning line driving circuit temporarily raises the gate signal from a reference voltage to an intermediate voltage. A flat display device characterized by increasing the write voltage after the operation.

According to a second aspect of the present invention, a vertical start signal for outputting a horizontal start signal for instructing a timing of generating the image signal to the signal line driving circuit, and for instructing a timing of generating the gate signal, A control circuit that outputs an output prohibition signal having a predetermined pulse width to the scanning line driving circuit, wherein the scanning line driving circuit receives the output prohibition signal based on a time when the vertical start signal is input; 2. The flat display device according to claim 1, wherein the gate signal is raised to an intermediate voltage after that, and then the gate signal is raised to a write voltage after the output inhibition signal stops.

In the flat display device of the present invention, the gate signal once rises to the intermediate voltage and then rises to the write voltage. Therefore, the rounding at the time when the gate voltage rises to the write voltage suddenly changes from the reference voltage to the write voltage. It becomes smaller than when ascending, and it is possible to reduce insufficient writing.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display device 10 according to one embodiment of the present invention will be described below with reference to FIGS.

The liquid crystal display device 10 includes a liquid crystal panel 12 having a UXGA-specified color display pixel having a diagonal effective area of, for example, 15 inches.

As shown in FIG. 1, the liquid crystal panel 12 has (1600 × 3 (R, G, B)) signal lines 16 and 1200 scanning lines arranged orthogonally to the signal lines 6. 1
8 and a pixel electrode 22 arranged via a TFT 20 arranged near an intersection of each of the signal lines 16 and the scanning lines 18.
And an array substrate 14 having the following. Further, a counter electrode substrate (not shown) having a color filter disposed above the opposing surface of the array substrate 14 with a predetermined gap.
And a liquid crystal (not shown) as a light modulation layer disposed between the array substrate 14 and the counter electrode substrate.

If an organic EL panel is used instead of the liquid crystal panel, it is necessary to dispose an induced EL layer instead of the liquid crystal.

Each of the scanning lines 18 is connected to the gate of the TFT 20, each of the signal lines 16 is connected to the drain of the TFT 20, each of the pixel electrodes 22 is connected to the source of the TFT 20,
Are electrically connected to each other so that the scanning line 1
The image signal Vs from the signal line 16 is written to the pixel electrode 22 in accordance with the gate signal Vg supplied to the pixel 8 and is displayed based on the potential difference between the pixel electrode 22 and the counter electrode.

The signal line 16 is connected to a source driver 24. The source driver 24 performs D / A conversion on the digital image data signal DATA and converts the digital image data signal DATA into an analog image signal Vs.
To the signal line 16.

The scanning line 18 is connected to a gate driver 28, and is supplied with a gate signal Vg.

A liquid crystal controller 30 for controlling the source driver 24 and the gate driver 28 is provided.

The liquid crystal controller 30 supplies the source driver 24 with a horizontal clock signal XCLK, a horizontal start signal STH, and the aforementioned image data signal DAT.
A, a polarity inversion signal POL is supplied. Further, a vertical clock signal YCLK, a vertical start signal STV, and an output inhibition signal OE are supplied to the gate driver 28.

The power supply circuit 32 performs DC / DC conversion of a DC voltage Vin supplied from the outside, and
To generate a plurality of DC voltages necessary for

For example, the power supply circuit 32 supplies a DC voltage V1 to the source driver 24, and also supplies a DC voltage V2 to the liquid crystal controller 30. The gate driver 28 is supplied with a write voltage Vgh and an intermediate voltage VDD described later.

A power supply selection circuit 30 is provided inside the gate driver 28, and selects the write voltage Vgh and the intermediate voltage VDD supplied from the power supply circuit 32 based on a control signal sent from the liquid crystal controller 30. It is output as a gate signal Vg.

FIG. 2 shows an output waveform of the gate signal Vg.

As shown in FIG. 2, the voltage is once increased from the reference voltage V0 to the intermediate voltage VDD, and is increased to the write voltage Vgh after the output inhibition time t1. Then, the gate voltage is lowered earlier by the gate delay time t2. As a result, the necessary time for writing the image signal Vs can be obtained, and insufficient writing is not performed.

That is, with this waveform, the intermediate voltage V
Since the voltage is increased from DD to the write voltage Vgh, the rounding at the time when the voltage is increased to Vgh is smaller than that when the voltage is suddenly increased from the reference voltage V0, so that insufficient writing does not occur.

The operation of the liquid crystal display device 10 for obtaining the waveform of the gate signal Vg will be described with reference to FIG.

FIG. 3 is a timing chart of each signal output from the liquid crystal controller 30.

FIG. 3 shows a vertical clock signal YCL from the top.
K, vertical start signal STV, output inhibit signal OE, gate signal Vg, delay signal TE, horizontal clock signal XCL
K, horizontal start signal STH, analog image signal Vs
Is shown.

In the liquid crystal controller 30, the horizontal clock signal XCLK, the vertical start signal STV, and the output inhibition signal OE are output to the gate driver 28.

The gate driver 28 receives the vertical start signal STV, and only after the vertical clock signal YCL
The gate signal Vg is output from the time when K rises.

However, as described in the prior art, in order to prevent the occurrence of flicker due to the rounding of the rising edge of the gate signal Vg, it is necessary to keep the gate signal Vg from being output for a certain period of time. Therefore, this time is determined by the output inhibition signal OE output from the liquid crystal controller 30.

First, in this embodiment, the vertical start signal S
When a TV is input and the vertical clock signal YCLK rises and the output inhibit signal OE rises, the gate signal V0 (for example, -12V) is once increased to the intermediate voltage VDD (for example, 3V).

Next, after the output prohibition signal OE falls after the output prohibition time t1 (for example, 20 μsec), the gate signal Vg is further raised to the write voltage Vgh (for example, 18 V).

Next, the gate delay signal will be described.

After a delay time t2, which is the time from when the vertical start signal STV output to the gate driver 28 rises to when the delay signal TE falls, a horizontal start signal STH to be output to the source driver 24 is generated. Output to the source driver 24. Then, as shown in FIG. 2, since the horizontal start signal STH is delayed by the gate delay time t2, the falling edge is similarly delayed by the gate delay time t2.

As a result, the fall time of the image signal Vs is also delayed by the gate delay time t2, and as shown in FIG. 2, the gate signal Vg rises relatively earlier than the image signal Vs by the gate delay time t2. It will be in the state of falling.

As described above, in the liquid crystal display device 10 according to the present embodiment, the gate signal Vg is raised to the write voltage Vgh in two stages, so that there is little occurrence of blunting at the time of start-up, and insufficient writing as in the prior art. It does not occur and there is no adverse effect on the image.

Although the power supply selection circuit is built in the gate driver in the above embodiment, it may be constituted by an independent circuit.

[0044]

According to the flat display device of the present invention, since the gate signal is raised to the write voltage in two steps, the gate signal is less rounded than when the voltage is suddenly raised from the reference voltage, resulting in insufficient writing. No clear image can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a gate signal and an image signal according to the present embodiment.

FIG. 3 is a timing chart of signals output from a liquid crystal controller.

FIG. 4 is a waveform diagram near a start end of a scanning line.

FIG. 5 is a waveform diagram near the end of a scanning line.

[Explanation of symbols]

 Reference Signs List 10 liquid crystal display device 12 liquid crystal panel 14 array substrate 16 signal line 18 scanning line 20 TFT 22 pixel electrode 24 source driver 28 gate driver 30 liquid crystal controller

Claims (2)

[Claims] 1. An array substrate comprising a plurality of signal lines and scanning lines arranged orthogonally to each other, and pixel electrodes arranged via switching elements near intersections of the signal lines and the scanning lines. A signal line drive circuit connected to the signal line and supplying an image signal; and a scan connected to the scan line and supplying a gate signal for writing the image signal to the pixel electrode by turning on the switching element. A flat panel display device comprising: a line driving circuit; and wherein the scanning line driving circuit temporarily increases the gate signal from a reference voltage to an intermediate voltage, and then increases the gate signal to a writing voltage. A horizontal start signal for instructing a timing for generating the image signal to the signal line driving circuit; a vertical start signal for instructing a timing for generating the gate signal; A control circuit for outputting an output inhibition signal to the scanning line driving circuit, wherein the scanning line driving circuit receives the output inhibition signal on the basis of a time at which the vertical start signal is input, and then outputs the gate signal 2. The flat display device according to claim 1, wherein the gate signal is increased to a write voltage after the output inhibit signal is stopped.