KR20080022801A - Liquid crystal diplay - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to dispose a source driver to drive source lines arranged in a column direction of an LC panel, thereby reducing the number of source driver ICs(Integrated Circuits) and accordingly reducing manufacturing costs of the LCD. An LC panel(150) includes source lines arranged in a column direction, gate lines arranged in a row direction, and LC cells respectively disposed in areas formed by intersection between the source lines and the gate lines. A timing controller(110) stores a first image signal sequentially inputted in the column direction order from the outside, and sequentially outputs a second image signal and control signals in the row direction order. A source driver(140) drives the source lines in response to the control signals and the image signals. A gate driver(120) drives the gate lines in response to the control signals.

Description

Liquid crystal display {LIQUID CRYSTAL DIPLAY}

1 is a view showing the configuration of a liquid crystal display according to a preferred embodiment of the present invention;

2 is a block diagram showing an example of a specific configuration of the timing controller 110 shown in FIG. 1;

3A and 3B show an order in which image data signals are input / output to / from the first and second frame memories shown in FIG. 2; And

4 is a diagram illustrating a configuration of a timing controller according to another embodiment of the present invention.

* Description of the main parts of the drawing

The present invention relates to a liquid crystal display device.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

The liquid crystal panel of the TFT_LCD includes a plurality of pixels, each of which includes a switching transistor connected to the data line and the gate line, a crystal capacitor and a storage capacitor connected thereto. Each pixel selectively receives a data voltage corresponding to an image signal through a switching element. The TFT-LCD also includes a gate driver for applying a gate-on voltage to the gate line, a data driver for applying an image signal to the data line, and a signal control circuit for controlling them.

In general, the data driver and the gate driver each include a plurality of integrated circuits and are disposed around the liquid crystal panel. As the resolution of the liquid crystal panel increases, a technique for securing a charging time of pixels configured in the liquid crystal panel is required for stable image display. In addition, in order to produce liquid crystal panels having various aspect ratios according to a user's request, consideration of an arrangement structure and a driving method of a data driver and a gate driver is also required.

In general, the ratio of the horizontal dimension to the vertical dimension of the liquid crystal panel is larger than the vertical dimension, such as 15: 9, 16: 9, or 16:10. Therefore, the number of source drivers arranged in the horizontal direction of the liquid crystal panel is required more than the number of gate drivers.

Recently, a technique for integrating a gate driver onto a substrate using amorphous silicon has been developed. According to this technique, the gate driver manufacturing cost is reduced and the circuit area is reduced. However, the source driver still needs to be implemented as a separate integrated circuit to be connected to the board, so a technique for reducing the number of source drivers is required.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can reduce the number of source drivers.

According to a feature of the present invention for achieving this object, a liquid crystal display device includes: a liquid crystal panel, a timing controller, a source driver and a gate driver. The liquid crystal panel includes a plurality of source lines arranged in a row direction, a plurality of gate lines arranged in a column direction, and liquid crystal cells respectively disposed in regions formed by an intersection of the source lines and the gate lines. do. The timing controller stores the first image signals sequentially input from the outside in the row direction order, and outputs the second image signals and the control signals sequentially in the column direction order. A source driver drives the source lines in response to the control signals and the image signal, and a gate driver drives the gate lines in response to the control signals.

The timing controller may include a first frame memory, a second frame memory, and the first image signal sequentially input from the outside in the row direction order of the first or second frame memories. And a control logic for storing the second image signal and the control signals sequentially in the column direction from one of the first or second frame memories.

In this embodiment, the first image signal sequentially input from the outside in the row direction order is an image signal of a k (k is a positive integer) frame, and the other of the first or second frame memories. The second video signal output from the video signal is a k-1th frame video signal.

The timing controller may include the frame memory including first and second regions, and the first image signal sequentially input from the outside in the row direction. And control logic for storing the second image signal and the control signals in one of two regions and sequentially outputting the second image signal and the control signals from the other one of the first or second regions of the frame memory in the column direction order. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a configuration of a liquid crystal display according to a preferred embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display 100 may include a timing controller 110, a gate driver 120, a voltage converter 130, a source driver 140, and a liquid crystal panel 150.

The liquid crystal panel 150 includes a plurality of gate lines G1 -Gm arranged in a column direction, a plurality of source lines S1 -Sn arranged in a row direction and intersecting the gate lines, a gate line and data. It includes pixels arranged in each of the regions defined by the lines. Each pixel includes a thin film transistor T1 having a gate electrode and a source electrode connected to a gate line and a data line, and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected to a drain electrode of the thin film transistor T1. Include. In this pixel structure, when the gate lines are sequentially selected by the gate driver 120, and when the gate-on voltage is applied in the form of a pulse to the selected gate line, the thin film transistor T1 of the pixel connected to the gate line is turned on. Subsequently, a voltage including pixel information is applied to each data line by the source driver 130. The voltage is applied to the liquid crystal capacitor C _LC and the storage capacitor C _ST through the thin film transistor of the pixel, and a predetermined display operation is performed by driving the liquid crystal and storage capacitors C _LC and C _ST .

The timing controller 110 receives a pixel data signal RGB, a horizontal sync signal H_SYNC, a vertical sync signal V_SYNC, a clock signal MCLK, and a data enable signal DE input from an external device. The timing controller 110 outputs the pixel data signal RGB ′ and the control signals obtained by converting the data format to match the interface specification with the source driver 140 to the source driver 140. Control signals provided from the timing controller 110 to the source driver 140 include a latch signal TP, a horizontal synchronization start signal STH, a start horizontal signal, and a horizontal clock signal HCLK.

The voltage converter 150 receives a power supply voltage VDD from an external source, and various voltages necessary for the operation of the liquid crystal display 100, for example, a gate on voltage VON, a gate off voltage VOFF, and an analog power source. A voltage AVDD, a digital power supply voltage DVDD, and a common voltage VCOM are generated. The gate on voltage VON and the gate off voltage VOFF are provided to the gate driver 120, and the analog power supply voltage AVDD and the digital power supply voltage DVDD are used as operating voltages of the liquid crystal display 100.

The gate driver 120 responds to control signals provided from the timing controller 110, that is, the vertical synchronization start signal STV, the gate clock signal GCLK, and the output enable signal OE. The gate lines G1 -Gm of 140 are sequentially scanned. Here, scanning refers to sequentially applying the gate-on voltage VON to the gate lines to make the pixel of the gate line to which the gate-on voltage VON is applied to enable data writing.

The source driver 140 controls the gray level voltage in response to control signals provided from the timing controller 110, that is, the latch signal TP, the horizontal synchronization start signal STH, the clock signal HCLK, and the afterimage elimination signal REX. The source lines S1 -Sn of the liquid crystal panel 150 are driven with gray voltages corresponding to the pixel data signal RGB 'among the gray voltages from the generator (not shown).

In the exemplary embodiment of the present invention, since the gate lines in the liquid crystal panel 150 are arranged in the column direction, the gate driver 120 is arranged on the upper side of the liquid crystal panel 150, and the source lines are arranged in the row direction. ) Is arranged on the left side of the liquid crystal panel 150. In another embodiment, the gate driver 120 may be arranged on the lower side of the liquid crystal panel 150, and in another embodiment, the source driver 140 may be arranged on the right side of the liquid crystal panel 150 or the liquid crystal panel 150 may be disposed on the right side of the liquid crystal panel 150. It may be arranged distributed to the left and right of the.

The timing controller 110 according to an embodiment of the present invention sequentially receives and stores the pixel data signal RGB in row order from the outside in synchronism with the main clock signal MCLK input from the outside, and in the column direction order. The pixel data signal RGB 'is sequentially output. In addition, the timing controller 100 may output control signals STV, GCLK, OE, TP, STH, and HCLK suitable for driving n source lines arranged in a row direction and m gate lines arranged in a column direction. Output

Accordingly, the gate driver 120 sequentially drives the m gate lines G1 -Gm arranged in the column direction of the liquid crystal panel 150, and the source driver 140 drives the n source lines arranged in the row direction. It is driven at a voltage corresponding to the image data signal RGB '.

As described above, the gate driver 120 integrates into the substrate using amorphous silicon. The source driver 140 includes a plurality of source driver integrated circuits. In general, the ratio of horizontal to vertical size of the liquid crystal panel is such that 15: 9, 16: 9 or 16:10, the horizontal size is larger than the vertical size, and the source driver is a source line arranged in the column direction of the liquid crystal panel. Drive them.

In the embodiment of the present invention, since the source driver 140 drives the source lines arranged in the row direction of the liquid crystal panel 150, the source driver 140 drives the source lines arranged in the column direction of the liquid crystal panel. The number of integrated circuits is reduced. Therefore, the manufacturing cost of the liquid crystal display device 100 can be reduced.

FIG. 2 is a block diagram illustrating an exemplary configuration of the timing controller 110 shown in FIG. 1.

Referring to FIG. 2, the timing controller 110 includes a first frame memory 210, a second frame memory 220, and a control logic 230. The control logic 230 stores the image data signal RGB sequentially input from the outside in the row direction in one of the first or second frame memories 210 and 220, and the first or second The image data signal RGB ′ is sequentially read from the other one of the frame memories 210 and 220 in the column direction, and provided to the source driver 140. In addition, the control logic 230 may provide control signals MCLK, STH, TP, and STV to be provided to the source driver 140 and the gate driver 120 in response to signals H_SYNC, V_SYNC, DE, and HCLK input from the outside. , GCLK, OE).

3A and 3B illustrate the order in which the image data signal is input / output to / from the first and second frame memories 210 and 220 shown in FIG. 2.

First, referring to FIG. 3A, the image data signal RGB of the k-th frame input from the outside is sequentially stored in the first frame memory 210. In this case, the order H1-Hn in which the image data signals are stored in the first frame memory 210 corresponds to the rows of the liquid crystal panel 150 shown in FIG. 1, that is, the source lines S1 -Sn. Meanwhile, the image data signal RGB of the k-1th frame stored in the second frame memory 220 while the image data signal RGB of the kth frame input from the outside is sequentially stored in the first frame memory 210. ') Is output sequentially. In this case, the order V1 -Vn of the image data signals read from the second frame memory 220 corresponds to the columns of the liquid crystal panel 150 illustrated in FIG. 1, that is, the gate lines G1 -Gm. . Therefore, when the gate line G1 is driven, the source lines S1 -Sn are driven according to the image data signal V1 output from the second frame memory 220. In this way, while the image data signal of the k-th frame is stored in the first frame memory 210, the liquid crystal panel 150 is connected to the liquid crystal panel 150 by the image data signal of the k-1 th frame read out from the second frame memory 220. The image is displayed.

3B illustrates that the image data signal RGB of the k + 1 th frame input from the outside is sequentially stored in the second frame memory 220, and the image data signal of the k th frame stored in the first frame memory 210 (FIG. RGB ') is output to the liquid crystal panel 150. As in FIG. 3A, the liquid crystal panel 150 is driven by the k-th frame image data signal read out from the first frame memory 210 while the image data signal of the k + 1th frame is stored in the second frame memory 220. The image is displayed on the screen.

As described above, the timing controller 110 stores the image data signal RGB sequentially input from the outside in the row direction in one of the first or second frame memories 210 and 220, and the first Alternatively, the image data signal RGB ′ is sequentially output from the other one of the second frame memories 210 and 220 to the source driver 140 in the column direction, so that the liquid crystal is changed even if the positions of the gate driver and the source driver are changed. An image may be normally displayed on the panel 150.

4 shows a timing controller 110 according to another embodiment of the present invention. The timing controller 400 shown in FIG. 4 includes one frame memory 410 and control logic 420. The frame memory 410 has a size capable of storing image data signals of at least two frames. In this embodiment, the frame memory 410 is divided into a first region 411 and a second region 412.

The control logic 420 stores the image data signal RGB sequentially inputted from the outside in the row direction in one of the first or second regions 411 and 412 of the frame memory 410, and The image data signal RGB 'is sequentially output from the other of the first or second regions 411 and 412 of the frame memory 410 in the column direction. Therefore, even if the positions of the gate driver and the source driver are changed, the image can be normally displayed on the liquid crystal panel.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention, since the source driver is arranged to drive the source lines arranged in the row direction of the liquid crystal panel, the number of source driver integrated circuits compared to the source driver driving the source lines arranged in the column direction of the liquid crystal panel. Decreases. Therefore, the manufacturing cost of the liquid crystal display device can be reduced.

In addition, since the timing controller sequentially outputs image data signals sequentially input from the outside in the row direction, the image may be normally displayed on the liquid crystal panel even when the positions of the gate driver and the source driver are changed.

Claims (4)

A liquid crystal panel comprising a plurality of source lines arranged in a row direction, a plurality of gate lines arranged in a column direction, and liquid crystal cells disposed in regions formed by intersections of the source lines and the gate lines, respectively and; A timing controller configured to store first image signals sequentially input from the outside in the row direction order, and output second image signals and control signals sequentially in the column direction order; A source driver driving the source lines in response to the control signals and the image signal; And And a gate driver for driving the gate lines in response to the control signals. The method of claim 1, The timing controller, A first frame memory; Second frame memory; And The first image signal sequentially input from the outside in the row direction order is stored in any one of the first or second frame memories, and the column direction order from the other of the first or second frame memories. And control logic to sequentially output the second image signal and the control signals. The method of claim 2, The first image signal sequentially input from the outside in the row direction order is an image signal of a k (k is a positive integer) frame, and is output from the other one of the first or second frame memories. The video signal is a video signal of the k-1th frame. The method of claim 1, The timing controller, A frame memory including first and second regions; And The first image signal sequentially input from the outside in the row direction order is stored in any one of the first or second regions of the frame memory, and the other one of the first or second regions of the frame memory is stored. And control logic for sequentially outputting the second image signal and the control signals in order from one to the column direction.

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