KR101351384B1 - Image Display Device and Driving Method the same - Google Patents

Abstract

The present invention relates to an image display apparatus, and more particularly, to an image display apparatus which compensates for distortion of a scan pulse.

The present invention provides a semiconductor device comprising: a gate wiring and a data wiring crossing each other to define a pixel region; A gate driver generating a scan pulse and supplying the scan pulse to one side of the gate line according to a gate output signal; A compensation voltage supply unit configured to output a compensation voltage in synchronization with the gate output signal; And a scan pulse compensator for supplying the compensation voltage to the other side of the gate line according to the scan pulse, wherein the compensating voltage supply part outputs the compensation voltage to the scan pulse compensator according to the gate output signal. It is characterized by including a switching element.

Compensation Voltage, Scan Pulse

Description

Image Display Device and Driving Method the same

1 schematically illustrates a problem of a liquid crystal display according to the related art.

2 is a block diagram schematically illustrating a driving unit of a liquid crystal display according to a first embodiment of the present invention.

3 is a circuit diagram illustrating a compensation voltage supply unit and a scan pulse compensator of the liquid crystal display according to the first embodiment of the present invention.

4 is a waveform diagram illustrating the gate wiring driving of the liquid crystal display according to the first embodiment of the present invention.

5 is a waveform diagram illustrating the gate wiring driving of the liquid crystal display according to the second exemplary embodiment of the present invention.

6 is a diagram illustrating a compensation voltage supply unit and a scan pulse compensator of a liquid crystal display according to a third exemplary embodiment of the present invention.

7 is a diagram illustrating a compensation voltage supply unit and a scan pulse compensator of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS OF THE DRAWINGS FIG.

105: liquid crystal panel 200: compensation voltage supply unit

220: scan pulse compensation unit 400: power generation unit

GOE: Gate output signal SP: Scan pulse

CV: Compensation Voltage VGH: Gate High Voltage

VGL: Gate Low Voltage

The present invention relates to an image display apparatus, and more particularly, to an image display apparatus which compensates for distortion of a scan pulse.

A liquid crystal display device, which is a kind of image display device, displays an image by controlling light transmittance of the liquid crystal by using an electric field. The liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix, and for driving the liquid crystal panel. It includes a drive circuit.

The driving circuit includes a gate driver for driving gate lines, a data driver for driving data lines, and a timing controller for controlling the gate driver and the data driver.

The gate driver includes a shift register for sequentially outputting scan pulses, and the shift register includes a plurality of stages that are connected to each other.

Each of the plurality of stages receives at least one clock pulse among a plurality of clock pulses having a sequential phase difference from each other, sequentially outputs scan pulses, and sequentially applies them to the gate lines of the liquid crystal panel.

However, the liquid crystal display according to the prior art has the following problems.

1 schematically illustrates a problem of a liquid crystal display according to the related art.

As the liquid crystal display device gradually increases in size, the RC resistance of the liquid crystal panel increases, and as shown in FIG. 1, the scan pulse applied to the gate wiring becomes distorted as the distance from the gate driver increases.

That is, as the gate wiring provided in the liquid crystal panel moves away from the gate driver, scan pulse distortion occurs due to a delay caused by the RC resistance of the gate wiring.

When the scan pulse is distorted, the turn-on of the thin film transistor is delayed, so that sufficient data cannot be charged in the pixel region, thereby degrading the image quality.

The present invention has been made to solve the above problems, an object of the present invention is to gate the compensation voltage corresponding to the high level of the scan pulse through the compensation voltage supply unit and the scan pulse compensation unit for supplying the compensation voltage to the gate wiring; The present invention provides an image display apparatus which compensates distortion of scan pulses and improves image quality by supplying the wirings.

In order to achieve the above technical problem, the image display device according to the present invention includes a gate wiring and a data wiring crossing each other to define a pixel region; A gate driver generating a scan pulse and supplying the scan pulse to one side of the gate line according to a gate output signal; A compensation voltage supply unit configured to output a compensation voltage in synchronization with the gate output signal; And a scan pulse compensator for supplying the compensation voltage to the other side of the gate line according to the scan pulse, wherein the compensating voltage supply part outputs the compensation voltage to the scan pulse compensator according to the gate output signal. It is characterized by including a switching element.

The present invention provides a distortion of scan pulses by supplying a compensation voltage corresponding to a high level of a scan pulse to the gate wiring through a compensation voltage supply unit for outputting a compensation voltage and a scan pulse compensation unit for supplying the compensation voltage to the gate wiring. To compensate.

In order to achieve the above technical problem according to the present invention, a method of driving an image display device including a gate line and a data line crossing a mutually defining pixel region, wherein the scan pulse is generated according to a gate output signal. Supplying to one side of the gate wiring; Outputting a compensation voltage to the scan pulse compensation unit through a first switching element of a compensation voltage supply unit to be synchronized with the gate output signal; And supplying the compensation voltage supplied to the scan pulse compensator to the other side of the gate line according to the scan pulse.

The present invention provides a distortion of scan pulses by supplying a compensation voltage corresponding to a high level of a scan pulse to the gate wiring through a compensation voltage supply unit for outputting a compensation voltage and a scan pulse compensation unit for supplying the compensation voltage to the gate wiring. To compensate.

The scan pulse compensator may include a control terminal to which scan pulses from the gate line are supplied; And an input / output terminal for inputting / outputting a compensation voltage according to the voltage of the control terminal, and the control terminal and the output terminal may be shorted.

In addition, in order to achieve the above object, the present invention provides a method of driving an image display apparatus including a gate wiring and a data wiring crossing each other to define a pixel region, and generating a scan pulse according to a gate output signal. Supplying to one side of the gate wiring; Outputting a compensation voltage in synchronization with the gate output signal; And supplying the compensation voltage to the other side of the gate line according to the scan pulse.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

2 is a block diagram schematically illustrating a driving unit of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 2, the driving unit of the liquid crystal display according to the first exemplary embodiment of the present invention is a liquid crystal panel 105, a gate driver 115, a data driver 125, a compensation voltage supply unit 200, and scan pulse compensation. The unit 220 includes a timing controller 300 and a power generator 400.

The liquid crystal panel 105 has an intersection area of n gate lines G1 to Gn, m data lines D1 to Dm, and n gate lines G1 to Gn and m data lines D1 to Dm. It comprises a thin film transistor (TFT) formed in.

The thin film transistor TFT supplies a data signal from the data lines D1 to Dm to the liquid crystal cell in response to the scan pulses from the gate lines G1 to Gn, and the liquid crystal cell faces the liquid crystal between the liquid crystal cells. Since the pixel electrode is composed of a common electrode and a pixel electrode connected to the thin film transistor TFT, the liquid crystal capacitor Clc may be equivalently represented.

The liquid crystal cell includes a storage capacitor Cst to maintain the data signal charged in the liquid crystal capacitor Clc until the next data signal is charged.

The gate driver 115 is formed on one side of the gate lines G1 to Gn to supply scan pulses to the n gate lines G1 to Gn, and the gate control signal from the timing controller 300. And a shift register that sequentially generates a scan pulse, that is, a gate high voltage VGH, in response to (GCS).

The gate control signal GCS may include a gate start pulse GSP and a gate shift clock GSC and a gate driver 115 that designate a time at which the thin film transistor TFT is turned on. It includes a gate output signal (GOE) for adjusting the width of the scan pulse output from the.

The data driver 125 has three colors arranged from the timing controller 300 according to the data control signal DCS supplied from the timing controller 300 to supply data signals to the m data lines D1 to Dm. The data signal is converted into a video data signal, which is an analog signal, and a data signal for one horizontal line is supplied to the data lines D1 to Dm for each horizontal period in which scan pulses are supplied to the gate lines G1 to Gn. do.

The compensation voltage supply unit 200 is configured to supply the compensation voltage CV to the scan pulse compensation unit 220, and synchronizes the compensation voltage CV in synchronization with the gate output signal GOE from the timing controller 300. Output to the scan pulse compensation unit 220.

The scan pulse compensator 220 is formed to compensate for the distortion of the scan pulses supplied to the gate lines G1 to Gn, and the compensation voltage CV from the compensating voltage supply part 200 according to the scan pulse. ) Is supplied to the other side of the gate lines G1 to Gn.

The timing controller 300 generates a gate control signal GCS to control the gate driver 115, generates a data control signal DCS to control the data driver 125, and simultaneously generates a gate output signal. It is formed to apply to the compensation voltage supply unit 220, the data control signal DCS using the main clock (MCLK), the data enable signal (DE), the horizontal and vertical synchronization signals (Hsync, Vsync) input from the outside And a gate control signal GCS are generated to control each of the gate driver 115 and the data driver 125, and supply three-color data RGB from the outside to the data driver 125.

The power generator 400 is formed to supply power to the gate driver and the liquid crystal panel, and turns on the thin film transistor TFT in accordance with the gate control signal GCS by using an input power Vin from the outside. To apply the electric field to the liquid crystal layer, the gate high voltage VGH to turn on, the gate low voltage VGL to turn off the thin film transistor TFT according to the gate control signal GCS, In order to compensate for distortion of the common voltage Vcom and scan pulses supplied to the liquid crystal panel 105, a compensation voltage CV supplied to the compensation voltage supply unit 200 is generated.

The compensation voltage CV has a high level of the scan pulse, that is, the same level as the gate high voltage VGH.

Hereinafter, the structure and operation of the compensation voltage supply unit 200 and the scan pulse compensation unit 220 which are features of the present invention will be described in detail.

3 is a circuit diagram illustrating a compensation voltage supply unit and a scan pulse compensator of the liquid crystal display according to the first embodiment of the present invention.

As can be seen in Figure 3, the compensation voltage supply unit 200 according to the first embodiment of the present invention is composed of a first transistor (TR1) as a switching element.

The first transistor TR1 outputs the compensation voltage CV from the power generator 400 to the scan pulse compensator 220 in synchronization with the gate output signal GOE of the timing controller 300. However, since the first transistor TR1 is controlled according to the second logic state of the gate output signal GOE, that is, the low level, it is preferable to use a PMOS transistor.

The scan pulse compensator 220 includes a second transistor TR2 and a resistor R, which are switching elements, and the second transistor TR2 and the resistor R are connected to each of the gate lines G1 to Gn. It is.

The second transistor TR2 is synchronized with the scan pulses of the gate lines G1 to Gn to compensate for the compensation voltage CV from the compensation voltage supply unit 200, that is, from the output terminal of the first transistor TR1. The voltage CV is input to the input terminal and output to the output terminal connected to the gate lines G1 to Gn. However, since the second transistor TR2 is controlled according to the first logic state of the scan pulse, that is, the high level, it is preferable to use an NMOS transistor.

In addition, the resistor R is connected between the output terminal and the control terminal of the second transistor TR2 for the potential difference between the output terminal and the control terminal of the second transistor TR2.

When the resistor R is larger than the resistances of the gate lines G1 to Gn, the compensation voltage CV may not be properly supplied to the gate lines G1 to Gn due to a voltage drop. R) is preferably designed smaller than the resistances of the gate lines G1 to Gn.

However, the resistor R is to improve the characteristics of the second transistor TR2 as a switching element by forming a potential difference between the output terminal and the control terminal of the second transistor, and the second resistor without the resistor R is performed. Even when the output terminal and the control terminal of the transistor TR2 are shorted, the compensation voltage CV may be supplied to the gate lines G1 to Gn.

4 is a waveform diagram illustrating the gate wiring driving of the liquid crystal display according to the first embodiment of the present invention.

As shown in FIG. 4, in the liquid crystal display according to the first exemplary embodiment of the present invention, when the gate output signal GOE is applied to the gate driver 115, the scan pulse may be entered into a second logic state, that is, a low level. SP, that is, the gate high voltage VGH is sequentially applied to each of the gate lines G1 to Gn.

In detail, when the gate output signal GOE is in a first logic state, that is, at a high level, a gate low voltage VGL is applied to each of the gate lines G1 to Gn, and the gate output signal GOE is applied. When entering the second logic state, that is, the low level, the gate high voltage VGH is applied to each of the gate lines G1 to Gn to turn on the thin film transistor.

In this case, the compensation voltage CV from the power generator 400 is input to the input terminal of the compensation voltage supply unit 200 and then the gate of the timing controller 300 is input to the control terminal of the first transistor TR1. The output terminal of the first transistor TR1 is output in synchronization with the output signal GOE.

Since the compensation voltage CV is used to compensate for the scan pulse SP distortion in the gate line, the compensation voltage CV preferably has the same waveform as the scan pulse SP applied to the gate lines G1 to Gn.

The compensation voltage CV output to the output terminal of the first transistor TR1 is applied to the second transistor TR2 of the scan pulse supply unit 220 connected to each of the gate lines G1 to Gn. The output pulses of the second transistor TR2 are output in synchronization with the scan pulses SP of G1 to Gn.

The compensation voltage CV output to the second transistor TR2 is applied to each of the gate lines G1 to Gn through the resistor R.

On one side of each of the gate lines G1 to Gn, a scan pulse SP from the gate driver 115 is applied, and on the other side where the scan pulse compensator 220 is formed, compensation of the same waveform as the scan pulse SP is performed. Since the voltage CV is applied, the scan pulse SP distorted by the RC delay of the gate line can be compensated.

After that, when the gate output signal GOE enters the first logic state, that is, the high level, the gate low voltage VGL is applied to each gate line G1 to Gn.

When the gate output signal GOE enters a high level, the first transistor TR1 synchronized with the gate output signal GOE is also turned off, so that the compensation voltage CV also includes the scan pulse compensation unit 220. It is not supplied with

Second Embodiment

5 is a waveform diagram illustrating the gate wiring driving of the liquid crystal display according to the second exemplary embodiment of the present invention.

The liquid crystal display according to the second exemplary embodiment of the present invention is a gate high voltage VGH generated by the power generator 400 and applied to the gate driver 115, and generated by the power generator 400 to compensate the voltage supply unit. Except for the waveform of the compensation voltage CV applied to 200, the structure and the driving method are the same as those of the first embodiment described above.

As can be seen from FIG. 5, the liquid crystal display according to the second exemplary embodiment of the present invention has a gate low voltage at each gate line G1 to Gn when the gate output signal (GOE) is in a first logic state, that is, a high level. When VGL is applied and the gate output signal GOE enters the second logic state, that is, the low level, the gate high modulation voltage VGH_M is applied to the gate lines G1 to Gn instead of the gate high voltage VGH. It is sequentially applied to turn on the thin film transistor (TFT).

The gate high modulation voltage VGH_M swings between a gate high voltage VGH level and a driving voltage Vdd level within one horizontal period. In this case, a time period occupied by the gate high voltage VGH level and the driving voltage Vdd level within the horizontal period may vary according to the charging characteristics of the liquid crystal.

As the gate high modulation voltage VGH_M is used instead of the gate high voltage VGH, the time taken for the thin film transistor TFT to turn from the turn-on state to the turn-off state is shortened, thereby improving image quality.

In this case, the compensation voltage CV, which is input from the power generator 400 to the input terminal of the compensation voltage supply unit 200, also includes the gate high modulation voltage VGH_M instead of the gate high voltage VGH.

The compensation voltage CV2 output to the output terminal of the first transistor TR1 is applied to the second transistor TR2 of the scan pulse supply unit 220 connected to each of the gate lines G1 to Gn. The output pulses of the second transistor TR2 are output in synchronization with the scan pulses SP of G1 to Gn.

The compensation voltage CV2 output to the second transistor TR2 is applied to each of the gate lines G1 to Gn through the resistor R.

After that, when the gate output signal GOE enters the first logic stage, that is, the high level, the gate lines G1 to Gn maintain the gate low voltage VGL.

As the gate output signal GOE enters a high level, since the first transistor TR1 of the compensation voltage supply unit 200 synchronized with the gate output signal GOE is turned off, the first transistor TR1 is turned off. ), The gate high modulation voltage VGH_M cannot be output to the output terminal.

In addition, since the second transistor TR2 of the scan pulse compensator 220 synchronized with the scan pulse SP is turned off, the gate line is maintained at the gate low voltage VGL.

Here, the first transistor TR1 of the compensation voltage supply unit 200 has a gate high swinging between a gate high voltage VGL level and a driving voltage Vdd level while the gate output signal GOE maintains a high level. The modulation voltage VGH_M serves to block the gate lines G1 to Gn from being applied.

Third Embodiment

6 is a diagram illustrating a compensation voltage supply unit 200 and a scan pulse compensator 220 of the liquid crystal display according to the third embodiment of the present invention.

The compensation voltage supply unit 200 includes an inverter 202 and a first transistor TR1.

The inverter 202 inverts the gate output signal GOE supplied from the timing controller 300 and supplies it to the first transistor TR1 and the scan pulse compensator 220.

Here, the inverter 202 outputs the low level gate output signal GOE at a high level and the high level gate output signal GOE at a low level.

The first transistor TR1 supplies the compensation voltage CV to the scan pulse compensator 220 according to the inverted gate output signal GOE from the inverter 202.

The scan pulse compensator 220 includes a plurality of second and third transistors TR2 and TR3 connected to the other side of each of the gate lines G1 to Gn.

The second transistor TR2 is turned on in response to the gate high voltage VGH supplied to the corresponding gate lines G1 to Gn to convert the compensation voltage CV from the first transistor TR1 into the third transistor TR3. )

The third transistor TR3 is turned on in response to the inverted gate output signal GOE from the inverter 202 so that the compensation voltage CV from the second transistor TR2 is applied to the corresponding gate wirings G1 to Gn. Supply to the other side of).

In this case, the first, second, and third transistors TR1, TR2, and TR3 use the same type of transistor. For example, the first, second, and third transistors TR1, TR2, and TR3 may use NMOS or PMOS transistors, and FIG. 6 shows the first, second, and third transistors TR1, TR2, and TR3. Shows a case where all are NMOS transistors.

Referring to the operation of the compensation voltage supply unit 200 and the scan pulse compensation unit 220 as follows.

When the gate output signal GOE of the timing controller 300 is supplied to the inverter 202, the inverter 202 inverts the gate output signal GOE and supplies it to the first and third transistors TR1 and TR3.

Specifically, the case where the gate output signal GOE is at the low level will be described below.

When the low level gate output signal GOE is input, the inverter 202 outputs a high level gate output signal GOE. Accordingly, the first and third transistors TR1 and TR3 are both turned on according to the high level gate output signal GOE.

In the meantime, the gate high voltage VGH is supplied to one of the gate lines G1 to Gn during a period in which the low level gate output signal GOE is input to the input terminal of the inverter 202. Therefore, the second transistor TR2 is turned on by the gate high voltage VGH by the gate lines G1 to Gn. Here, assume that the gate high voltage VGH is supplied to the first gate line G1 in the period.

As described above, in the period in which the low level gate output signal GOE is supplied to the inverter 202, the second and third transistors TR1 and TR3 connected to the first gate line G1 are connected. Transistor TR2 is turned on.

Accordingly, the compensation voltage CV via the first transistor TR1 is the gate high voltage VGH through the turned-on second transistor TR2 and the third transistor TR3 and the first gate wiring G1. Is supplied.

The compensation voltage CV is supplied to the second to n-th gate lines G1 to Gn in the same manner as the driving method of the first gate line G1 described above.

Therefore, when scan pulses are supplied to one side of the gate lines G1 to Gn, the compensation voltage supplying unit 200 and the scan pulse compensating unit 220 supply the scan pulses to the other side of the gate lines G1 to Gn, thereby providing RC. Distortion due to resistance can be prevented.

On the other hand, the case where the gate output signal GOE is at the high level will be described below.

When the high level gate output signal GOE is input, the inverter 202 outputs a low level gate output signal GOE.

Accordingly, the first and third transistors TR1 and TR3 are both turned off by the low level gate output signal GOE, and the second transistor TR2 is turned off according to the gate low voltage VGL. do. Therefore, the compensation voltage CV is not supplied to the other side of the gate lines G1 to Gn.

Fourth Embodiment

7 is a diagram illustrating a compensation voltage supply unit 200 and a scan pulse compensator 220 of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

The compensation voltage supply unit 200 includes an inverter 202 and a first transistor TR1.

The inverter 202 inverts the gate output signal GOE supplied from the timing controller 300 and supplies it to the first transistor TR1 and the scan pulse compensator 220.

Here, the inverter 202 outputs the low level gate output signal GOE at a high level and the high level gate output signal GOE at a low level.

The first transistor TR1 supplies the compensation voltage CV to the scan pulse compensator 220 according to the inverted gate output signal GOE from the inverter 202.

The scan pulse compensator 200 includes a plurality of second and third transistors TR2 and TR3 connected to the other side of each of the gate lines G1 to Gn.

The second transistor TR2 is turned on in response to the gate high voltage VGH supplied to the corresponding gate lines G1 to Gn to convert the compensation voltage CV from the first transistor TR1 into the third transistor TR3. )

The third transistor TR3 is turned on in accordance with the compensation voltage CV from the second transistor TR2 to convert the compensation voltage CV from the first transistor TR1 to the corresponding gate wirings G1 to Gn. It is supplied to the other side of the.

The third transistor TR3 is patterned in the same manner as the thin film transistor in the pixel region. That is, the third transistor TR3 is formed by a mask pattern designed in the same manner as the mask pattern for manufacturing the thin film transistor in the pixel region.

In addition, the first, second, and third transistors TR1, TR2, and TR3 use the same type of transistor. For example, the first, second, and third transistors TR1, TR2, and TR3 may use NMOS or PMOS transistors, and FIG. 6 shows the first, second, and third transistors TR1, TR2, and TR3. Shows a case where all are NMOS transistors.

Referring to the operation of the compensation voltage supply unit 200 and the scan pulse compensation unit 220 as follows.

When the gate output signal GOE of the timing controller 300 is supplied to the inverter 202, the inverter 202 inverts the gate output signal GOE and supplies the inverted gate signal to the first transistor TR1.

Specifically, the case where the gate output signal GOE is at the low level will be described.

When the low level gate output signal GOE is input, the inverter 202 outputs a high level gate output signal GOE. Accordingly, the first transistor TR1 is turned on according to the high level gate output signal GOE.

In the meantime, the gate high voltage VGH is supplied to one of the gate lines G1 to Gn during a period in which the low level gate output signal GOE is input to the input terminal of the inverter 202. Therefore, the second transistor TR2 is turned on by the gate high voltage VGH by the gate lines G1 to Gn. Here, assume that the gate high voltage VGH is supplied to the first gate line G1 in the period.

As described above, the first transistor TR1 is turned on in the period in which the low level gate output signal GOE is supplied to the inverter 202. In addition, the second transistor TR2 connected to the first gate line G1 is turned on, and the third transistor TR3 connected to the second transistor TR2 is turned on.

Accordingly, the gate high voltage VGH becomes the first gate line G1 through the second transistor TR2 and the third transistor TR3 that are turned on by the compensation voltage CV via the first transistor TR1. Is supplied.

The compensation voltage CV is supplied to the second to n-th gate lines G1 to Gn in the same manner as the driving method of the first gate line G1 described above.

Therefore, when scan pulses are supplied to one side of the gate lines G1 to Gn, the compensation voltage supplying unit 200 and the scan pulse compensating unit 220 supply the scan pulses to the other side of the gate lines G1 to Gn, thereby providing RC. Distortion due to resistance can be prevented.

On the other hand, the case where the gate output signal GOE is at the high level will be described below.

When the high level gate output signal GOE is input, the inverter 202 outputs a low level gate output signal GOE.

Accordingly, the first transistor TR1 is turned off by the low level gate output signal GOE, and the second transistor TR2 is turned off according to the gate low voltage VGL. In addition, the third transistor TR3 is turned off by the second transistor TR2 that is turned off. Therefore, the compensation voltage CV is not supplied to the other side of the gate lines G1 to Gn.

As described above, the image display device and the driving method thereof according to the present invention include a compensation voltage supply unit and a scan pulse compensation unit capable of compensating for distortion of the scan pulse due to the RC delay of the gate wiring. The image quality can be improved by preventing distortion.

In addition, since the compensation voltage supply unit and the scan pulse compensator are formed of a simple circuit on one side of the gate line, the compensation voltage supply unit and the scan pulse compensator may be formed together when forming the gate line and the data line in the liquid crystal panel. Can compensate.

Claims (17)

A gate wiring and a data wiring crossing each other to define a pixel region; A gate driver generating a scan pulse and supplying the scan pulse to one side of the gate line according to a gate output signal; A compensation voltage supply unit configured to output a compensation voltage in synchronization with the gate output signal; And A scan pulse compensation unit configured to supply the compensation voltage to the other side of the gate line according to the scan pulse, And the compensation voltage supply unit includes a first switching element to output the compensation voltage to the scan pulse compensator in accordance with the gate output signal. The method of claim 1, And the first switching element outputs the compensation voltage to the scan pulse compensator in accordance with a low level state which is a second logic state of the gate output signal. The method of claim 1, And the scan pulse compensator outputs the compensation voltage according to a high level of the first logic state of the scan pulse. The method of claim 1, The scan pulse compensator A control terminal to which the scan pulse from the gate wiring is supplied; And It includes an input and output terminal for inputting and outputting the compensation voltage in accordance with the voltage of the control terminal, And the control terminal and the output terminal are short-circuited switching elements. 5. The method of claim 4, And a resistor is connected between the output terminal and the control terminal. The method of claim 5, And the resistance is smaller than the resistance of the gate wiring. The method of claim 1, And the gate driver supplies the scan pulse to the gate wiring in accordance with a second logic state of the gate output signal. The method of claim 7, wherein And the gate driver supplies a scan pulse swinging between a high level of the scan pulse and a driving voltage level to the gate wiring in accordance with a second logic state of the gate output signal. The method of claim 1, And the compensation voltage supplies a scan pulse swinging between a high level of the scan pulse and a driving voltage level to the gate wiring in accordance with a second logic state of the gate output signal. The method of claim 1, The compensation voltage supply unit further includes an inverter for inverting and outputting a logic state of the gate output signal. And the first switching device includes a first switching device for supplying the compensation voltage to the scan pulse supply unit according to the inverted gate output signal from the inverter. The method of claim 10, The scan pulse compensation unit, A second switching element for outputting the compensation voltage from the first switching element in accordance with a scan pulse supplied to the gate wiring; And And a third switching element for supplying the compensation voltage from the second switching element to the other side of the gate wiring in accordance with the inverted gate output signal. The method of claim 10, The scan pulse compensation unit, A second switching element for outputting the compensation voltage from the first switching element in accordance with a scan pulse supplied to the gate wiring; And And a third switching element for supplying the compensation voltage from the first switching element to the other side of the gate wiring in accordance with the compensation voltage from the second switching element. A driving method of an image display apparatus including a gate wiring and a data wiring crossing each other to define a pixel region, Generating a scan pulse according to a gate output signal and supplying the scan pulse to one side of the gate line; Outputting a compensation voltage to the scan pulse compensation unit through a first switching element of a compensation voltage supply unit to be synchronized with the gate output signal; And And supplying the compensation voltage supplied to the scan pulse compensator to the other side of the gate line in accordance with the scan pulse. 14. The method of claim 13, Outputting a compensation voltage to be synchronized with the gate output signal Inverting and outputting the gate output signal using an inverter; And And outputting the compensation voltage according to the inverted gate output signal by using the first switching element. The method of claim 14, The step of supplying the compensation voltage to the other side of the gate wiring in accordance with the scan pulse Outputting the compensation voltage from the first switching element according to a scan pulse supplied to the gate wiring using a second switching element; And And supplying the compensation voltage from the second switching element to the other side of the gate wiring using a third switching element in accordance with the inverted gate output signal. The method of claim 14, The step of supplying the compensation voltage to the other side of the gate wiring in accordance with the scan pulse Outputting the compensation voltage from the first switching element according to a scan pulse supplied to the gate wiring using a second switching element; And And supplying the compensation voltage from the first switching element to the other side of the gate wiring using a third switching element in accordance with the compensation voltage from the second switching element. Driving method. 14. The method of claim 13, And the first switching element outputs the compensation voltage to the scan pulse compensator in accordance with a low level state which is a second logic state of the gate output signal.

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