KR101777126B1 - Driving apparatus for liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device and a driving method thereof, which can reduce power consumption while further improving the display quality by applying an optimized charge share level to a data line charge sharing technique A data driver for driving a plurality of data lines; a gate driver for driving a plurality of gate lines; a data driver for supplying image data inputted from the outside to the data driver, A timing controller for controlling the data driver, and a data switching unit for charge-sharing the plurality of data lines in a predetermined charge share level in at least one frame period or at least during a horizontal period in response to a control signal from the outside Characterized by .

Description

Technical Field [0001] The present invention relates to a driving apparatus for a liquid crystal display,

The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display device capable of reducing power consumption while further improving display quality by applying an optimized charge- And a method of driving the same.

BACKGROUND ART [0002] Lightweight thin flat panel displays (LCDs) are mainly used as image display devices used in monitors for personal computers, portable tablet terminals, notebooks, and various information devices. As such flat panel display devices, a liquid crystal display, a light emitting display, a plasma display panel, a field emission display, and the like are emerging.

The flat panel display devices include a display panel in which a plurality of pixel cells are arranged and a driving circuit for driving the display panel so that the image is displayed on the display panel by the driving circuit.

In recent years, in order to further improve the display quality of an image, that is, the image quality of a display image, a version driving method and a charge share technique are further applied in driving the display panel. Herein, the inversion driving method is a driving method of inverting the polarity of the data voltage supplied to each data line of the display panel, and the charge sharing technique shortens all of the data lines during the initial period of every horizontal period in which the data voltage is supplied, To be shared. When the charge sharing technique is applied while inverting the polarity of the data voltage applied to each pixel cell in units of horizontal lines, it is possible to prevent the display failure due to the horizontal crosstalk phenomenon or the afterimage and reduce the power consumption.

However, the present charge sharing scheme has a problem that the charge sharing level is unstable because the voltage level at the time of application of the charge share is varied irregularly from time to time. Thus, there arises a problem that the charge-share characteristic at the time of charge-share operation becomes unstable and the luminance unevenness of the display image occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a driving apparatus for a liquid crystal display device capable of reducing the power consumption while further improving the display quality by setting and fixing an optimized charge- And a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving a liquid crystal display including a liquid crystal panel including a plurality of pixels, a data driver driving a plurality of data lines, a gate driving a plurality of gate lines, A driver for supplying image data inputted from the outside to the data driver, a timing controller for controlling the gate and the data driver, and a timing controller for supplying the image data to the data driver in at least one frame period or at least during a horizontal period in a charge sharing period And a data switching unit for charge-sharing the plurality of data lines to a predetermined charge share level.

The data switching unit may include at least one of a charge-sharing unit that supplies a video signal from the data driver to each of the data lines or charge-share each of the data lines, and a data driving control signal generated from the timing controller And a charge share control section for controlling a charge share operation of the charge share section in a charge sharing period during at least one frame period or a horizontal period and supplying a preset charge share voltage to the charge share section.

The predetermined charge share voltage is set to either a predetermined reference voltage at a level at which black data is displayed or a positive gamma voltage at a level at which black data is displayed and a negative gamma voltage at a level at which black data is displayed And is supplied to each of the data lines during the charge sharing period.

Wherein the charge sharing unit includes a plurality of first switching elements for supplying the video signal to each of the plurality of data lines in response to a charging control signal from the charge sharing control unit, And a plurality of second switching elements for supplying a charge sharing voltage supplied from the charge share controller to each of the data lines.

Wherein the charge sharing unit supplies a video signal to each of the data lines in response to the charging control signal or supplies a charge sharing voltage supplied from the charge sharing control unit to each of the data lines .

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display (LCD) device, comprising: supplying image data input from an external source to a data driver; And displaying an image on the liquid crystal panel, wherein the step of displaying an image on the liquid crystal panel comprises the steps of: setting data lines of the liquid crystal panel in a charge occupancy period during at least one frame period or at least one horizontal period, And charge-sharing the shared level.

Wherein the charge sharing is performed by supplying a video signal from the data driver to each of the data lines using the charge share unit or by charge sharing each of the data lines and generating data from the timing controller using the charge share control unit Controlling the charge sharing operation of the charge sharing section in at least one frame period or a charge sharing period in a horizontal period according to at least one of a driving control signal and a driving control signal and supplying a preset charge sharing voltage to the charge sharing section .

The predetermined charge share voltage is set to either a predetermined reference voltage at a level at which black data is displayed or a positive gamma voltage at a level at which black data is displayed and a negative gamma voltage at a level at which black data is displayed And is supplied to each of the data lines during the charge sharing period.

Wherein the charge share step includes supplying the video signal to each of the plurality of data lines in accordance with a charging control signal from the charge sharing control unit using a plurality of first switching elements, And supplying the charge sharing voltage supplied from the charge share control unit to each of the data lines in response to a charging control signal of the control unit.

Wherein the charge sharing step comprises supplying the video signal to each of the data lines in accordance with the charging control signal using a plurality of multiplexers or supplying a charge sharing voltage supplied from the charge sharing control part to each of the data lines .

The driving apparatus and the driving method of the liquid crystal display according to the present invention having the above-described features set and fixed the optimized charge share level and apply it to the data line charge sharing technique so that at least one frame period or at least one So that a black image can be displayed in the charge sharing period during the horizontal period. Accordingly, the liquid crystal display of the present invention can reduce the power consumption while further improving the display image quality.

1 is a block diagram schematically showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention.
2 is a configuration diagram illustrating the data driver and the data switching unit shown in FIG. 1;
3 is a circuit diagram specifically showing the charge-share section shown in FIG. 2. FIG.
Fig. 4 is an input / output waveform diagram of the data switching unit shown in Fig. 3; Fig.
FIG. 5 is another circuit diagram specifically showing the charge share section of FIG. 3; FIG.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a driving apparatus for a liquid crystal display according to an embodiment of the present invention.

1 includes a liquid crystal panel 2 formed with a plurality of pixels, a data driver 4 for driving a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, A timing controller 8 for supplying image data RGB inputted from the outside to the data driver 4 and for controlling the data driver 4 and the gate driver 6, And a data switching unit 10 for charge-sharing the plurality of data lines DL1 to DLm to a predetermined charge share level in at least one frame period or at least during a horizontal period in a charge sharing period.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies data signals from the data lines DL1 to DLm to the pixel electrodes in response to a scan pulse from the gate lines GL1 to GLn, that is, a gate-on signal. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, a source output enable SOE (Source Output Enable) signal to the data lines DL1 to DLm. In other words, the data driver 4 latches the digital image data input according to the SSC, then converts the digital image data Data into analog data signals, and outputs the analog data signals to the gate lines GL1 to GLn in response to the SOE signal A data signal for one horizontal line is supplied to each data line DL1 to DLm for every one horizontal period in which the scan pulse is supplied. At this time, the data driver 4 selects a gamma voltage having a predetermined level according to the gray level value of the digital image data Data, and supplies the selected gamma voltage to each of the data lines DL1 to DLm as a data signal.

The gate driver 6 receives a gate control signal GCS from the timing controller 8, for example, a gate start pulse (GSP), a gate shift clock (GSC) A gate pulse signal or a gate output enable (GOE) signal to the gate lines GL1 to GLn.

The timing controller 8 arranges image data (RGB) from the outside so as to be suitable for driving the liquid crystal panel 2 and supplies it to the data driver 4. [ A gate control signal GCS and a data control signal DCS are generated using external synchronization signals DCLK, DE, Hsync and Vsync and the data driver 4 and the gate driver 6 are respectively controlled do.

The data switching unit 10 is provided with at least one data control signal DCS from the timing controller 8 for at least one frame period or at least one horizontal period using a SOE signal, The data lines DL1 to DLm are charge-shared to a predetermined charge share level. To this end, the data switching unit 10 receives the SOE, the vertical synchronizing signal Vsync, and the like among the data control signals DCS from the timing controller 8 and receives the data from the data driver 4 as the charge sharing charge sharing voltage It is also supplied with a gamma voltage to supply.

The data switching unit 10 responds to the SOE or the vertical synchronizing signal Vsync supplied from the timing controller 8 to switch the data lines DL1 to DLm in at least one frame period or in a charge- Charge share. During the charge sharing of the data lines DL1 to DLm, the positive polarity (+) gamma voltage at the level at which the black data is displayed or the predetermined reference voltage at the level at which the black data is displayed and the polarity -) gamma voltage to each data line DL1 to DLm with a charge sharing voltage.

2 is a block diagram showing the data driver and the data switching unit shown in FIG.

2 includes a shift register 21 for outputting a sampling signal (SAM) in response to the SSP and the SSC from the timing controller 8, (VData) from the power supply unit 10 and the timing controller 8 from the timing controller 8 to the latch unit 22 for sequentially sampling the data (Data) sequentially and outputting one line of data (RData) sampled in accordance with the SOE signal, A gamma voltage generating unit 24 for generating a gamma voltage GV in response to a gamma control signal GVC of the latch unit 24 and a gamma voltage GV supplied from the gamma voltage generating unit 24, A digital-to-analog converter (DAC) 23 for converting one line of data (RData) from the DAC 23 into an analog video signal AData and outputting the analog video signal AData AData) to be supplied to the data lines DL1 to DLm And a buffer 25.

The shift register 21 generates the sampling signal SAM by using the SSC and the SSP from the timing controller 8. [ Specifically, the shift register 21 generates the sampling signal SAM by shifting the source start pulse SSP according to the SSC, and sequentially supplies the sampling signal SAM to the latch unit 22. [

The latch unit 22 sequentially samples the image data Data supplied from the timing controller 8 through the data bus line in accordance with the sampling signal SAM from the shift register 21. The sampled data is stored in units of one horizontal line, and the latched image data (RData) for one horizontal line is simultaneously output to the DAC 25 in response to the SOE signal.

The gamma voltage generating section 24 generates a series connection (not shown) between the first and second voltages (not shown) in response to the driving voltage VDD from the power supply section 10 and the gamma control signal GVC from the timing controller 8 (+) And negative (-) gamma voltages (GV) and a plurality of positive (+) and negative (-) gamma voltages (GV) in a divided mode between a plurality of resistors And supplies it to the DAC 23.

The DAC 23 outputs the image data RData to the positive polarity (+) using the plurality of positive (+) or negative (-) gamma voltages GV supplied in accordance with the polarity control signal from the timing controller 8. [ ) Or a negative (-) analog video signal AData and outputs the converted video signal AData for one line to the output buffer 25 at the same time. Here, the polarity control signal is inverted in units of one horizontal line. More specifically, when the plurality of positive (+) gamma voltages GV are supplied from the gamma voltage generator 24 by the polarity control signal, the DAC 23 outputs the video data RData from the latch 22, (+) Gamma voltage (GV) corresponding to the analog video signal (AData). If a plurality of negative (-) gamma voltages GV are supplied from the gamma voltage generator 24, a negative (-) gamma voltage GV corresponding to the image data RData is selected, Signal (AData) and outputs it.

The output buffer 25 outputs the video signal AData using the driving voltage VDD in order to prevent the video signal AData from the DAC 23 from being distorted according to the RC time constant of the data lines DL1 to DLm. And supplies the amplified video signal AData to the data switching unit 10. [

The data switching unit 10 supplies a video signal AData from the data driver 4 to each of the data lines DL1 to DLm or a charge sharing unit for charge sharing each of the data lines DL1 to DLm And a charge sharing controller 14 for controlling the charge sharing operation of the charge sharing section 14 according to the SOE or the vertical synchronizing signal Vsync and supplying the charge sharing section 14 with a preset charge sharing voltage, 12.

The charge sharing unit 14 supplies the video signal AData to the respective data lines DL1 to DLm in the video display period in response to the charging control signal CSS from the charge share control unit 12, The data lines DL1 to DLm are all shorted to charge-share the data lines DL1 to DLm. More specifically, in the charge sharing, the data lines DL1 to DLm are all shorted, and then the charge share voltages supplied through the charge share control unit 12 are supplied to the data lines DL1 to DLm. Here, the predetermined charge share voltage is a predetermined reference voltage VRef at a level at which the black data is displayed or a positive (+) gamma voltage PBV at which the black data is displayed at the time of charge sharing of the data lines DL1 to DLm ) And a negative (-) gamma voltage (NBV) having a level at which black data is displayed.

The charge share controller 12 responds to the SOE or the vertical synchronizing signal Vsync so that the charge sharing unit 14 supplies the video signal AData to the respective data lines DL1 to DLm during the video display period of at least one horizontal period, And supplies the generated charging control signal CSS to the charge sharing unit 14. [ During the charge sharing period of at least one horizontal period, the charge sharing unit 14 generates the charging control signal CSS to charge the plurality of data lines DL1 to DLm to a predetermined charge sharing voltage, And supplies it to the charge share section 14. The charge share control section 12 and the charge share section 14 may be formed outside the data driver 4 such as a non-display region of the liquid crystal panel 2, a printed circuit film, have. Also, the charge share controller 12 and the charge share unit 14 may be built in the data driver 4.

3 is a circuit diagram specifically showing the charge-share section shown in Fig.

The charge share section 14 shown in Fig. 3 receives the video signal AData supplied from the output buffer 25 of the data driver 4 in response to the charging control signal CSS from the charge- A plurality of first switching elements Tr1, Tr2 and Tr3 for supplying the respective data lines DL1 to DLm to the charge sharing controller (DL1 to DLm) in response to the charging control signal CSS, And a plurality of second switching elements T1, T3, and T5 for supplying the charge sharing voltages supplied from the plurality of data lines DL1 to DLm, respectively, to the data lines DL1 to DLm.

When the charge share control unit 12 and the charge share unit 14 are embedded in the data driver 4, the first and second switching elements Tr1 to Tr3, T1 To T3 may be separated and incorporated in the data driver 4. [ Here, each of the first switching elements Tr1 to Tr3 may be a PMOS switching transistor, and each of the second switching elements T1 to T3 may be a PMOS switching transistor. Therefore, the charging control signal CSS can be a signal in which one bit of high or low is periodically repeated. In response to this charging control signal CSS, the first and second switching elements Tr1 to Tr3, T3 operate opposite to each other.

Specifically, each of the plurality of first switching elements Tr1 to Tr3 is formed so as to correspond to the first to third data lines DL1 to DL3, respectively. In accordance with the charging control signal CSS inputted to the base terminal, The analog data voltage input to the terminal is output to the collector terminal. Here, each of the plurality of first switching elements Tr1 to Tr3 is turned on when a low level charging control signal CSS is inputted, and can supply the video signal AData to the respective data lines DL1 to DL3 have. Then, when the charging control signal CSS of high level is inputted, it is turned off.

Each of the plurality of second switching elements T1 to T3 is formed to correspond to each of the first to third data lines DL1 to DL3. When the charge sharing voltage is supplied to the source terminals of the NMOS switching elements T1 to T3, the charge sharing voltage is output to the drain terminal in accordance with the charging control signal CSS input to each gate terminal. Here, each of the plurality of second switching elements T1 to T3 is turned on when a high-level charging control signal CSS is input, and supplies the charge sharing voltage to each of the plurality of data lines DL1 to DL3 . When the low level of the charging control signal CSS is inputted, it is turned off. Although only the PMOS and NMOS switching elements Tr1 to Tr3 and T1 to T3 corresponding to the first to third data lines DL1 to DL3 are shown in FIG. 3, a plurality of PMOS and NMOS switching elements Tr1 to Trn, T1 To Tn may be formed to correspond to the plurality of data lines DL1 to DLm, respectively.

4 is an input / output waveform diagram of the data switching unit shown in FIG.

4, the charge share controller 12 generates the charging control signal CSS in accordance with the SOE signal input from the timing controller 8. [

The charge share controller 12 turns off the plurality of first switching elements Tr1 to Tr3 during the charge sharing period in which the SOE signal is input to the high level and blocks the output of the video signal AData . The plurality of second switching elements T1 to T3 are turned on so that the charge sharing voltage CSV is supplied to each of the plurality of data lines DL1 to DL3. Here, the charge share controller 12 may supply the SOE signal as the charging control signal CSS in accordance with the phase of the SOE signal. If a charge sharing voltage CSV is supplied to a plurality of data lines DL1 to DL3 during at least one frame period to display a black image, a charging control signal CSS can be generated and supplied in units of at least one frame period have.

On the other hand, the charge share controller 12 turns on the plurality of first switching elements Tr1 to Tr3 during the video display period in which the SOE signal is input at a low level, for example, To be supplied to the data lines DL1 to DL3, respectively. Then, the plurality of second switching elements T1 to T3 are turned off.

In this case, since the preset charge share voltage, that is, the charge share voltage at the optimized level is set and fixed and applied to the data line charge sharing technique, the power consumption can be reduced while further improving the display quality of the image.

5 is another circuit diagram specifically showing the charge share portion of FIG.

The charge share unit 26 shown in Fig. 5 outputs the video signal AData supplied from the output buffer 25 of the data driver 4 in response to the charging control signal CSS from the charge share control unit 12, And a plurality of multiplexers 41 to 43 for supplying the charge sharing voltages CSV to the data lines DL1 to DLm or the charge sharing voltages CSV supplied from the charge share control unit 12 to the data lines DL1 to DLm, respectively.

Each of the multiplexers 41 to 43 supplies a charge sharing voltage CSV to each of the data lines DL1 to DL3 when a high level charging control signal CSS is inputted and a low level charging control signal CSS And can supply a video signal AData to each of the data lines DL1 to DLm when inputted.

Although only the first through third multiplexers 41 through 43 corresponding to the first through third data lines DL1 through DL3 are shown in FIG. 5, the plurality of multiplexers correspond to the plurality of data lines DL1 through DLm, respectively. .

As described above, the driving apparatus and driving method of the liquid crystal display according to the embodiment of the present invention set and lock the preset charge share voltage, that is, the optimized charge sharing voltage, As a result, it is possible to further reduce the power consumption while improving the display quality of the image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

Claims (10)

A liquid crystal panel formed with a plurality of pixels,
A data driver for driving the plurality of data lines,
A gate driver for driving a plurality of gate lines,
A timing controller for supplying image data inputted from the outside to the data driver and controlling the gate and the data driver,
In response to a control signal from the outside, the plurality of data lines in a charge sharing period during at least one frame period or at least one horizontal period is divided into a first voltage, which is a predetermined reference voltage at a level at which black data is displayed, To a voltage level of a third voltage which is a negative gamma voltage of a level at which black data is displayed and a second voltage which is a positive polarity gamma voltage of the liquid crystal display device . The method according to claim 1,
The data switching unit
A charge sharing unit for supplying a video signal from the data driver to each of the data lines or for charge sharing each of the data lines,
A charge sharing operation of the charge sharing section is controlled in at least one frame period or a charge sharing period in a horizontal period according to at least one of a data driving control signal generated from the timing controller, A charge sharing voltage among a first voltage which is a predetermined reference voltage, a second voltage which is a positive polarity gamma voltage at which a black data is displayed and a third voltage which is a negative polarity gamma voltage at which a black data is displayed, And a charge sharing control unit for supplying the charge sharing control signal to the share unit. delete 3. The method of claim 2,
The charge-
A plurality of first switching elements for supplying the video signal to each of the plurality of data lines in response to a charging control signal from the charge-
And a plurality of second switching elements for shorting the data lines in response to the charging control signal to supply the charge sharing voltage supplied from the charge share controller to each of the data lines. Device. 3. The method of claim 2,
The charge-
And a plurality of multiplexers for supplying the video signal to each of the data lines in response to a charging control signal from the charge share control unit or supplying a charge sharing voltage supplied from the charge sharing control unit to each data line And the driving device of the liquid crystal display device. Arranging image data inputted from the outside and supplying to the data driver,
And displaying the image on the liquid crystal panel by controlling the gate and the data driver,
The step of displaying an image on the liquid crystal panel
Data lines of the liquid crystal panel in a charge sharing period during at least one frame period or at least one horizontal period using a data switching unit, a first voltage which is a predetermined reference voltage of a level at which black data is displayed, A second voltage that is a polarity gamma voltage, and a third voltage that is a negative gamma voltage of a level at which black data is displayed. The method according to claim 6,
The charge share step
Supplying a video signal from the data driver to each of the data lines using a charge sharing section or charge-sharing each of the data lines; and
The charge sharing control unit controls the charge sharing operation of the charge sharing unit in at least one frame period or in a charge sharing period during the horizontal period according to at least one of the data driving control signals generated from the timing controller using the charge share control unit, And a third voltage that is a negative gamma voltage of a level at which black data is displayed, and a second voltage that is a positive gamma voltage of a level at which black data is displayed, and a third voltage that is a negative gamma voltage of a level at which black data is displayed To the charge sharing section. The method of driving a liquid crystal display device according to claim 1, further comprising: delete 8. The method of claim 7,
The charge share step
Supplying the video signal to each of the plurality of data lines in accordance with a charging control signal from the charge-sharing control unit using a plurality of first switching elements, and
And supplying the charge sharing voltage supplied from the charge share control unit to each of the data lines by shorting the data lines according to the charging control signal using the plurality of second switching elements. . 8. The method of claim 7,
The charge share step
A step of supplying the video signal to each of the data lines according to a charging control signal from the charge share control unit using a plurality of multiplexers or supplying a charge sharing voltage supplied from the charge share control unit to each of the data lines And a driving method of the liquid crystal display device.

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