KR100480176B1 - Liquid crystal display apparatus driven 2-dot inversion type and method of dirving the same - Google Patents

Abstract

The present invention provides a two-dot inversion driving method and a driving method thereof, which can prevent a luminance difference between scanning lines supplied with data voltages having the same polarity in the two-dot inversion driving method.

The present invention provides a two-dot inversion driving type liquid crystal display device in which a polarity of a data signal is inverted by a dot in a horizontal direction and inverted by a two-dot unit in a vertical direction, and the gate lines and the data lines intersect each other. A liquid crystal panel including a plurality of liquid crystal cells provided for each unit; A gate driver for driving the gate lines; A data driver for driving data lines in the two-dot inversion driving method and sequentially supplying a charge distribution voltage and a data signal to the data lines at horizontal periods so that the charging conditions of the data signals are the same for each gate line; And a timing controller for controlling the gate driver and the data driver.

Description

Liquid crystal display device with 2-dot inversion driving method and its driving method {LIQUID CRYSTAL DISPLAY APPARATUS DRIVEN 2-DOT INVERSION TYPE AND METHOD OF DIRVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of preventing a horizontal line phenomenon generated in a 2-dot inversion driving method.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In fact, the liquid crystal display includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix form as shown in FIG. 1, and a gate driver 4 for driving gate lines GL0 to GLn of the liquid crystal panel 2. ), A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 10 for controlling the gate driver 4 and the data driver 6. do.

The timing controller 10 controls the driving timing of the gate driver 4 and the data driver 6 in response to the main clock signals MCLK, horizontal and vertical synchronization signals H, V, and the like, which are input from the outside, and input video. The data signals R, G, and B are supplied to the data driver 6.

The gate driver 4 supplies the gate high voltage to the gate lines GL1 to GLn during the corresponding syringe period (1H) in response to the gate control signals from the timing controller 10, and applies the gate low voltage in the remaining period. Is authorized. In addition, the gate driver 4 applies a gate low voltage to the gate line GL0 formed at the uppermost side for the storage capacitor Cst of the first scan line.

The data driver 6 converts the digital data signals R, G, and B from the timing controller 10 into analog data signals in response to the data control signals from the timing controller 10 to the gate lines GL1 to GLn. The pixel voltage signal for one horizontal line is supplied to the data lines DL1 to DLm every one horizontal period 1H to which the gate high voltage is supplied to the plurality of gate lines. In this case, the data driver 6 converts the data driver 6 into an analog data signal using a gamma voltage from a gamma voltage generator (not shown). In particular, the data driver 6 determines the polarity of the data signals supplied to the data lines DL1 to DLm by converting the analog data signal using a negative polarity or a positive gamma voltage in response to the polarity inversion signal.

The liquid crystal panel 2 is a thin film transistor TFT formed at intersections of liquid crystal cells arranged in a matrix form and n + 1 gate lines GL0 to GLn and m data lines DL1 to DLm. It is provided. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate high voltages from the gate lines GL1 to GLn. The liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc including a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. Further, a storage capacitor Cst is further formed in the liquid crystal cell to hold the data signal charged in the liquid crystal capacitor Clc until the next data signal is charged, that is, while the gate low voltage is applied. The storage capacitor Cst is formed between the previous gate line and the pixel electrode. The liquid crystal cell realizes gray scale by controlling light transmittance by varying an arrangement state of liquid crystal having dielectric anisotropy according to a data signal charged through a thin film transistor (TFT).

In such a liquid crystal display device, in order to drive the liquid crystal cells on the liquid crystal panel 2, in-frame conversion method such as a frame inversion system, a line column inversion system, and a dot inversion system may be used. The version drive method is used. The liquid crystal panel driving method of the frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells on the liquid crystal panel every time the frame is changed. In the liquid crystal panel driving method of the line inversion method, the polarities of the data signals supplied to the liquid crystal cells are reversed according to a line (column) on the liquid crystal panel. The dot inversion scheme allows each of the liquid crystal cells on the liquid crystal panel to be supplied with a pixel voltage signal having a polarity opposite to that of the data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. The polarities of the data signals supplied to the cells are reversed. Of these inversion driving methods, the dot inversion method provides an image having excellent image quality compared to the frame and line inversion methods. The inversion driving is performed in response to the data driver 6 according to the polarity inversion signal supplied from the controller 10 to the data driver 6.

Generally, a liquid crystal display is driven by a frame frequency of 60 Hz. However, in a system requiring low power consumption such as a notebook computer, it is required to lower the frame frequency to 50 to 30 Hz. As the frame frequency is lowered, the flicker phenomenon occurs in the dot inversion method that provides excellent image quality among the inversion methods. Thus, a two-dot inversion type liquid crystal panel driving method as shown in FIGS. 2A and 2B is proposed. It became.

3A and 3B illustrate data signal polarities supplied to liquid crystal cells of a liquid crystal panel divided into odd frames and even frames by a 2-dot inversion liquid crystal panel driving method. In the odd and even frames shown in Figs. 3A and 3B, the two-dot inversion scheme changes the polarity of the data signal in the horizontal direction in the liquid crystal cell, that is, in the unit of dots, as in the conventional dot inversion scheme. It can be seen that the drive is changed in units of 2 dots in the direction. While the two-dot inversion method has the advantage that the flicker phenomenon is reduced compared to the dot inversion method in a commercial screen driven at a frame frequency of 50 Hz, the horizontal line is generated every two scanning lines depending on the luminance difference between the scanning lines. Have.

3A and 3B illustrate horizontal lines in the odd and even frames of the horizontal line phenomenon caused by the 2-dot inversion liquid crystal panel driving method. 3A and 3B, when the polarity of the liquid crystal cell is changed every two scan lines in the vertical direction, a horizontal phenomenon occurs due to the luminance difference between the odd scan lines G1 and the even scan lines G2. In the case of the 2-dot inversion method, as shown in FIGS. 4 and 5, the data voltage Vd at the even-numbered scan lines G2 to which the odd-numbered scan line is adjacent and the data voltage signal of the same polarity is supplied. This is because the charging characteristics are different.

4 shows the liquid crystal cell of the i th scan line and the i + 1 th scan line in the i th horizontal period (iH) and the i + 1 th horizontal period (i + 1H) by a 2-dot inversion driving method in an arbitrary frame. The waveforms of the positive data voltages Vdi and Vdi + 1 charged in the j-th liquid crystal cell [i, j], [i, j + 1] are shown.

First, in the i-th horizontal period iH, the shifted gate high voltage Vgh is supplied to the i-th scan line in response to the gate shift pulse GSC, and the corresponding data voltage is supplied to the data lines. The thin film transistors of the i-th scan line are turned on by the gate high voltage Vgh, so that only the liquid crystal cells of the i-th scan line are charged with the data voltage supplied to the data lines. For example, the positive data voltage Vdi supplied to the j-th data line is charged in the [i, j] -th liquid crystal cell with a predetermined rising period as shown in part A of FIG. This reaches the positive data voltage Vd from the negative voltage state that was supplied in the i-1 th scan line enable period until the [i, j] th liquid crystal cell is charged with the positive data voltage Vdi. This is because a predetermined rise period is required.

Subsequently, the shifted gate high voltage Vgh is supplied to the i + 1th scan line in response to the gate shift pulse GSC in the i + 1th horizontal period i + 1H, and the corresponding data voltage is supplied to the data lines. . The thin film transistors of the i + 1th scan line are turned on by the gate high voltage Vgh, so that only the liquid crystal cells of the i + 1th scan line are charged with the data voltage supplied to the data lines. For example, the positive data voltage Vdi + 1 supplied to the j-th data line is charged in the [i + 1, j] -th liquid crystal cell with almost no rising period as shown in part B of FIG. This is because the data voltage Vdi + 1 charged in the [i + 1, j] th liquid crystal cell is charged from the positive data voltage Vdi supplied to the i-th scan line enable period.

5 shows the liquid crystal cell of the i th scan line and the i + 1 th scan line in the i th horizontal period (iH) and the i + 1 th horizontal period (i + 1H) by the 2-dot inversion driving method in the next frame. The waveforms of the negative data voltages Vdi and Vdi + 1 charged in the j-th liquid crystal cell [i, j], [i, j + 1] are shown.

First, in the i-th horizontal period iH, the shifted gate high voltage Vgh is supplied to the i-th scan line in response to the gate shift pulse GSC, and the corresponding data voltage is supplied to the data lines. The thin film transistors of the i-th scan line are turned on by the gate high voltage Vgh, so that only the liquid crystal cells of the i-th scan line are charged with the data voltage supplied to the data lines. For example, the negative data voltage Vdi supplied to the j-th data line is charged in the [i, j] -th liquid crystal cell with a predetermined falling period as shown in part C of FIG. This reaches the negative data voltage Vd from the positive voltage state that was supplied in the i-1 th scan line enable period until the [i, j] th liquid crystal cell is charged with the negative data voltage Vdi. This is because a predetermined descent period required to take is required.

Subsequently, the shifted gate high voltage Vgh is supplied to the i + 1th scan line in response to the gate shift pulse GSC in the i + 1th horizontal period i + 1H, and the corresponding data voltage is supplied to the data lines. . The thin film transistors of the i + 1th scan line are turned on by the gate high voltage Vgh, so that only the liquid crystal cells of the i + 1th scan line are charged with the data voltage supplied to the data lines. For example, the negative data voltage Vdi + 1 supplied to the j-th data line is charged in the [i + 1, j] -th liquid crystal cell with almost no falling period as shown in part D shown in FIG. This is because the data voltage Vdi + 1 charged in the [i + 1, j] -th liquid crystal cell is charged from the negative data voltage Vdi supplied to the i-th scan line enable period.

As described above, in the 2-dot inversion driving method, when data voltages Vdi and Vdi + 1 having the same polarity are continuously supplied for two horizontal periods (iH and i + 1H), the i-th scan line and the i + 1 th scan line As the charging conditions of the supplied data voltages are different, the data voltages charged to the same luminance are changed. In particular, the data voltage charged in the i + 1 th scan line becomes larger than the data voltage charged in the i th scan line with a relatively long rise (fall) period. Accordingly, in the normal white mode, a horizontal line phenomenon occurs in which the i-th scan line appears brighter than the i + 1 th scan line, resulting in poor display quality.

Accordingly, an object of the present invention is to provide a two-dot inversion driving liquid crystal display device and a driving method thereof, which can prevent a luminance difference between scanning lines supplied with data voltages of the same polarity in a two-dot inversion driving method. It is.

In order to achieve the above object, the two-dot inversion drive type liquid crystal display according to the present invention is a two-dot drive in which the polarity of the data signal is inverted by a dot unit in the horizontal direction and inverted by 2 dots unit in the vertical direction An inversion drive type liquid crystal display device comprising: a liquid crystal panel including a plurality of liquid crystal cells provided at intersections of gate lines and data lines; A gate driver for driving the gate lines; A data driver for driving data lines in the two-dot inversion driving method and sequentially supplying the charge distribution voltage and the data signal to the data lines every one horizontal period such that the charging conditions of the data signals are the same for each scan line; And a timing controller for controlling the gate driver and the data driver.

The data driver is configured to supply a charge-sharing voltage to the data lines just before the gate high voltage is supplied to the gate lines so as to be charged in advance, and then supply the corresponding data signals to the data lines.

In particular, the data driver may include a first charge sharing voltage having a voltage greater than a common voltage supplied to the common electrode serving as a reference electrode of the liquid crystal cells in response to a polarity control signal from the timing controller as a charge sharing voltage, and smaller than the common voltage. And selectively supplying a second charge distribution voltage.

The data driver may include a shift register array for supplying a sequential sampling signal, a latch array for latching and outputting video data in response to a sampling signal, and a polarity of the video data from the latch array in the unit of dots in the horizontal direction. A digital-to-analog converter array for inverting and converting the data signal into an analog signal such that the polarity of the data signal is inverted every two horizontal periods, and a charge-sharing voltage generator for generating a charge-sharing voltage; And a multiplexer array configured to supply the charge distribution voltage and the data signal to the data lines step by step in a horizontal period.

The data driver may further include a buffer array positioned at an input terminal or an output terminal of the multiplexer array to buffer and output an input data signal.

In response to the polarity control signal from the timing controller, when the polarity control signal indicates positive polarity, the charge distribution voltage generator supplies a first charge distribution voltage greater than the common voltage supplied to the common electrode serving as a reference electrode of the liquid crystal cells. When the polarity control signal indicates negative polarity, the second charge distribution voltage smaller than the common voltage is supplied.

The charging / distributing voltage generator may generate the first and second charging / distributing voltages by dividing an input power supply voltage using a voltage divider connected in series.

In the method of driving a 2-dot inversion liquid crystal display device according to the present invention, in a liquid crystal panel including a plurality of liquid crystal cells provided at the intersections of the gate lines and the data lines, the polarity of the data signal is in the unit of dots in the horizontal direction. A driving method of a 2-dot inversion driving type liquid crystal display device which is inverted and inverted in a 2-dot unit in a vertical direction, wherein the charge distribution is applied to the data lines in horizontal periods so that the data signal charging condition is the same for each gate line. And sequentially supplying a voltage and a data signal.

In the step of supplying the data signal stepwise, the charge distribution voltage is supplied to the data lines just before the gate high voltage is supplied to the gate lines of the corresponding scan line to be charged in advance, and then the corresponding data signals are transferred to the data lines. Characterized in that the step of supplying the field.

In addition, when the polarity control signal indicates positive polarity in response to an input polarity control signal, a first charge distribution voltage greater than the common voltage supplied to the liquid crystal panel is supplied to the charge distribution voltage, and the polarity control signal is In the case of indicating negative polarity, a second charge sharing voltage smaller than the common voltage may be supplied.

Specifically, the step of supplying the data signal comprises the steps of generating a sequential sampling signal; Latching and outputting video data in response to a sampling signal; Converting the output video data into an analog signal so that the polarity of the data signal is inverted in the unit of dots in the horizontal direction and the polarity of the data signal is inverted every two horizontal periods; Generating a charge sharing voltage; And gradually supplying the charge distribution voltage and the data signal to the data lines every horizontal period.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 10.

FIG. 6 is a block diagram illustrating a data driver configuration of a liquid crystal display for a 2-dot inversion driving method according to an exemplary embodiment of the present invention.

According to an exemplary embodiment of the present invention, a two-dot inversion driving liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, a gate driver for driving gate lines of the liquid crystal panel, and driving data lines of the liquid crystal panel. And a timing controller for controlling the gate driver and the data driver.

The liquid crystal panel includes liquid crystal cells arranged in a matrix and thin film transistors formed at intersections of gate lines and data lines, respectively. The thin film transistor supplies a data signal from the data line to the liquid crystal cell in response to the gate high voltage from the gate line. The liquid crystal cell realizes gray scale by adjusting the light transmittance by varying the arrangement state of the liquid crystal having dielectric anisotropy according to the data signal charged through the thin film transistor.

The gate driver supplies the gate high voltage to the gate lines during the corresponding syringe in response to the gate control signals from the timing controller, and applies the gate low voltage in the remaining period.

The timing controller controls driving timing of the gate driver and the data driver, and supplies the input video data signals R, G, and B to the data driver 20.

The data driver 20 converts the digital data signals R, G, and B from the timing controller into analog data signals in response to the data control signals from the timing controller, and supplies them to the data lines D1 through Dm. In particular, the data driver makes the data voltage charging condition uniform for each scan line even when driven by a 2-dot inversion driving method using a charge sharing voltage. In other words, the data driver 20 first supplies the charge distribution voltage to the data lines every horizontal period, and then supplies the data voltage so that the data voltage is charged from the charge distribution voltage for each scan line.

To this end, the data driver 20 includes a shift register array 22 for supplying a sequential sampling signal as shown in FIG. 6, and a latch for latching and outputting video data R, G, and B in response to the sampling signal. The array 24, a digital-to-analog conversion (hereinafter referred to as DAC) array 26 for converting video data from the latch array 24 into an analog data signal, and a data signal from the DAC array 26. A buffer array 28 that buffers and outputs the charge distribution voltage generation unit 30 that generates the positive polarity and the second charge distribution voltage, and a multiplexer MUX selectively supplying the charge distribution voltage and the data signal for each horizontal period. An array 32 is provided.

A plurality of shift registers configured in the shift register array 22 sequentially shift the input source start pulse SSP according to the source sampling clock signal SSC to output the sampling signal.

A plurality of latches configured in the latch array 24 are sequentially latched by sampling input pixel data by a predetermined unit in response to a sampling signal from the shift register array 22 and simultaneously in response to a source output enable signal SOE. Output

A plurality of DACs configured in the DAC array 26 converts data from the latch array 24 into analog data signals using positive and negative gamma voltages from a gamma voltage unit (not shown). . In particular, the DAC array 26 converts the odd-numbered and even-numbered data signals to have polarities opposite to each other for the 2-dot inversion driving in response to the input polarity control signal POL, and the data every two horizontal periods (2H). Causes the polarity of the signal to be reversed.

The buffer array 28 buffers and outputs data signals output from the DAC array 26.

The charge sharing voltage generator 30 generates a first charge sharing voltage Vsa and a second charge sharing voltage Vsb in response to the polarity control signal. The first charge sharing voltage Vsa is set to be greater than the common voltage Vcom supplied to the common electrode, and the second charge sharing voltage Vsb is set smaller than the common voltage Vcom.

The multiplexer array 32 receives data lines from the charge share voltages Vsa and Vsb and the buffer array 28 from the charge share voltage generation unit 30 at horizontal periods in response to the input control signal CS. It is supplied to (D1-Dm) sequentially.

FIG. 7 shows the i-th scan in the i-th horizontal period (iH) and the i + 1-th horizontal period (i + 1H) by the 2-dot inversion driving method in an arbitrary frame by the data driver 20 shown in FIG. The waveforms of the positive data voltages Vdi and Vdi + 1 charged in the liquid crystal cell of the line and the jth liquid crystal cell ([i, j], [i, j + 1]) of the i + 1th scan line are shown.

First, in the i th horizontal period iH, the shifted gate high voltage Vgh is supplied to the i th scan line in response to the gate shift pulse GSC. Just before the gate high voltage Vgh is supplied, the multiplexer array 32 receives the charge share voltages Vsa and Vsb from the charge share voltage generator 30 in response to the polarity control signal POL. D1 to Dm). The multiplexer array 32 then supplies the data voltages from the buffer array 28 to the data lines D1-Dm. Accordingly, the thin film transistors of the i th scan line are turned on by the gate high voltage Vgh, so that the charge distribution voltage Vsa supplied to the data lines D1 through Dm is supplied to the liquid crystal cells of the i th scan line. , Vsb) and the data voltage are gradually charged. For example, the first charge distribution voltage Vsa is supplied and charged to the j-th data line Dj immediately before the gate high voltage Vgh is supplied. Subsequently, a positive data voltage Vdi is supplied to the j-th data line Dj. Accordingly, in the [i, j] -th liquid crystal cell, the data voltage Vdi is increased from the first charge distribution voltage Vsa that is already charged in the j-th data line Dj, as shown in part E of FIG. 7. The data voltage Vdi is charged in a shorter rising period than in the prior art.

Subsequently, the shifted gate high voltage Vgh is supplied to the i + 1th scan line in response to the gate shift pulse GSC in the i + 1th horizontal period i + 1H. Just before the gate high voltage Vgh is supplied, the multiplexer array 32 receives the charge share voltages Vsa and Vsb from the charge share voltage generator 30 in response to the polarity control signal POL. D1 to Dm). The multiplexer array 32 then supplies the data voltages from the buffer array 28 to the data lines D1-Dm. In this case, the data voltage supplied from the buffer array 28 has the same polarity as the data voltage supplied in the previous i-th horizontal period iH. Accordingly, the thin film transistors of the i + 1 th scan line are turned on by the gate high voltage Vgh, thereby charging the liquid crystal cells of the i + 1 th scan line to the data lines D1 through Dm. The division voltages Vsa and Vsb and the data voltage are charged in stages. For example, the first charge distribution voltage Vsa is supplied and charged to the j-th data line Dj immediately before the gate high voltage Vgh is supplied. Subsequently, a positive data voltage Vdi + 1 is supplied to the j-th data line Dj. Accordingly, in the [i, j] th liquid crystal cell, the data voltage Vdi + 1 increases from the first charge distribution voltage Vsa that is already charged in the jth data line Dj, as shown in part F of FIG. 7. As it begins to charge, the corresponding data voltage Vdi + 1 is charged within a shorter rising period than before.

FIG. 8 shows the i-th scan line in the i-th horizontal period iH and the i + 1-th horizontal period i + 1H by the 2-dot inversion driving method in the next frame by the data driver 20 shown in FIG. The waveforms of the positive data voltages Vdi and Vdi + 1 charged in the liquid crystal cell of < RTI ID = 0.0 > and < / RTI > the i < th >

First, in the i th horizontal period iH, the shifted gate high voltage Vgh is supplied to the i th scan line in response to the gate shift pulse GSC. Just before the gate high voltage Vgh is supplied, the multiplexer array 32 receives the charge share voltages Vsa and Vsb from the charge share voltage generator 30 in response to the polarity control signal POL. D1 to Dm). The multiplexer array 32 then supplies the data voltages from the buffer array 28 to the data lines D1-Dm. Accordingly, the thin film transistors of the i th scan line are turned on by the gate high voltage Vgh, so that the charge distribution voltage Vsa supplied to the data lines D1 through Dm is supplied to the liquid crystal cells of the i th scan line. , Vsb) and the data voltage are gradually charged. For example, the second charge distribution voltage Vsb is supplied and charged to the j-th data line Dj immediately before the gate high voltage Vgh is supplied. Subsequently, a negative data voltage Vdi is supplied to the j-th data line Dj. Accordingly, the data voltage Vdi is charged in the [i, j] th liquid crystal cell from the second charge distribution voltage Vsb that is already charged in the jth data line Dj, as shown in part G of FIG. 8. The data voltage Vdi is charged within a shorter falling period than before.

Subsequently, the shifted gate high voltage Vgh is supplied to the i + 1th scan line in response to the gate shift pulse GSC in the i + 1th horizontal period i + 1H. Just before the gate high voltage Vgh is supplied, the multiplexer array 32 receives the charge share voltages Vsa and Vsb from the charge share voltage generator 30 in response to the polarity control signal POL. D1 to Dm). The multiplexer array 32 then supplies the data voltages from the buffer array 28 to the data lines D1-Dm. In this case, the data voltage supplied from the buffer array 28 has the same polarity as the data voltage supplied in the previous i-th horizontal period iH. Accordingly, the thin film transistors of the i + 1 th scan line are turned on by the gate high voltage Vgh, thereby charging the liquid crystal cells of the i + 1 th scan line to the data lines D1 through Dm. The division voltages Vsa and Vsb and the data voltage are charged in stages. For example, the second charge distribution voltage Vsb is supplied and charged to the j-th data line Dj immediately before the gate high voltage Vgh is supplied. Subsequently, a negative data voltage Vdi + 1 is supplied to the j-th data line Dj. Accordingly, in the [i, j] th liquid crystal cell, as shown in part I of FIG. 8, the data voltage Vdi + 1 drops from the second charge distribution voltage Vsb already charged in the jth data line Dj. Since the battery starts to charge, the corresponding data voltage Vdi + 1 is charged within a shorter falling period than before.

As described above, even if the data voltages Vdi and Vdi + 1 having the same polarity are continuously supplied for two horizontal periods (iH, i + 1H) in the two-dot inversion driving method, the i-th scan line and the i + 1 scan line are pre-set in advance. Since the data voltage is charged from the charged charge distribution voltages Vsa and Vsb, the charging condition of the data voltage is uniform for each scan line. Accordingly, it is possible to prevent a horizontal line phenomenon caused by different charging conditions for each line charging the data voltage having the same polarity in the 2-dot inversion driving method. In addition, as the charge distribution voltages Vsa and Vsb and the data voltages are gradually supplied to the data lines, chargers may be shortened and power consumption may be reduced.

FIG. 9 is a detailed circuit diagram of the charge distribution voltage generation unit 30 shown in FIG. 6.

The charging / distributing voltage generator 30 shown in FIG. 9 divides the voltage using the first to third resistors R1, R2, and R3 connected in series to the power supply voltage VDD, thereby providing the first and second charge sharing voltages. (Vsa, Vsb) is generated. In detail, in the first node N1, the voltage voltage VDD is dropped by the first resistor R1 to generate the first charge distribution voltage Va. In the second node N1, the power supply voltage VDD is dropped by the first and second resistors R1 and R2 to generate the second charge distribution voltage Vb. The first and second charge distribution voltages Va and Vb generated at each of the first and second nodes N1 and N2 may perform a switching operation in response to the polarity control signal POL. It is supplied to the multiplexer array 32 via each of SW1 and SW2. When the polarity control signal POL indicates positive polarity, the first switch SW1 is turned on to supply the first charge distribution voltage Vsa, and the second switch SW2 is configured to supply the polarity control signal POL. In the case of indicating a negative polarity, it is turned on to supply the second charge distribution voltage Vsb.

FIG. 10 is a block diagram illustrating a data driver configuration of a liquid crystal display for a two-dot inversion driving method according to another exemplary embodiment of the present invention.

In contrast to the data driver 20 shown in FIG. 10, the data driver 40 shown in FIG. 10 shows that the multiplexer array 50 to which the charge-sharing voltage generator 48 is connected is installed at the input of the buffer array 52. Except for the same components.

The plurality of shift registers of the shift register array 42 sequentially shift the input source start pulse SSP according to the source sampling clock signal SSC and output the sampling signal.

A plurality of latches configured in the latch array 44 are sequentially latched by sampling input pixel data by a predetermined unit in response to a sampling signal from the shift register array 22 and simultaneously in response to a source output enable signal SOE. Output

A plurality of DACs configured in the DAC array 46 converts data from the latch array 44 into analog data signals using positive and negative gamma voltages from a gamma voltage unit (not shown). . In particular, the DAC array 44 converts the odd-numbered and even-numbered data signals to have polarities opposite to each other for the 2-dot inversion driving in response to the input polarity control signal POL, and the data every two horizontal periods (2H). Causes the polarity of the signal to be reversed.

The charge sharing voltage generator 48 generates a first charge sharing voltage Vsa and a second charge sharing voltage Vsb in response to the polarity control signal. The first charge sharing voltage Vsa is greater than the common voltage Vcom supplied to the common electrode as shown in FIG. 7, and the second charge sharing voltage Vsb is the common voltage Vcom as shown in FIG. 8. Set it smaller.

The multiplexer array 50 sequentially supplies the charge share voltages Vsa and Vsb from the charge share voltage generator 48 and the data signals from the DAC array 46 every horizontal period in response to the input control signal CS. do.

The buffer array 52 buffers the data signals output from the DAC array 46 and outputs them to the data lines D1 to Dm.

In the data driver 40 having such a configuration, the charge sharing voltages Vsa and sb and the data voltages are gradually supplied to the data lines D1 to Dm every horizontal period. Accordingly, in the two-dot inversion driving method, even if the data voltages Vdi and Vdi + 1 having the same polarity are continuously supplied for two horizontal periods (iH and i + 1H), the i th scan line and the i + 1 th scan line are not included. Since the data voltage is charged from the pre-charged charge distribution voltages Vsa and Vsb, the charging condition of the data voltage is uniform for each scan line. As a result, it is possible to prevent the horizontal line phenomenon caused by the different charging conditions for each line charging the data voltage having the same polarity in the 2-dot inversion driving method. In addition, as the charge distribution voltages Vsa and Vsb and the data voltages are gradually supplied to the data lines, chargers may be shortened and power consumption may be reduced.

As described above, in the two-dot inversion liquid crystal display according to the present invention and the driving method thereof, the data voltages of the same polarity are continuously supplied for two horizontal periods by supplying the charge distribution voltage and the data voltage stepwise to the data lines every horizontal period. Even if supplied, the charging condition of the data voltage becomes uniform for each scan line. As a result, in the two-dot inversion driving method, the image quality can be improved by preventing the horizontal line phenomenon caused by the different charging conditions for each line charging the same polarity data voltage. In addition, the two-dot inversion liquid crystal display device and the driving method thereof according to the present invention can shorten the data charger and reduce power consumption as the charge distribution voltage and the data voltage are gradually supplied to the data line.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram showing the configuration of a conventional liquid crystal display device.

2A and 2B illustrate polar patterns of data signals supplied to liquid crystal cells of a liquid crystal panel by a 2-dot inversion driving method.

3A and 3B are diagrams showing a horizontal line phenomenon by a 2-dot inversion driving method.

4 is a charging characteristic diagram of a positive data signal supplied to liquid crystal cells by a conventional two-dot inversion driving method.

5 is a charging characteristic diagram of a negative data signal supplied to liquid crystal cells in a conventional two-dot inversion driving method.

FIG. 6 is a block diagram illustrating a data driver configuration of a liquid crystal display device for a two-dot inversion driving method according to an exemplary embodiment of the present invention.

FIG. 7 is a charging characteristic diagram of a positive data signal supplied to liquid crystal cells in a 2-dot inversion manner by the data driver shown in FIG. 6; FIG.

FIG. 8 is a charging characteristic diagram of a negative data signal supplied to liquid crystal cells in a 2-dot inversion manner by the data driver shown in FIG. 6; FIG.

FIG. 9 is a detailed circuit diagram of the charge share voltage generation unit illustrated in FIG. 6.

FIG. 10 is a block diagram illustrating a data driver configuration of a liquid crystal display for a two-dot inversion driving method according to another exemplary embodiment of the present invention. FIG.

<Description of Symbols for Main Parts of Drawings>

2: liquid crystal panel 4: gate driver

6, 20, 40: data driver 10: timing controller

22, 42: shift register array 24, 44: latch array

26, 46: Digital-to-Analog Transform (DAC) Array

28, 52: buffer array

30, 48: charge distribution voltage generator

32, 50: multiplexer (MUX) array

Claims (11)

In the liquid crystal display device of the two-dot inversion driving method in which the polarity of the data signal is inverted in the unit of dots in the horizontal direction and inverted by 2 dots in the vertical direction, A liquid crystal panel including a plurality of liquid crystal cells provided at intersections of gate lines and data lines; A gate driver for driving the gate lines; A data driver for driving the data lines in the two-dot inversion driving method and sequentially supplying a charge sharing voltage and a data signal to the data lines every one horizontal period such that the charging conditions of the data signals are the same for each gate line. Wow; And a timing controller for controlling the gate driver and the data driver. The method of claim 1, The data driver Just before the gate high voltage is supplied to the gate lines, the charge distribution voltage is supplied to the data lines to be charged in advance, and then the corresponding data signals are supplied to the data lines. LCD display device. The method of claim 1, The data driver uses the charge sharing voltage. In response to a polarity control signal from the timing controller, a first charge distribution voltage having a voltage greater than a common voltage supplied to a common electrode serving as a reference electrode of the liquid crystal cells, and a second charge distribution voltage smaller than the common voltage are selectively selected. And a 2-dot inversion driving method. The method of claim 1, The data driver A shift register array for supplying a sequential sampling signal; A latch array for latching and outputting video data in response to the sampling signal; A digital-to-analog converter array for converting video data from the latch array into an analog signal such that the polarity of the data signal is inverted in units of dots in the horizontal direction and the polarity of the data signal is inverted every two horizontal periods; A charge distribution voltage generation unit generating the charge distribution voltage; And a multiplexer array configured to supply the charge distribution voltage and the data signal to the data lines step by step in the horizontal period. The method of claim 4, wherein The data driver And a buffer array positioned at an input terminal or an output terminal of the multiplexer array to buffer and output an input data signal. The method of claim 5, wherein When the polarity control signal indicates a positive polarity in response to the polarity control signal from the timing controller, the charge distribution voltage generator generates a first charge distribution voltage that is greater than a common voltage supplied to a common electrode serving as a reference electrode of the liquid crystal cells. And supplying a second charge-sharing voltage smaller than the common voltage when the polarity control signal indicates negative polarity. 2. The method of claim 6, The charge sharing voltage generator And dividing an input power supply voltage using voltage divider resistors connected in series to generate the first and second charge distribution voltages. In the liquid crystal panel including a plurality of liquid crystal cells provided at the intersections of the gate lines and the data lines, two dots in which the polarity of the data signal is inverted in the horizontal direction by dots and in the vertical direction by two dots. In a driving method of a version driving method liquid crystal display device, And sequentially supplying the charge share voltage and the data signal to the data line every horizontal period such that the data signal is equally charged for each of the gate lines. Way. The method of claim 8, The step of supplying the data signal step by step 2, characterized in that the charge distribution voltage is supplied to the data lines just before the gate high voltage is supplied to the gate lines of the scan lines so as to be charged in advance, and then the corresponding data signals are supplied to the data lines. A dot inversion driving method of driving a liquid crystal display device. The method of claim 8, As the charge distribution voltage When the polarity control signal indicates positive polarity in response to an input polarity control signal, a first charge distribution voltage greater than the common voltage supplied to the liquid crystal panel is supplied, and when the polarity control signal indicates negative polarity, the common A method for driving a 2-dot inversion driving method liquid crystal display device, characterized in that a second charge sharing voltage smaller than the voltage is supplied. The method of claim 8, The step of supplying the data signal step by step Generating a sequential sampling signal; Latching and outputting video data in response to the sampling signal; Converting the output video data into an analog signal such that the polarity of the data signal is inverted in the unit of dots in the horizontal direction and the polarity of the data signal is inverted every two horizontal periods; Generating the charge distribution voltage; And supplying the charge distribution voltage and the data signal to the data lines step by step in the horizontal period.