KR20080040898A - Liquid crystal display and driving method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to equalize the charge quantity of liquid crystal cells by shortening a charge time for charging odd-numbered data voltages in the liquid crystal cells. An LCD(Liquid Crystal Display) device includes a liquid crystal panel(140), a gate driver(130) and a data driver(120), and a control signal generator. The liquid crystal panel includes data and gate lines and plural liquid crystal cells in matrix. The gate driver supplies scan pulses to the gate lines in response to a gate control signal including a gate shift clock. The data driver supplies data voltages which are periodically inversed, to the data lines in response to a data control signal. The control signal generator generates the gate and data control signals, controls the period of the gate shift clock as a first period when the data voltages are inversed, and controls the period of the gate shift clock as a second period shorter than the first period when the data voltages are maintained as the same polarity.

Description

Liquid Crystal Display and Driving Method

1 is a view schematically showing the data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme. FIG.

3 is a block diagram schematically illustrating a liquid crystal display device driven in a two dot inversion method.

FIG. 4 is an enlarged view of a 4x4 liquid crystal cell matrix vertically arranged side by side in the liquid crystal panel of FIG.

FIG. 5 is a waveform diagram illustrating data of a 2-dot inversion method filled in a liquid crystal cell matrix as shown in FIG. 4.

6 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

7 is a waveform diagram of a gate shift clock according to an embodiment of the present invention.

8 is a block diagram of a gate shift clock generation circuit according to an embodiment of the present invention.

9 is a waveform diagram of a signal output from each part of FIG. 8;

10 is a schematic configuration diagram of a gate driving circuit.

11 is a waveform diagram of scan pulses output in accordance with a gate shift clock;

12 is a schematic configuration diagram of a data driving circuit.

Fig. 13 is a waveform diagram for explaining that the charge amount of a liquid crystal cell charged with an odd data voltage and a liquid crystal cell charged with an even data voltage becomes uniform.

<Description of Symbols for Main Parts of Drawings>

110: timing controller 120: data driving circuit

130: gate driving circuit 140: liquid crystal panel

150: GSC generating circuit 151: counter

152,153,155,156: first to fourth control signal generators

154,157: first and second logical operator

158: OR operation R1_V, R2_V: first and second rising decision value

F1_V, F2_V: first and second polling decision values

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for improving display quality of an inversion type liquid crystal display device.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

The LCD is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method for inverting polarities of data between adjacent liquid crystal cells in a vertical line direction, a column inversion method for inverting polarities of data between adjacent liquid crystal cells in a horizontal line direction, a vertical line direction and a horizontal line direction. There is a dot inversion method of inverting the polarity of data between adjacent liquid crystal cells. Of these inversion methods, the dot inversion method is mainly selected because flicker hardly appears in the vertical and horizontal directions.

In the dot inversion scheme, as illustrated in FIG. 1, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, and polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame (Fn-1, Fn). The dot inversion method is most widely used in liquid crystal display devices because flicker is minimized in both the vertical and horizontal directions.

In the dot inversion method of FIG. 2, the polarity of data is inverted in units of two dots in a horizontal or vertical direction. The two-dot inversion method as shown in FIG. 2 has the advantage of lower power consumption than the one-dot inversion method as shown in FIG.

3 schematically shows a conventional liquid crystal display device driven in a two dot inversion method.

Referring to FIG. 3, a conventional liquid crystal display device includes a liquid crystal panel 34 in which data lines D1 to Dm and gate lines G1 to Gn cross each other, and TFTs for driving the liquid crystal cell Clc are formed at the intersections thereof. ), A data driving circuit 32 for supplying data to the data lines D1 to Dm of the liquid crystal panel 34, and a scan pulse for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 34. And a timing controller 31 for controlling the gate driving circuit 33 and the data driving circuit 32 and the gate driving circuit 33.

The data driving circuit 32 stores a shift register for sampling a clock, a register for temporarily storing data, a line for storing data in response to a clock signal from the shift register, and simultaneously outputs the stored one line of data. Latch, a digital / analog converter for selecting a positive / negative gamma voltage corresponding to the digital data value from the latch, and a data line to which analog data converted by the positive / negative gamma voltage is supplied (D1 to Dm) ), And a multiplexer for selecting) and an output buffer connected between the multiplexer and the data line. The data driving circuit 32 inverts the polarity of the data voltages supplied to the data lines D1 to Dm in units of two horizontal periods according to a two dot inversion scheme, and converts the data voltages into a source output enable signal. Enable: Supply the data lines D1 to Dm of the liquid crystal panel 34 according to SOE.

The gate driving circuit 33 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. The gate driving circuit 33 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 31.

The timing controller 31 controls the gate control signal GDC and the data driving circuit 32 for controlling the gate driving circuit 33 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity signal POL, and the like. Here, the source output signal SOE is a signal indicating the output time of the data. The gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, a gate start pulse GSP, and the like. Here, the gate output signal GOE is a control signal indicating an output time point of the gate driving circuit 33.

FIG. 4 is an enlarged view of a 4x4 liquid crystal cell matrix vertically arranged side by side in the liquid crystal panel, and FIG. 5 shows a data voltage of a 2-dot inversion type supplied to four liquid crystal cells shown in FIG. .

4 and 5, the liquid crystal display of the two dot inversion method inverts the polarity of the data voltage every two horizontal line periods. Therefore, the positive polarity voltage higher than the common voltage Vcom is applied to the liquid crystal cell A of the first horizontal line HL1 and the liquid crystal cell B of the second horizontal line HL2 connected to the first data line DL1. On the other hand, the liquid crystal cell C of the third horizontal line HL3 connected to the first data line DL1 and the liquid crystal cell D of the fourth horizontal line HL4 are connected to the common voltage Vcom. Low negative voltage is applied.

However, in such a two-dot inversion system, a liquid crystal cell to which a positive voltage (or negative voltage) rising from the negative voltage (or positive voltage) is applied, and a positive voltage changing from the positive voltage (or negative voltage) The amount of charge of data charged in the liquid crystal cell is different between the liquid crystal cells to which the negative voltage is applied. This is because the rising time (or falling time) of the positive voltage (or negative voltage) rising from the negative voltage (or positive voltage) is long, while the positive voltage varies from the positive voltage. This is because the rising time (or polling time) of R is relatively short. Due to such a difference in charging characteristics, the second and fourth horizontal lines HL2 and HL4 may have the same gray level data voltage as compared to the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. The liquid crystal cells B and D of FIG. 2 appear brighter, and as a result, a luminance difference is generated between neighboring horizontal lines.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven in an inversion method.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention comprises a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are arranged in a matrix form; A gate driving circuit configured to supply scan pulses to the gate lines in response to a gate control signal including a gate shift clock; A data driving circuit for supplying data voltages whose polarities are periodically inverted to the data lines in response to a data control signal; And generating the gate control signal and the data control signal and controlling the period of the gate shift clock to a first period when the polarity of the data voltage is inverted and the period of the gate shift clock when the data voltage is maintained at the same polarity. A control signal generation circuit for controlling a to a second period shorter than the first period.

The control signal generation circuit includes a gate shift clock generation circuit for controlling the period of the gate shift clock.

The gate shift clock generation circuit may include: a counter for counting a reference clock based on any one of the falling edges of a data enable signal indicating the output of the data voltages; A first control signal generator for generating a first control signal that is synchronized in synchronization with a point in time at which a counting value supplied from the counter becomes equal to a predetermined first rising determination value; A second control for generating a second control signal that is polled in synchronization with a time point when a counting value supplied from the counter becomes equal to a first polling determination value set to a value larger than the first rising determination value by a predetermined magnitude; Signal generator; A third control signal generator for generating a third control signal that is synchronized in synchronism with the time when the counting value supplied from the counter becomes equal to a predetermined second rising determination value; A fourth control for generating a fourth control signal that is polled in synchronization with a time point when the counting value supplied from the counter becomes equal to a second polling determination value set to a value larger than the second rising determination value by a predetermined magnitude; Signal generator; A first AND product for ANDing the first and third control signals, and a second AND product for ANDing the second and fourth control signals; And an OR operation for generating the gate shift clock by performing an OR operation on the output signal of the first AND operator and the output signal of the second AND operator.

The second rising determination value is set to a value larger than the first polling determination value, and is set such that the third control signal rises in less than one horizontal period from the rising time of the first control signal.

In synchronization with a new reference point generated two horizontal periods after the reference point, the first and third control signals are polled and the second and fourth control signals are raised.

The gate driving circuit outputs an odd scan pulse having a first pulse width in response to the gate shift clock of the first period, and a second narrower than the first pulse width in response to the gate shift clock of the second period. An even scan pulse having a pulse width is output.

The data voltages are inverted in polarity in units of two horizontal periods.

The data driving circuit sequentially outputs a first data voltage, a second data voltage having the same polarity as the first data voltage, and third and fourth data voltages having the same polarity as the first and second data voltages.

The liquid crystal panel includes a plurality of thin film transistors for supplying data voltages from the data lines to the liquid crystal cells in response to the scan pulse.

The odd scan pulse supplies the first data voltage to the first liquid crystal cell and the third data voltage to the third liquid crystal cell disposed below the first liquid crystal cell.

The even scan pulse may be configured to supply the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and to provide the fourth data voltage below the third liquid crystal cell. 4 Supply to the liquid crystal cell.

According to an exemplary embodiment of the present invention, a plurality of data lines and a plurality of gate lines intersect, a plurality of liquid crystal cells are arranged in a matrix form, and a gate driving circuit for supplying scan pulses to the gate lines and data to the data lines. A driving method of a liquid crystal display device having a data driving circuit for supplying voltages includes: generating a gate control signal for controlling the gate driving circuit including a gate shift clock and a data control signal for controlling the data driving circuit; And controlling the period of the gate shift clock to a first period when the polarity of the data voltage is inverted and controlling the period of the gate shift clock to a second period shorter than the first period when the data voltage is maintained at the same polarity. step; And supplying a scan pulse to the gate lines in response to the gate control signal and supplying data voltages whose polarities are periodically inverted to the data lines in response to the data control signal.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 13.

6 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 7 is a waveform diagram of a gate shift clock according to an exemplary embodiment of the present invention.

Referring to FIG. 6, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn intersect, and a plurality of liquid crystal cells Clc are matrixes. A liquid crystal panel 140 disposed in a form and a gate shift alternately generating a gate shift clock GSC having a first period and a gate shift clock GSC having a shorter second period in units of two horizontal periods 2H. A gate driving circuit 130 for supplying a scan signal to the gate lines G1 to Gn in response to the clock generation circuit 150, the gate control signal GDC including the gate shift clock GSC, and a data control signal. In response to the DDC, the data driving circuit 120 supplies data voltages whose polarities are inverted every two horizontal periods to the data lines D1 to Dm, and the input digital data RGB is rearranged. Gate to the gate and supply The timing controller 110 generates a gate control signal GDC for controlling the driving circuit 130 and a data control signal DDC for controlling the data driving circuit 120.

The liquid crystal panel 140 is substantially the same as that shown in FIG. 3. Reference numeral 'Cst' denotes a storage capacitor. The storage capacitor Cst may be formed between the liquid crystal cell Clc connected to the k-th gate line (where k is a positive integer between 1 and n) and the k-1 th front gate line, and the k th It may be formed between the liquid crystal cell Clc connected to the gate line and a separate common line.

As illustrated in FIG. 7, the gate shift clock generation circuit 150 has a gate shift clock GSC of the first period T1 and a gate of the second period T2 shorter than the second horizontal period 2H. The shift clock GSC is generated alternately. The gate shift clock generation circuit 150 may be embedded in the timing controller 110. The gate shift clock generation circuit 150 will be described in detail with reference to FIGS. 8 and 9.

The gate driving circuit 130 includes a scan pulse having a first pulse width W1 and a first pulse in response to the gate control signal GDC (GSC) including the gate shift clock GSC from the timing controller 110. The scan pulse having the second pulse width W2 smaller than the width is alternately supplied to the gate lines G1 to Gn. That is, the gate driving circuit 130 generates a scan pulse having the first pulse width W1 in response to the gate shift clock GSC of the first period T1 and supplies the scan pulse to the odd-numbered gate lines. The gate driving circuit 130 generates a scan pulse having the second pulse width W1 in response to the gate shift clock GSC of the second period T2 and supplies it to the even-numbered gate lines. The gate driving circuit 130 will be described in detail with reference to FIGS. 10 and 11.

The data driving circuit 120 responds to the digital data RGB input from the timing controller 110 in response to the control signal DDC input from the timing controller 110. ) Will be supplied. That is, the data driving circuit 120 generates data having the same polarity for two horizontal periods 2H according to the polarity control signal POL included in the control signal DDC from the timing controller 110 and then sets the polarity of the data. Inverts and inverts the polarities of horizontally neighboring data. The data driving circuit 120 will be described in detail with reference to FIG. 12.

The timing controller 110 may include a gate control signal GDC for controlling the gate driving circuit 130 by using the data enable signal DE, the vertical / horizontal synchronization signals Vsync and Hsync, and the clock CLK. A data control signal DDC for controlling the data driving circuit 120 is generated. As shown in FIG. 10, the gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like. As shown in FIG. 12, the data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like.

Here, the gate shift clock GSC is a signal generated by the gate shift clock generation circuit 150 in the timing controller 110. When the polarity of the data voltage supplied to the vertically adjacent liquid crystal cells changes in two horizontal periods 2H, the timing controller 110 may include a gate shift clock GSC having a first period and a first period shorter than the first period. By alternately supplying the gate shift clock GSC having two cycles to the gate driving circuit 130, the time required for the even data voltage to be charged in the liquid crystal cell is reduced, thereby being charged to the liquid crystal cell and the even data voltage charged to the odd data voltage. The filling amount of the liquid crystal cell is made uniform.

8 is a configuration diagram of a gate shift clock generation circuit according to an exemplary embodiment of the present invention, and FIG. 9 is a waveform diagram of signals output from respective parts of FIG. 8.

8 and 9, the gate shift clock generation circuit 150 according to an embodiment of the present invention may include a counter 151, first to fourth control signal generators 152, 153, 155, 156, and first and second logic. And multiplication operators 154 and 157.

The counter 151 counts the reference clock CLK based on the falling edge of the data enable signal DE and supplies the counted value to the first to fourth control signal generators 152, 153, 155, and 156 in real time. Here, the reference clock CLK swings between 0 V and 3.3 V and has a frequency of several tens of MHz. In the data enable signal DE, a falling edge is generated at approximately one horizontal period 1H, and a falling edge generated every two horizontal periods 2H is used as a reference point for counting.

The first control signal generator 152 compares the counting value from the counter 151 with the predetermined first rising determination value R1_V, and at a point when the counting value becomes equal to the first rising determination value R1_V. The first rising signal SR1 is synchronized with each other to generate the first rising signal SR1 (see SR1 of FIG. 9). For this purpose, the first control signal generator 152 sets its output terminal (not shown) to the high potential voltage source VCC and the ground. A switch element (not shown) for selectively connecting to the voltage source GND, and its output terminal connected to the base voltage source GND in synchronization with the point of time when the counting value becomes equal to the first rising determination value R1_V. Is connected to a high potential voltage source (VCC). The first control signal generator 152 connects its output terminal connected to the high potential voltage source VCC to the base voltage source GND in synchronization with the new reference point generated two horizontal periods 2H later from the reference point. .

The second control signal generator 153 compares the counting value from the counter 151 with the predetermined first polling determination value F1_V, and the point of time when the counting value becomes equal to the first polling determination value F1_V. Generates a first polling signal SF1 that is polled in synchronization with (see SF1 of FIG. 9). Here, the first polling determination value F1_V is larger than the first rising determination value R1_V by a predetermined magnitude. Is set. In order to generate the first polling signal SF1, the second control signal generator 153 selectively switches its output terminal (not shown) to the high potential voltage source VCC and the ground voltage source GND. (Not shown), and its output terminal connected to the high potential voltage source VCC is connected to the base voltage source GND in synchronization with the point of time when the counting value becomes equal to the first polling determination value F1_V. The second control signal generator 153 connects the output terminal connected to the base voltage source GND to the high potential voltage source VCC in synchronization with the new reference point generated two horizontal periods 2H later from the reference point.

The first AND product 154 performs an AND operation on the first rising signal SR1 from the first control signal generator 152 and the first falling signal SF1 from the second control signal generator 153. As shown in FIG. 9, a synthesized signal SR1 x SF1 having a period of two horizontal periods 2H is generated.

The third control signal generator 155 compares the counting value from the counter 151 with the predetermined second rising determination value R2_V, and at a point when the counting value becomes equal to the second rising determination value R2_V. A second rising signal SR2 that is synchronously generated is generated (see SR2 of FIG. 9). Here, the second rising decision value R2_V is set to a value larger than the first polling decision value F1_V, but the second rising signal SR2 is generated. The rising signal SR2 is set to rise within a time less than one horizontal period from the rising time of the first rising signal SR1. In order to generate the second rising signal SR2, the third control signal generator 155 selectively switches its output terminal (not shown) to the high potential voltage source VCC and the ground voltage source GND. (Not shown), and its output terminal connected to the ground voltage source GND is connected to the high potential voltage source VCC in synchronization with the point of time when the counting value becomes equal to the second rising determination value R2_V. The third control signal generator 155 connects its output terminal connected to the high potential voltage source VCC to the base voltage source GND in synchronization with the new reference point generated two horizontal periods 2H from the reference point. .

The fourth control signal generator 156 compares the counting value from the counter 151 with the predetermined second polling determination value F2_V, and at a time point when the counting value becomes equal to the second polling determination value F2_V. A second polling signal SF2 that is synchronously polled is generated (see SF2 of FIG. 9). Here, the second polling determination value F2_V is set to a value larger than the second rising determination value R2_V by a predetermined magnitude. do. In order to generate the second polling signal SF2, the fourth control signal generator 156 may selectively switch its output terminal (not shown) to the high potential voltage source VCC and the ground voltage source GND. (Not shown), and its output terminal connected to the high potential voltage source VCC is connected to the base voltage source GND in synchronization with the point of time when the counting value becomes equal to the second polling determination value F2_V. The fourth control signal generator 156 then connects the output terminal connected to the base voltage source GND to the high potential voltage source VCC in synchronization with the new reference point generated two horizontal periods 2H later from the reference point.

The second AND product 157 logically ANDs the second rising signal SR2 from the third control signal generator 155 and the second falling signal SF2 from the fourth control signal generator 156. 9 to generate a combined signal SR2 x SF2 having a period of two horizontal periods 2H as shown in FIG.

The AND operator 158 performs an OR operation on the combined signal SR1 × SF1 from the first AND product 154 and the combined signal SR2 × SF2 from the second AND product 157 to perform two horizontal periods (2H). ) Alternately generates the gate shift clock GSC of the first period T1 and the gate shift clock GSC of the second period T2 shorter than this.

As such, the gate shift clock generation circuit 150 may include the gate shift clock GSC having the first period T1 and the gate shift clock GSC having the second period T2 shorter than the first period T1. By alternately supplying to the gate driving circuit 130, the time required for the even data voltage to be charged in the liquid crystal cell is reduced to make the charging amount of the liquid crystal cell charged to the odd data voltage and the liquid crystal cell charged to the even data voltage uniform.

Meanwhile, the first and second rising decision values R1_V and R2_V and the first and second polling decision values F1_V and F2_V are nonvolatile memories capable of erasing and updating data, for example, EEPROM (Electrically Erasable Programmable Read). Only Memory) and / or Extended Display Identification Data ROM (EDID ROM). Therefore, when the amount of charge between the liquid crystal cells of the even-numbered horizontal line and the liquid crystal cells of the even-numbered horizontal line is greater than the same gray scale according to the charging characteristics or the position of the liquid crystal cell, the user determines the second rising decision value. The second period of the gate shift clock GSC may be shortened by reducing R2_V and the second polling determination value F2_V. As will be described with reference to FIGS. 10 and 11, the shorter the second period of the gate shift clock GSC, the shorter the time that the good data voltage is charged in the liquid crystal cell.

10 is a schematic configuration diagram of the gate driving circuit 130, and FIG. 11 is a waveform diagram of scan pulses output according to the gate shift clock GSC.

10 and 11, the gate driving circuit 130 has a plurality of stages 132-1 to 132-n and outputs scan pulses according to the gate shift clock GSC and the gate output signal GOE. A shift register 132 for adjusting and a level shifter 134-1 to 134-n for converting the swing width of each output signal of the shift register 132 into a swing width suitable for driving the liquid crystal cell Clc. .

The first stage 132-1 of the shift register 132 generates a scan pulse in response to the gate start pulse GSP and the gate shift clock GSC from the timing controller 110. The second to nth stages 132-2 to 132-n receive a voltage on the front gate lines G1 to Gn-1 as a gate start pulse GSP and respond to the signal and the gate shift clock GSC. Scan pulses are generated sequentially. In particular, in the case of a gate driving circuit such as Silicon Works, Inc., model number SW8010_K, the width of the scan pulse output from the shift register 132 is mainly in the period of the gate shift clock GSC as shown in FIG. 11. Adjusted accordingly. For example, the scan pulse when the gate shift clock GSC of the second period T2 is input to the shift register 132 than when the gate shift clock GSC of the first period T1 is input to the shift register 132. The width of is relatively narrower (W1> W2).

The level shifters 134-1 to 134-n are connected to output terminals of the shift register 132, respectively, to convert swing widths of the output signals of the shift registers 132 into swing widths suitable for driving the liquid crystal cell Clc. do. The scan pulses SP1 to SPn output from the level shifters 134-1 to 134-n have two voltage levels, a gate high voltage Vgh and a gate low voltage Vgl. A buffer may be provided between the level shifters 134-1 through 134-n and the gate lines G1 through Gn.

FIG. 12 is a schematic configuration diagram of the data driving circuit 120, and FIG. 13 is a waveform diagram for explaining that the charging amount of the liquid crystal cell charged with the odd data voltage and the liquid crystal cell charged with the even data voltage becomes uniform.

Referring to FIG. 12, the data driving circuit 120 includes a plurality of integrated circuits (ICs), each integrated circuit including a shift register 122 and a first latch (sub) which are cascaded between an input line and a data line. 121, a second latch 123, a digital-to-analog converter (hereinafter referred to as a “DAC”) 124, and a buffer 125.

The shift register 122 shifts the source start pulse SSP from the timing controller 110 according to the source shift clock SSC to generate a sampling signal. In addition, the shift register 122 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 122.

The first latch 121 samples and stores the digital data RGB according to the sampling signal input from the shift register 122, and supplies the stored digital data to the second latch 123.

The second latch 123 latches the data EFD and RGB input from the first latch 121 and then, in response to the source output signal SOE from the timing controller 110, a second latch in another integrated circuit. The digital data of one horizontal line latched together with 123 is simultaneously output. At this time, the source output signal SOE is generated approximately every one horizontal period, and each pulse width is constant.

The DAC 124 converts the digital data RGB from the second latch 123 to the positive analog data voltage VPG or the negative analog data voltage VNG according to the polarity signal POL from the timing controller 110. Convert to In addition, the voltage generated from the DAC 124 is controlled in polarity of the data voltage according to the 2-dot inversion scheme in response to the polar line signal POL.

The buffer 125 outputs the analog data voltages VPG and VNG input from the DAC 124 to the data lines D1 to Dm without signal attenuation.

In FIG. 12, reference numeral R denotes a line resistance between the output terminal of the data driving circuit 120 and the data lines D1 to Dm.

As illustrated in FIG. 13, the data driving circuit 120 alternately generates the positive analog data voltage VPG and the negative analog data voltage VNG every two horizontal periods 2H. D1 to Dm). In order to charge the data voltages VPG and VNG to the pixel electrode of the liquid crystal cell, gate lines G1 to Gn are provided with the first pulse width W1 from the gate driving circuit 130 as shown in FIG. 13. The scan pulse SP having a scan pulse SP and the second pulse width smaller than the first pulse width are supplied. The scan pulse SP having the first pulse width W1 is supplied to the even horizontal line, and the scan pulse SP having the second pulse width is supplied to the even horizontal line, whereby the even data voltage is supplied to the liquid crystal cell. The charging time is reduced compared to the time when the odd data voltage is charged in the liquid crystal cell. For example, as shown in FIG. 13, compared to the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3, the liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4. ), The charging time of the data voltage charged in the circuit becomes shorter. Accordingly, the time required for the even data voltage to be charged in the liquid crystal cell is reduced, so that the charging amount of the liquid crystal cell charged with the odd data voltage and the liquid crystal cell charged with the even data voltage becomes uniform.

As a result, the present invention can uniformize the charging characteristic irregularity between the liquid crystal cell of the odd-numbered horizontal line and the liquid crystal cell of the even-numbered horizontal line by the period modulation of the gate shift clock GSC in the two-dot inversion method.

As described above, the liquid crystal display and the driving method thereof according to the present invention control the period of the gate shift clock to the first period when the polarity of the data voltage is inverted, and the period of the gate shift clock when the data voltage is maintained at the same polarity. By controlling a to a second period shorter than the first period, it is possible to reduce the time for the even data voltage to be charged in the liquid crystal cell, thereby making it possible to uniformize the amount of charge of the liquid crystal cell charged to the odd data voltage and the liquid crystal cell charged to the even data voltage. As a result, the liquid crystal display device and the driving method thereof according to the present invention can prevent the occurrence of a luminance difference between neighboring horizontal lines, thereby significantly improving the display quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, although the embodiment of the present invention has been described based on the two dot inversion method, N (where N is a positive integer of 2 or more) may also be applied to the dot inversion method. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are arranged in a matrix form; A gate driving circuit configured to supply scan pulses to the gate lines in response to a gate control signal including a gate shift clock; A data driving circuit for supplying data voltages whose polarities are periodically inverted to the data lines in response to a data control signal; And The period of the gate shift clock is controlled as a first period when the gate control signal and the data control signal are generated and the polarity of the data voltage is inverted. The period of the gate shift clock is controlled when the data voltage is maintained at the same polarity. And a control signal generation circuit for controlling at a second period shorter than the first period. The method of claim 1, The control signal generation circuit, And a gate shift clock generation circuit for controlling a period of the gate shift clock. The method of claim 2, The gate shift clock generation circuit, A counter for counting a reference clock based on any one of the falling edges of the data enable signal indicating the output of the data voltages; A first control signal generator for generating a first control signal that is synchronized in synchronization with a point in time at which a counting value supplied from the counter becomes equal to a predetermined first rising determination value; A second control for generating a second control signal that is polled in synchronization with a time point when a counting value supplied from the counter becomes equal to a first polling determination value set to a value larger than the first rising determination value by a predetermined magnitude; Signal generator; A third control signal generator for generating a third control signal that is synchronized in synchronism with a time point at which a counting value supplied from the counter becomes equal to a predetermined second rising determination value; A fourth control for generating a fourth control signal that is polled in synchronization with a time point when the counting value supplied from the counter becomes equal to a second polling determination value set to a value larger than the second rising determination value by a predetermined magnitude; Signal generator; A first AND product for ANDing the first and third control signals, and a second AND product for ANDing the second and fourth control signals; And And an OR operation for generating the gate shift clock by performing an OR operation on the output signal of the first AND operator and the output signal of the second AND operator. The method of claim 3, wherein The second rising determination value is, And a value greater than the first polling determination value and set so that the third control signal rises within a time period less than one horizontal period from the rising time of the first control signal. The method of claim 4, wherein And in synchronization with a new reference point generated two horizontal periods after the reference point, the first and third control signals are polled and the second and fourth control signals are risen. The method of claim 5, wherein The gate driving circuit, An even scan having an odd scan pulse having a first pulse width in response to the gate shift clock of the first period, and having a second pulse width narrower than the first pulse width in response to the gate shift clock of the second period A liquid crystal display device which outputs a pulse. The method of claim 6, And the data voltages are inverted in polarity in units of two horizontal periods. The method of claim 7, wherein The data driving circuit, And a first data voltage, a second data voltage having the same polarity as the first data voltage, and third and fourth data voltages having the same polarity as the first and second data voltages. . The method of claim 8, The liquid crystal panel, And a plurality of thin film transistors for supplying data voltages from the data lines to the liquid crystal cells in response to the scan pulse. The method of claim 9, The radix scan pulse, And supplying the first data voltage to the first liquid crystal cell and the third data voltage to the third liquid crystal cell disposed under the first liquid crystal cell. The method of claim 10, The excellent scan pulse, Supplying the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and supplying the fourth data voltage to a fourth liquid crystal cell disposed under the third liquid crystal cell. Liquid crystal display device characterized in that. A plurality of data lines and a plurality of gate lines intersect, a plurality of liquid crystal cells are arranged in a matrix form, a gate driving circuit supplying scan pulses to the gate lines, and a data driving circuit supplying data voltages to the data lines. In the method of driving a liquid crystal display device having: A gate control signal for controlling the gate driving circuit and a data control signal for controlling the data driving circuit, including a gate shift clock, and generating a gate control signal when the polarity of the data voltage is reversed. Controlling the period of the gate shift clock to a second period shorter than the first period when the control is performed at a first period and the data voltage is maintained at the same polarity; And Supplying a scan pulse to the gate lines in response to the gate control signal and supplying data voltages whose polarities are periodically inverted to the data lines in response to the data control signal. Method of driving the device. The method of claim 12, The scan pulse, An odd scan pulse having a first pulse width in response to the gate shift clock of the first period; And And an even scan pulse having a second pulse width narrower than the first pulse width in response to the gate shift clock of the second period. The method of claim 13, And the data voltages are inverted in polarity in units of two horizontal periods. The method of claim 14, The data voltages, And a first data voltage sequentially output, a second data voltage having the same polarity as the first data voltage, and third and fourth data voltages having the same polarity as the first and second data voltages. Driving method of liquid crystal display device. The method of claim 15, The radix scan pulse, And supplying the first data voltage to the first liquid crystal cell and supplying the third data voltage to the third liquid crystal cell disposed under the first liquid crystal cell. The method of claim 16, The excellent scan pulse, The second data voltage is supplied to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell, and the fourth data voltage is supplied to a fourth liquid crystal cell disposed below the third liquid crystal cell. Method of driving a liquid crystal display device characterized in that.

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