KR20070010524A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display device and a driving method thereof are provided to reduce a driving time for an impulse image by displaying the impulse image on plural pixel rows at the same time. A liquid crystal display device includes plural gate lines(G1~Gn), plural data lines(D1~Dm), plural pixels, a gate driver(400), and a data driver(500). The gate lines deliver a gate-on voltage and include first and second bundles of gate lines. The data lines deliver a data voltage including a regular image data voltage and an impulsive data voltage. The pixels are connected to the gate and data lines. The gate driver is connected to the gate lines and applies the gate-on voltage. The data driver is connected to the data lines and applies a data voltage. The polarity of the data voltage is inverted per every predetermined numbers of horizontal periods. When the polarity of the data voltage is inverted, the regular image data voltage is applied on the next first horizontal period, and the gate-on voltage is applied on the first and second bundles of the gate lines.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a timing diagram illustrating driving signals of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a schematic diagram showing an image displayed in accordance with the drive signal shown in FIG. 3 for one frame.

The present invention relates to a liquid crystal display and a driving method thereof.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

However, if the polarity of the data voltage is inverted every pixel row, one horizontal period is relatively short in high resolution, and thus the data voltage is not sufficiently charged in the data line. Therefore, in order to increase the charge rate of the data line, an N row inversion scheme has been proposed in which the polarity of the data voltage is inverted every N pixel rows. However, in the N row inversion method, horizontal lines may be displayed for every (N + 1) th pixel row in which the polarity of the data voltage is inverted.

On the other hand, since the liquid crystal display is a hold type display device, blurring occurs when an edge of an object is not clear and blurs when a moving image is displayed. In order to eliminate blurring, an impulsive driving method has been developed in which a desired normal image is displayed while a black image is displayed in the middle thereof. However, since additional driving time is required to display the black image, there is no driving margin in the case of high resolution and high speed driving.

Accordingly, an object of the present invention is to provide a liquid crystal display and a method of driving the same, which can be prevented from blurring without a horizontal line and have a relatively high driving margin while using the N inversion and impulsive driving methods.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of gate lines, a regular image data voltage, and impulsive data that transmit gate-on voltages and include first and second bundle gate lines. A plurality of data lines transferring a data voltage including a voltage, a plurality of pixels connected to the gate line and the data line, a gate driver connected to the gate line to apply the gate-on voltage, and to the data line. And a data driver connected to apply the data voltage, wherein the polarity of the data voltage is inverted every predetermined horizontal period, and the impulsive data voltage is set in the first horizontal period after the polarity of the data voltage is inverted. Applied to a data line and the gate-on voltage is applied to the gate lines of the first and second bundles. do.

The gate-on voltage may be sequentially applied to the gate lines of the first bundle, and the impulsive data voltage and the normal image data voltage may be sequentially applied to the pixels connected to the gate lines of the first bundle.

The gate-on voltage applied to the gate lines of the first bundle may have a pulse width of 1H or more and may overlap the gate lines of the first bundle.

The gate-on voltage may be simultaneously applied to the gate lines of the second bundle, and the impulsive data voltage may be simultaneously applied to the pixels connected to the gate lines of the second bundle.

The impulsive data voltage may be smaller than the normal image data voltage.

The impulsive data voltage may be any one of a voltage of the lowest gray level, a voltage of gray indicating black, and a voltage of gray level giving a predetermined range of luminance.

A signal controller configured to receive N bundles of image information, convert the N bundles into normal image data, generate a bundle of impulsive data, and transmit the normal image data and the impulsive data to the data driver; Can be.

The impulsive data may be smaller than the normal image data.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, including a plurality of gate lines including first and second bundled gate lines, a plurality of data lines crossing the gate lines, and the gate lines and the data lines. A driving method of a liquid crystal display device including a plurality of pixels connected to a device, the method comprising: applying a data voltage including a normal image data voltage and an impulsive data voltage to the data line by changing polarities at predetermined horizontal periods; Sequentially applying a gate-on voltage to the gate lines of the first bundle, and simultaneously applying the gate-on voltage to the gate lines of the second bundle, the first being after the polarity of the data voltage is inverted. The impulsive data voltage is applied to the data line in a horizontal period and the gate-on voltage is applied to the first line. It is applied to the gate lines of the second bundle.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the i-th (i = 1, 2, ..., n) gate line G _i and the j-th (j = 1, 2, ..., m) data line D _The pixel PX connected to _j ) includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor C _LC , and a storage capacitor C _ST connected thereto. Include. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 191 of the lower panel 100 and a common electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 191 and 270. It functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates a gray voltage set (or a reference gray voltage set) related to the transmittance of the pixel PX. (Reference) The gray scale voltage set includes a positive value (positive polarity) and a negative value (negative polarity) with respect to the common voltage Vcom. The gray voltage generator 800 may generate two (reference) gray voltage sets based on different gamma curves.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it. When the gray voltage generator 800 generates two (reference) gray voltage sets, the data driver 500 selects one of the two gray voltage sets from the gray voltage generator 800 and selects the selected gray voltage. One gray voltage belonging to the set is applied to the data lines D ₁ -D _m as data signals.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be provided in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be integrated in the form of a driving circuit. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail with reference to FIGS. 3 and 4.

FIG. 3 is a timing diagram illustrating a drive signal of the liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a schematic diagram showing an image displayed according to the drive signal shown in FIG. 3 for one frame.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input video signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed. ) Is output to the data driver 500. The output image signal DAT has a predetermined number (or gradation) as a digital signal, and includes regular image data generated based on the input image signals R, G, and B, and impulsive data for impulsive driving. do.

The gate control signal CONT1 defines the scan start signal STV indicating the start of scanning, the gate clock signal CPV controlling the output timing of the gate on voltage Von, and the durations of the gate on voltage Von. At least one output enable signal (OE).

The data control signal CONT2 is a load signal LOAD for applying a data signal to the horizontal synchronization start signal STH that indicates the start of image data transmission for one row of pixels PX and the data lines D ₁ -D _m . ) And a data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal relative to the common voltage "). RVS) further.

The signal controller 600 converts the N bundles of input image signals R, G, and B into N bundles of normal image data, and generates one bundle of impulsive data. The time at which the N bundled input video signals R, G, and B are inputted and the time at which the (N + 1) bundled output video signal DAT is sent out are substantially the same (N is a natural number). Therefore, the frequency of the horizontal synchronization start signal STH is (N + 1) / N times the frequency of the horizontal synchronization signal Hsync. In addition, the frequency of the data clock signal HCLK to which the output video signal DAT is synchronized may be (N + 1) / N times the frequency of the main clock MCLK to which the input video signals R, G, and B are synchronized. For example, FIG. 3 shows N as three.

The impulsive data may be generated by correcting the input image signals R, G, and B according to a predetermined rule or by applying a predetermined gray scale value. When N is 2 or more, impulsive data may be obtained by averaging N bundles of input video signals R, G, and B.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives an output image signal DAT of one pixel row and selects a gray scale voltage corresponding to each output image signal DAT. Thus, the output image signal DAT is converted into the analog data voltage Vdat and then applied to the corresponding data lines D ₁ -D _m . The data voltage Vdat includes positive and negative normal image data voltages Vp and Vn to which normal image data is converted, and an impulsive data voltage Vim to which impulsive data is converted.

The gray scale value of the impulsive data is smaller than the gray scale value of the normal image data of the pixel PX, and in some cases, the impulsive data may have any constant gray scale. The constant gradation may be the lowest gradation or may be black or a predetermined level of gradation that produces a range of luminance.

When the gray voltage generator 800 generates two gray voltage sets, different gray voltage sets correspond to the normal image data and the impulsive data, respectively, and the gray voltages for the gray levels may be different from each other. The gamma curve represented by the normal image data is determined according to the characteristics of the liquid crystal display, and the gamma curve represented by the impulsive data shows lower luminance than the gamma curve represented by the normal image data. In some cases, the gamma curve represented by the impulsive data may show black for all gray levels or may indicate any constant luminance.

The gate driver 400 applies the gate-on voltage Von to at least one gate line G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate line G _1- . The switching element Q connected to G _n ) is turned on. Then, the data voltage Vdat applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the data voltage Vdat and the common voltage Vcom applied to the pixel PX is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. This change in polarization is represented by a change in transmittance of light by a polarizer attached to the liquid crystal panel assembly 300.

By repeating this process in units of one horizontal period (also referred to as "1H"), the normal image data voltages Vp and Vn and the impulsive data voltages Vim are applied to all the pixels PX to normalize one frame. The image and the impulsive image are displayed once for one frame.

When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is changed such that the polarity of the data voltage Vdat applied to each pixel PX is opposite to that of the previous frame. Controlled ("frame inversion").

At this time, even within one frame, the polarity of the data voltage Vdat flowing through one data line is changed for every N pixel rows according to the characteristics of the inversion signal RVS (eg, inversion of a row and inversion of a point). In addition, polarities of the data voltages Vdat descending on the neighboring data lines D ₁ -D _m may be different from each other (eg, thermal inversion and point inversion).

The normal image is sequentially displayed one pixel row from the first pixel row, and the impulsive image is sequentially displayed N pixel rows at a time from the i th pixel row. This representation looks like the rotation of an impulsive image band with a width of row i. If necessary, the regular image and the impulsive image may be displayed in the upward direction, starting from the bottom. This will be described in more detail with reference to FIG. 3 as follows.

The inversion signal RVS has a high level and a low level and is alternately applied to the data driver 500 every four horizontal periods. The data driver 500 emits a positive data voltage Vdat when the inversion signal RVS is at a high level, and emits a negative data voltage Vdat when the inversion signal RVS is at a high level. Therefore, the data driver 500 outputs a positive impulsive data voltage Vim for one horizontal period, a positive normal image data voltage Vp for three horizontal periods, and a negative impulsive data voltage for one horizontal period. (Vim), and in turn outputs the negative normal image data voltage (Vn) for three horizontal periods.

The scan start signal STV includes a pulse P1 for regular image data and a pulse for impulsive data (not shown), and is a gate driving circuit (or an integrated circuit chip) connected to the gate line of the first pixel row. Is applied to. The pulse for regular image data P1 has a width of 2H, and the pulse for impulsive data has a width of 4H. The generation timing of the pulse for impulsive data is determined based on the position at which the impulsive image is displayed. After the positive normal image data voltage Vp is applied to the pixels PX of the first to third pixel rows, the impulsive data voltage Vim is the pixels PX of the i th to (i + 2) th pixel rows. If is applied to, the pulse for impulsive data is generated at the time when (ni) / n vertical period has elapsed after the pulse for normal image data P1 is generated (n is vertical resolution). During one frame, pulses P1 for regular image data and pulses for impulsive data are generated one by one.

The carry signal CS generated by the front gate driving circuit also includes a pulse for normal image data (not shown) and a pulse P2 for impulsive data, and a gate driving to which a scan start signal STV is applied. It is applied to each gate drive circuit other than a circuit. Due to the impulsive data pulse of the scan start signal STV, when the pulse for normal image data P1 of the scan start signal STV is applied to the first gate driving circuit, it is connected to the gate line of the i-th pixel row. The impulse data pulse P2 of the carry signal CS is applied to the gate driving circuit.

The plurality of output enable signals OE provided to each gate driving circuit to limit the duration of the gate-on voltage Von outputted by the gate driving circuits include a waveform for regular image data OEN and a waveform for impulsive data. There are two waveforms of (OEI), and the waveforms applied to the respective gate driving circuits are changed at an appropriate time under the control of the signal controller 600. If the output enable signal OE is at a high level, the output of the gate-on voltage Von is cut off so that the gate-off voltage Voff is output, and if the output enable signal OE is low, the gate-on voltage Von is output. The normal image data waveform OEN becomes high level for a short time whenever the polarity is reversed according to the inversion signal RVS. It becomes a low level during the 1H is applied, the period of the two waveforms (OEN, OEI) is equal to 4H. The waveform of the output enable signal OE applied to the gate driving circuit to which the pulse start signal P1 of the scan start signal STV and the carry signal CS is applied is the waveform for normal image data OEN. The waveform of the output enable signal OE applied to the gate driving circuit to which the impulsive data pulse P2 of the scan start signal STV and the carry signal CS is applied is the impulsive data waveform OEI. . Therefore, when the output enable signal OE has the waveform for normal image data OEN, the gate-on voltage Von while the impulsive data voltage Vim and the regular image data voltage Vp / Vn of the same polarity are applied. ) Is output to apply the impulsive data voltage Vim and the normal image data voltage Vp / Vn of the same polarity to the pixel PX. In contrast, when the output enable signal OE has an impulsive data waveform OEI, the gate-on voltage Von is output while the impulsive data voltage Vi is applied to impulse the corresponding pixel PX. Only the data voltage Vi is applied.

The gate clock signal CPV includes a first clock having a width of 1H and a second clock having a width of 2H, and two first clocks and one second clock are alternately repeated. A scan pulse is generated in synchronization with each clock rising edge of the gate clock signal CPV. Therefore, no scan pulse occurs at the start of every fourth horizontal period when the second clock of the gate clock signal CPV falls. The width of the scan pulse is substantially equal to the width of the pulses P1 and P2 of the scan start signal STV and the carry signal CR.

When the pulse P1 of the scan start signal STV is applied to the first gate driving circuit, in each of the first to third horizontal periods, each scan pulse is a gate signal g ₁ , g ₂ , g ₃ , which in turn corresponds to the corresponding gate line. Is approved. The three scan pulses have a width of 2H and are sequentially outputted by 1H.

In the first horizontal period, the positive impulsive data voltage Vi is applied to the pixel PX of the first pixel row. In the second horizontal period, the positive normal image data voltage Vp corresponding to the pixel PX of the first pixel row is applied to the pixel PX of the first pixel row, and at the same time, the data voltage Vp The pixel PX in the first pixel row is charged as a precharge voltage. In the third horizontal period, the positive normal image data voltage Vp corresponding to the pixel PX of the second pixel row is applied to the pixel PX of the second pixel row, and at the same time, the data voltage Vp is three times. The pixel PX in the first pixel row is charged as a precharge voltage. In the fourth horizontal period, the positive normal image data voltage Vp corresponding to the pixel PX of the third pixel row is applied to the pixel PX of the third pixel row. In the fifth to eighth horizontal periods, the polarity of the data voltage Vdat is negatively driven. The polarity of the data voltage Vdat is changed every four horizontal periods, and the normal image data voltages Vp and Vn are applied to all the pixels PX. Here, the impulsive data voltage Viim precharges the data line and the pixel PX of the pixel row with a polarity opposite to that of the previous data voltage Vdat. And these scan pulses may have a width α of less than 1H at the front for precharging.

As described above, by precharging the data voltages having the same polarity for each pixel, the charging rate of the data line and the pixel electrode can be increased, and the horizontal lines seen for each pixel row in which the polarities of the data voltages are reversed can be prevented.

On the other hand, when the pulse P2 of the carry signal CS is applied to the gate driving circuit connected to the gate line of the i-th pixel row, the scan pulses thereof have a width of 4H and overlap each other. However, the output of the gate drive circuit is cut off by the output enable signal (OE) in the second to fourth horizontal periods (indicated by the hatched portion of the scanning pulse), but the gate-on voltage (Von in the fifth horizontal period). ) Is output. Therefore, the gate signals g _i , g _{i + 1} and g _{i + 2} are simultaneously applied to the corresponding gate lines in the fifth horizontal period. Similarly, the gate signals g _{i + 3} , g _{i + 4} and g _{i + 5} are simultaneously applied to the corresponding gate lines in the ninth horizontal period. In this manner, the gate signal is applied to the last gate line, and the gate signal is applied from the first gate line to the (i-1) th gate line. Therefore, the impulsive data voltage Vim is simultaneously applied to each of the three pixel rows from the pixel connected to the i-th gate line, and the impulsive data voltage Vim is sequentially charged to all the pixels PX.

As described above, since the N charging and the driving of the N-throw inversion drive simultaneously perform the pre-charging and the impulsive image display for the regular image at every (N + 1) th horizontal period, the driving frequency is relatively small and there is a driving margin.

Referring to FIG. 4, an impulsive image of a previous frame is displayed from the top of the screen to a quarter point on the initial screen of one frame, and a regular image of the previous frame is displayed below the quarter point. In the driving signal of FIG. 3, i is n / 4, so the vertical width of the impulsive image is 25% of the vertical width of the entire screen. This ratio refers to the impulsive image ratio among the images displayed for one frame in one pixel. When the pulse P1 of the scan start signal STV and the pulse P2 of the carry signal CS are input, the normal image is displayed in order from the top of the screen to the bottom, and the impulsive image from the quarter point from the top down Is displayed. When a quarter frame elapses, a regular image is displayed from the top of the screen to a quarter point, and an impulsive image is displayed from the quarter point to the center of the screen. As such, the impulsive image is displayed while erasing the normal image of the previous frame, and the normal image is displayed while erasing the impulsive image. Impulsive images appear as bands 25% wide and appear to rotate from top to bottom for one frame. In this way, blurring can be prevented by displaying the normal image and the impulsive image.

Although the operation has been described with reference to three pixel rows in FIG. 3, any number of pixel rows may be used as a reference. In addition, i is a variable defining the vertical width of the impulsive video band and may be set as necessary within the range of the vertical resolution.

As described above, according to the present invention, blurring can be prevented by performing impulsive driving, and horizontal lines can be prevented from appearing by applying a predetermined precharge voltage to the pixel row whose polarity is reversed. In addition, by simultaneously displaying an impulsive image on a plurality of pixel rows, a driving time for displaying an impulsive image can be relatively reduced, thereby increasing the charging rate of the pixel voltage.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (12)

A plurality of gate lines transferring a gate-on voltage and including first and second bundle gate lines, A plurality of data lines transferring a data voltage including a normal image data voltage and an impulsive data voltage; A plurality of pixels connected to the gate line and the data line, A gate driver connected to the gate line to apply the gate-on voltage, and A data driver connected to the data line to apply the data voltage Including; The polarity of the data voltage is inverted every predetermined number of horizontal periods, The impulsive data voltage is applied to the data line and the gate-on voltage is applied to the first and second bundled gate lines in a first horizontal period after the polarity of the data voltage is inverted. Liquid crystal display. In claim 1, And the gate-on voltage is sequentially applied to the gate lines of the first bundle, and the impulsive data voltage and the normal image data voltage are sequentially applied to the pixels connected to the gate lines of the first bundle. In claim 2, The gate-on voltage applied to the gate lines of the first bundle has a pulse width of 1H or more and is superimposed on the gate lines of the first bundle. In claim 1, And the gate-on voltage is simultaneously applied to the gate lines of the second bundle so that the impulsive data voltage is simultaneously applied to the pixels connected to the gate lines of the second bundle. In claim 1, The impulsive data voltage is less than the normal image data voltage. In claim 5, The impulsive data voltage is any one of a voltage of the lowest gray scale, a voltage of gray indicating black, and a voltage of gray scale giving a predetermined range of luminance. In claim 1, And a signal controller configured to receive N bundles of image information, convert the N bundles into normal image data, generate a bundle of impulsive data, and transmit the normal image data and the impulsive data to the data driver. Liquid crystal display device (N is a natural number). In claim 7, And the impulsive data is smaller than the normal image data. A drive of a liquid crystal display including a plurality of gate lines including first and second bundled gate lines, a plurality of data lines crossing the gate lines, and a plurality of pixels connected to the gate lines and the data lines. As a method, Applying a data voltage including a normal image data voltage and an impulsive data voltage to the data line by changing polarity every predetermined number of horizontal periods, Sequentially applying a gate-on voltage to the first bundle of gate lines, and Simultaneously applying the gate-on voltage to the second bundle of gate lines Including, The impulsive data voltage is applied to the data line and the gate-on voltage is applied to the first and second bundled gate lines in a first horizontal period after the polarity of the data voltage is inverted. Driving method of liquid crystal display device. In claim 9, The gate-on voltage applied to the gate lines of the first bundle has a pulse width of 1H or more and is superimposed on the gate lines of the first bundle. In claim 10, And wherein the impulsive data voltage is less than the normal image data voltage. In claim 11, And wherein the impulsive data voltage is any one of a voltage of the lowest gray level, a voltage of gray indicating black, and a voltage of gray giving a predetermined range of luminance.

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