KR20100097346A - Driving circuit and driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE: A driving circuit and driving a method for a liquid crystal display device are provided to display a normal image by improving the distortion of a clock signal. CONSTITUTION: A first clock signal controls the generation of a gate drive signal. The gate drive signal writes image data in a liquid crystal panel. A second clock signal controls the generation of a gate drive signal for writing black data. The first clock signal and the second clock signal are outputted for each one frame time. A driver circuit is a timing controller.

Description

Driving circuit and driving method for liquid crystal display device {Driving circuit and driving method for liquid crystal display device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and a driving method for a liquid crystal display device, and more particularly to a driving circuit for a liquid crystal display device in which a distortion of a clock signal provided to a gate driver in a liquid crystal display device performing black data insertion (BDI) driving is improved. And a driving method.

Recently, various driving methods for improving the image quality and viewing characteristics of a display image have been proposed. Among them, black-data insertion (BDI) driving is one of them.

FIG. 1 is a configuration diagram briefly illustrating a configuration of a liquid crystal display for driving black data insertion according to the prior art, and includes a liquid crystal panel 10, a timing controller 20, a source driver 30, and a gate driver 40. ) As a representative.

Referring to FIG. 2, the liquid crystal panel 10 crosses a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn on a substrate using glass to form a plurality of pixel regions. In each pixel area, a thin film transistor TFT and a liquid crystal LC are configured to display an image by input data.

The timing controller 20 is commonly referred to as a timing controller, and is configured of a plurality of source drive integrated circuits by using a control signal and a clock signal CLK input from an external driving system such as a TV or a graphics card. A control signal for driving the gate driver 40 including the source driver 30 and the plurality of gate driver integrated circuits is generated. In addition, the RGB data input from the external drive system is transmitted to the source driver (30).

The source driver 30 selects gamma reference voltages of input RGB data in response to control signals input from the timing controller 20, and converts the data voltage Vdata generated by the selected gamma reference voltage into a liquid crystal panel. 2) to control the rotation angle of the liquid crystal molecules.

The gate driver 40 turns on / off the TFTs arranged on the liquid crystal panel 10 in response to the clock signal D_CLKs B_CLKs and control signals input from the timing controller 20. outputs a gate driving signal Vg for controlling the thin film transistors TFT on the liquid crystal panel 10 by sequentially enabling the gate lines GL1 to GLn on the liquid crystal panel 10. Each line is sequentially driven so that analog image signals supplied from the source driver 30 are applied to the pixels connected to the TFTs.

3 is a view for explaining a method of providing clock signals D_CLKs and B_CLKs applied to a liquid crystal display for driving black data insertion according to the prior art, wherein the gate driver 40 displays an image in the case of a BDI gate embedded circuit. The first clock signal D_CLKs and the second clock signal B_CLKs for outputting the gate driving signal for black data insertion are separately provided from the timing controller 20. Are provided. In this case, since the first clock signal D_CLKs and the second clock signal B_CLKs are required to have a 4-phase clock signal according to the shift register circuit mounted in the gate driver 40, different phases are used. It is generally composed of a plurality of clock signals having a).

Each of the clock signals D_CLKs B_CLKs is provided to the gate driver 40 after converting the signal level through the level shifter 50.

However, referring to the signal timing diagram of FIG. 4, the first clock signal D_CLKs and the second clock signal B_CLKs are each blank time at which a clock signal is not provided at the second half of one frame display time. It has (blanc time: BT_D, BT_B) respectively. The blank times BT_D and BT_B are generated by the timing controller 20 in accordance with the timing of providing the clock signal CLK provided from the external driving system. The blank time BT_D and BT_B generate the voltages of the other clock signals. The problem of raising the level arises.

This problem is caused by the load variation of the clock signal input channel of the level shifter (50 in FIG. 3), and is applied to the first clock signal blank time BT_D to which the first clock signal D_CLKs is not applied. Generation of the first clock signal D_CLKs during the second clock signal blank time BT_B to which the operation power is biased to the generation channel of the second clock signal B_CLKs and to which the second clock signal B_CLKs is not applied. The operating power is biased in the channel, causing a voltage rise of about several hundred mV.

The voltage level distortion of the clock signal D_CLKs B_CLKs eventually causes abnormal output of the gate driving voltage Vg generated by the gate driver 40, leading to problems such as distortion of the display image.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and to improve the distortion of the clock signal provided to the gate driver to generate the gate driving signal to display a normal image in the liquid crystal display device.

In order to achieve the above object, the present invention provides a first clock signal for controlling the generation of a gate driving signal for writing image data on a liquid crystal panel and a second for controlling the generation of a gate driving signal for writing black data. A driving circuit for a liquid crystal display device which outputs clock signals for one vertical display time (1 vertical time) is proposed.

The driving circuit is characterized in that the timing controller.

In the driving circuit, the first clock signal and the second clock signal may be signals composed of a plurality of clock signals each having a different phase.

In the drive circuit, the drive circuit is characterized in that to perform the operation continuously.

In addition, the present invention provides one frame display for each of the first clock signal for controlling the generation of the gate driving signal for writing image data on the liquid crystal panel and the second clock signal for controlling the generation of the gate driving signal for writing black data. The present invention provides a method of driving a liquid crystal display, characterized in that for outputting for one vertical time.

In the driving method, the first clock signal and the second clock signal may be configured of a plurality of clock signals each having a different phase.

In addition, the driving method is characterized in that it is carried out continuously.

In addition, the present invention provides a first clock signal for controlling the generation of the gate driving signal for writing image data on the liquid crystal panel and a second clock signal for controlling the generation of the gate driving signal for writing black data (1V-). 4H) to 1V, where V is a frame display time and H is a horizontal time.

The driving method is characterized in that it is carried out continuously.

According to the present invention, the gate driver provides a clock signal having a normal voltage level, thereby providing a stable display quality without distortion of an image.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a signal timing diagram illustrating a method of driving a liquid crystal display according to the present invention, and illustrates a method of providing clock signals D_CLKs and B_CLKs applied to a liquid crystal display for driving black data insertion.

Reference to the configuration of FIG. 1 and FIG. 3 is repeated for the purpose of this invention.

In the driving method of the liquid crystal display according to the present invention, the timing control unit 20 is provided from the timing controller 20 to the gate driver 40 to improve the clock signal voltage level. The first clock signal D_CLKs for the output of Vg and the second clock signal B_CLKs for the output of the gate drive signal Vg for inserting the black data are respectively displayed in one frame display time. Change the signal to be continuously supplied for 1V).

That is, the timing controller 20 outputs the first clock signal D_CLKs and the second clock signal B_CLKs, but continuously outputs without a blank period. This can be implemented through logic changes that are programmed and implemented inside the module.

At this time, since the first clock signal D_CLKs and the second clock signal B_CLKs are required to have a plurality of clock signals according to the shift register circuit mounted in the gate driver 40, different phases are used. Naturally, it is composed of a plurality of clock signals having a.

As described above, when the clock signals D_CLKs B_CLKs are continuously provided without a blank time, load variations between operating channels in the level shifter 50 of FIG. It is possible to provide the gate driver 40 with the clock signals D_CLKs and B_CLKs without an abnormal voltage rise. Therefore, the gate driving signal Vg output from the gate driver 40 to the liquid crystal panel 10 is also provided as a normal signal having a stable voltage level, thereby improving distortion of an image.

If the concept of the present invention is applied to an actual liquid crystal display device, the blank time (BT_D and BT_B of FIG. 4) as described in the related art may be set within 4 horizontal periods (4H) at most. The effects of the present invention described with reference to FIG. 5 will be seen.

1 is a configuration diagram schematically showing a configuration of a liquid crystal display device for driving black data insertion according to the prior art;

FIG. 2 is a view schematically illustrating a configuration of a liquid crystal panel among the components of FIG. 1.

3 is a diagram illustrating a method of providing clock signals D_CLKs and B_CLKs applied to a liquid crystal display for driving black data insertion according to the prior art.

4 is a signal timing diagram illustrating a first clock signal D_CLKs and a second clock signal B_CLKs according to the related art.

5 is a signal timing diagram illustrating a method of driving a liquid crystal display according to the present invention.

<Brief description of the main parts of the drawing>

D_CLKs: First Clock Signal B_CLKs: Second Clock Signal

Claims (9)

The first clock signal for controlling the generation of the gate driving signal for writing image data on the liquid crystal panel and the second clock signal for controlling the generation of the gate driving signal for writing black data are respectively displayed in one frame time. Driving circuit for liquid crystal display The method according to claim 1, The driving circuit is a driving circuit for a liquid crystal display device, characterized in that the timing controller The method according to claim 1, The first clock signal and the second clock signal are driving signals for the liquid crystal display device, characterized in that the signal consisting of a plurality of clock signals having different phases, respectively. The method according to claim 1, The driving circuit is a driving circuit for a liquid crystal display, characterized in that to perform the operation continuously. The first clock signal for controlling the generation of the gate driving signal for writing image data on the liquid crystal panel and the second clock signal for controlling the generation of the gate driving signal for writing black data are respectively displayed in one frame time. Driving method of the liquid crystal display device The method according to claim 5, And the first clock signal and the second clock signal are composed of a plurality of clock signals each having a different phase. The method according to claim 5, The driving method is a driving method of the liquid crystal display device, characterized in that is carried out continuously. The first clock signal for controlling generation of the gate driving signal for writing image data on the liquid crystal panel and the second clock signal for controlling generation of the gate driving signal for writing black data are respectively (1V-4H) to 1V. Output, Wherein V is the frame display time (Vertical time) and H is a horizontal period (Horizontal time) driving method of the liquid crystal display device The method of claim 8, The driving method is a driving method of the liquid crystal display device, characterized in that is carried out continuously.

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