KR20070070639A - Driving apparatus of display device - Google Patents

Abstract

A driving apparatus of a display device is provided to minimize flicker due to insufficient charge rate of a pixel voltage by simultaneously displaying impulsive images on plural pixel columns. A driving apparatus includes plural gate and data lines(G1~Gn,D1~Dm), a data driver(500), and a gate driver(400). The gate lines deliver a gate-on voltage(Von) to pixels(PX). The data lines deliver a normal data voltage and an impulsive data voltage to the pixels. The data driver applies the normal data voltage and the impulsive data voltage to the data lines. The gate driver applies the gate-on voltage to the gate lines. The data driver changes the voltage level of all the data lines to a predetermined level before applying the normal data voltage and the impulsive data voltage to the data lines.

Description

Drive device for display device {DRIVING APPARATUS OF DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a waveform diagram of a vertical synchronization start signal and a gate signal used in a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a data driver in an embodiment of the present invention.

FIG. 5 is an example of a circuit diagram of the charge sharing unit shown in FIG. 4.

FIG. 6 is a waveform diagram of an operation of a charge sharing unit according to an embodiment of the present invention and a voltage flowing through any one data line by a load signal, a gate clock signal, and an inversion signal.

The present invention relates to a driving device of a display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

However, when the polarity of the data voltage is inverted as described above, the response speed of the liquid crystal molecules is slow, so that it takes a long time for the liquid crystal capacitor to charge to the target voltage, so that the screen is not clear and blurring occurs. In order to solve this problem, an impulsive driving method for inserting a black screen for a short time has been developed.

Such an impulsive driving method applies an impulsive data voltage, such as a black data voltage, to a pixel at regular intervals, in addition to an impulsive emission type that turns off the backlight lamp at a predetermined period and turns the entire screen black. There is a cyclic resetting type.

However, these methods still do not compensate for the late response speed of the liquid crystal, but also the response speed of the backlight lamp is slow, there is a problem that the image quality is deteriorated due to the afterimage of the screen or flicker occurs. In particular, in the case of applying the impulsive data voltage, the application time of the normal data voltage is reduced.

Therefore, the technical problem to be achieved by the present invention is to solve this problem, to prevent the degradation of the image quality due to impulsive driving.

According to an aspect of the present invention, there is provided a driving apparatus of a display device including a plurality of pixels, the driving apparatus of a display device having a plurality of pixels, the plurality of gate lines transferring a gate-on voltage to the pixels, and a normal data voltage. A plurality of data lines for transmitting an impulsive data voltage to the pixel, a data driver for applying the normal data voltage and the impulsive data voltage to the data line, and a gate driver for applying the gate-on voltage to the gate line And the data driver changes the voltage levels of all data lines to a predetermined level before the normal data voltage or the impulsive data voltage is applied to the data lines.

The data driver preferably includes a charge sharing unit for connecting all data lines according to a control signal.

The charge sharing unit may include a plurality of transmission gates connected between adjacent data lines to change a conduction state according to the control signal.

The driving device of the display device according to the above feature may further include a signal controller configured to output a plurality of data control signals to control the operation of the data driver.

The plurality of control signals may include a load signal LOAD for applying the data voltage to the data line.

The transmission gate preferably includes a control terminal and an inversion control terminal, and the load signal is applied as the control signal to the control terminal.

It is preferable that the pulse width of the load signal is 1 kHz or more.

The driving apparatus of the display device according to the above-mentioned feature converts M bundle image signals into M bundle normal image data and generates one bundle of impulsive image data to generate the normal image data and the impulsive image data. And a signal controller to transmit to the data driver (M is a natural number), wherein the data driver generates the normal data voltage based on the normal image data and generates the impulsive data voltage based on the impulsive image data. Good to do.

The normal image data is sequentially applied to M pixel rows, and the impulsive data is simultaneously applied to M pixel rows.

The gate on voltage may include a first gate on voltage for applying the normal data voltage and a second gate on voltage for applying the impulsive data voltage.

It is preferable that the application times of the first and second gate-on voltages are the same.

The impulsive data voltage may be a black data voltage.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A driving device of the liquid crystal display device, which is an embodiment of the driving device of the display device of the present invention, will now be described in detail with reference to the accompanying drawings.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the i-th (i = 1, 2, ..., n) gate line G _i and the j-th (j = 1, 2, ..., m) data line D _The pixel PX connected to _j ) includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. . Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input video signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

In addition, the data processing of the signal controller 600 includes application of impulsive image data as well as application of normal image data based on the input image signals R, G, and B. To this end, the signal controller 600 converts the normal image data of the M pixel rows based on the input image signals R, G, and B of the M pixel rows, and then applies the M pixel rows to the M pixel rows normally. Image data is generated and impulsive image data is simultaneously applied to M different pixel rows for substantially the same time as when the normal image data is applied (M is a natural number). In this case, since M impulsive image data are simultaneously applied, the time for applying M normal image data and M impulsive image data is the same as the time for applying (M + 1) normal image data. The impulsive image data may be black gray or may exhibit any constant luminance.

Therefore, the frequency of the horizontal synchronization start signal STH is (M + 1) / M times the frequency of the horizontal synchronization signal Hsync. In addition, the frequency of the data clock signal HCLK to which the output video signal DAT is synchronized may be (M + 1) / M times the frequency of the main clock MCLK to which the input video signals R, G, and B are synchronized. Here, M may be 6 as an example. As a result, the output image signal DAT has one of a number of values (or gray levels) determined as a digital signal, and is used for impulsive driving and normal image data generated based on the input image signals R, G, and B. Contains impulsive video data.

Such data processing of the signal controller 600 will be described in detail below.

The gate control signal CONT1 defines the scan start signal STV indicating the start of scanning, the gate clock signal CPV controlling the output timing of the gate on voltage Von, and the durations of the gate on voltage Von. An output enable signal OE or the like.

The data control signal CONT2 is configured to apply a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of transmission of the output image signal DAT for one row of pixels PX. The load signal LOAD and the data clock signal HCLK are included. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives an output image signal DAT for one row of pixels PX and corresponds to each output image signal DAT. By selecting the gray scale voltage, the output image signal DAT is converted into an analog data signal and then applied to the corresponding data lines D ₁ -D _m . The analog data signal includes a normal data voltage corresponding to the normal image data and an impulsive data voltage corresponding to the impulsive image data. The impulsive data voltage may be a black data voltage.

In addition, the data driver 500 performs charge sharing before the data voltage is applied to the data lines D ₁ -D _m in synchronization with the load signal LOAD. The operation of the data driver 500 will be described next.

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

By repeating this process in units of one input horizontal period (also referred to as 1H and equal to one period of the horizontal sync signal Hsync), the gate-on voltage Von is sequentially applied to all the gate lines G ₁ -G _n . ) By applying a normal image data voltage and an impulsive data voltage to all the pixels PX, thereby displaying a normal image and an impulsive image corresponding to one frame once for one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the normal image data voltage flowing through one data line is changed and the polarity of the normal image data voltage flowing through the adjacent data line is changed to the data driver 500 according to the characteristics of the inversion signal RVS within one frame. The state of the inverted signal RVS to be controlled is controlled (point inversion). The polarity of the impulsive data voltage also changes according to the inversion signal RVS, but may be any polarity.

Next, the impulsive driving of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a waveform diagram of various signals used in a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 3 illustrates a vertical synchronization signal Vsync, image data DAT, and gate signals g1, g2, ... It is shown.

As described above, the image data DAT includes normal image data N ₁₁ -N ₁₆ , N _21, ... And impulsive image data I, and is a predetermined number, for example, six pixel rows. After the normal data voltage corresponding to the normal image data (N ₁₁ -N ₁₆ , N _21, ...) is sequentially applied in units, the impulsive corresponding to the impulsive image data I is applied to the other six pixel rows. The data voltage is applied at the same time.

Thus, during 6H, six normal data voltages and six impulsive data voltages are applied to the corresponding data lines D ₁ -D _m . The data voltage inversion method is one point inversion.

As shown in FIG. 3, the gate-on voltages Von applied to the respective gate signals g1, g2,... Correspond to the normal image data N ₁₁ -N ₁₆ , N _21, ... A first gate on voltage Von1 for applying a normal data voltage and a second gate on voltage Von2 for applying an impulsive data voltage corresponding to the impulsive image data I are included. As illustrated in FIG. 3, the output time of the first gate on voltage Von1 and the output time of the second gate on voltage Von2 are the same, but may be different from each other. At this time, the output time of the gate-on voltages Von1 and Von2 is called one output horizontal period 1H 'and is equal to one period of the data clock signal HCLK.

The impulsive driving will then be described.

When one frame starts according to the vertical synchronization signal Vsync, the first gate-on is applied to the gate signals g _1- g ₆ that are sequentially applied from the first gate line G ₁ to the sixth gate line G ₆ . The voltage Von1 is applied. As a result, during each 1H ′ in which the first gate-on voltage Von1 is output, the pixels connected to the first gate line G ₁ to the sixth gate line G ₆ in turn turn their normal image data N _11. Charge the normal data voltage corresponding to N ₁₆ ).

As such, when the normal data voltage corresponding to the normal image data (N ₁₁ -N ₁₆ ) corresponding to six consecutive pixel rows is charged, the (k + 1) th gate line (G _{k + 1} ) to (K + 6) th gate lines (G _{K + 6),} the second gate-on voltage (Von2) at the same time by applying, from during the next 1H '(k + 1) th gate lines _{(G k + 1) (K} + 6 in) th The pixels connected to the gate line G _{K + 6} charge an impulsive data voltage corresponding to the impulsive image data I.

Next, the first gate-on voltage Von1 is sequentially applied to the gate signals g _7- g ₁₂ applied from the seventh gate line G ₇ to the twelfth gate line G ₁₂ , and the corresponding gate line ( The pixels connected to G ₇ -G ₁₂ are sequentially charged with normal data voltages corresponding to their normal image data N ₂₁ -N ₂₆ . Subsequently, a second signal is applied to the gate signal g _{k + 7} −g _{k + 12} applied from the (k + 7) th gate line G _{k + 7} to the (K + 12) th gate line G _{K + 12} . By applying the gate-on voltage (Von2) at the same time, impulsive image data (pixels) connected to the (k + 7) th gate line (G _{k + 7} ) to the (K + 12) th gate line (G _{k + 12} ) The impulsive data voltage corresponding to I) is charged.

As such, a plurality of gate line sets GL1, GL2,..., Each of the gate lines G ₁ -G _n each consisting of six gate lines G ₁ -G ₆ , G ₇ -G ₁₂ , .. After dividing by, the normal image data (N ₁₁ -N ₁₆ , N ₂₁ -N ₂₆ , ...) from the first gate line set GL1 to the last gate line set so that the interval between adjacent gate line sets is maintained at 1H '. A normal data voltage corresponding to the normal image data (N ₁₁ -N ₁₆ , N ₂₁ -N ₂₆ , ...) to each gate line set GL1, GL2, ... After this is applied, impulsive image data every 6H 'intervals from the Kth gate line group GL _k to the (K-1) th gate line group GL _k-1 during 1H' when no normal data voltage is applied. An impulsive data voltage corresponding to I) is applied.

As a result, an impulsive image band having a width of six pixels is displayed while moving sequentially from the top to the bottom of the screen, thereby performing impulsive driving.

In FIG. 3, the operation has been described with reference to six pixel rows, but the number of the pixel rows can be changed, and the vertical width of the impulsive image band can also be changed. As described above, blurring can be prevented by displaying a normal image and an impulsive image, and a charging rate of the pixel voltage can be increased due to a relatively small increase in frequency for impulsive driving.

At this time, before the normal data voltage or the black data voltage is applied to the data voltages D ₁ -D _m , the data driver 500 connects all the data lines D ₁ -D _m in synchronization with the load signal LOAD. Charge sharing is performed. Next, the operation of the data driver 500 will be described in more detail with reference to FIGS. 4 to 6.

4 is a block diagram of a data driver according to an exemplary embodiment of the present invention, and FIG. 5 is an example of a circuit diagram of the charge sharing unit illustrated in FIG. 4. 6 is a waveform diagram of an operation of the charge sharing unit according to an embodiment of the present invention and a voltage flowing through any one data line by a load signal, a gate clock signal, and an inversion signal.

As illustrated in FIG. 4, the data driver 500 includes a shift register 510, a latch 520, a digital-to-analog converter 530, a buffer 540, and a charge sharing unit 550. As shown in FIG. 5, the charge sharing unit 550 includes a plurality of switching elements SC ₁ , SC ₂ ,..., SC _m-1 connected between adjacent data lines. Each switching element SC ₁ , SC ₂ ,..., SC _m-1 is a transmission gate having a control terminal and an inverting control terminal, and a load signal LOAD is applied to the control terminal.

When the horizontal register start signal STH is applied, the shift register unit 510 sequentially shifts the input image data DAT according to the data clock signal HCLK, thereby shifting a row of image data DAT to the latch 520. To pass. The shift register unit 510 includes a plurality of shift registers, shifts all of the image data DAT in charge of the shift register, and then sends a shift clock signal (not shown) to the next stage shift register to transfer the image data (DAT). ) Shift operation can be made. For this reason, the image data DAT of one pixel row is sequentially shifted to the shift register of the shift register unit 510.

The latch 520 outputs the image data DAT sequentially received from the shift register unit 510 to the digital-analog converter 530 according to the load signal LOAD.

The digital-to-analog converter 530 receives the gray voltage V _gm from the gray voltage generator 800 and receives a gray voltage having a positive value with respect to the common voltage V _com according to the inversion signal RVS. One of gray level voltages having a value is selected. Then, a gray voltage corresponding to each image data DAT is selected from the selected gray voltages, and the digital image data DAT is converted into a corresponding analog data voltage.

The buffer 540 sends the data voltage from the digital-to-analog converter 530 to the charge sharing unit 550.

As described above, the charge sharing unit 550 includes a transmission gate applied to the load signal LOAD to the control terminal. Therefore, as shown in FIG. 6, the transmission gates SC _1- SC _m-1 are in a conductive state while the load signal LOAD maintains a high level, so that all data lines D ₁ -D _m are connected to each other. Therefore, the voltage states of all the data lines D1-Dm become uniform to the predetermined voltage level V1, that is, charge sharing is performed. Then, when the load signal LOAD changes from a high level to a low level, that is, at the falling edge, a low level is applied to the control terminal of the transmission gates SC ₁ -SC _m-1 so that all of the transmission gates SC ₁ -SC _m- are applied. ₁ ) is changed from the conduction state to the non-conduction state, and the corresponding data voltage corresponding to the image data DAT is transmitted through the data lines D ₁ -D _m .

As a result, charge sharing occurs while the load signal LOAD maintains a high level, and the voltage DOUT of the data line maintains a predetermined voltage V1 level during charge sharing, and then the normal data voltage of the corresponding polarity is maintained. It changes to an impulsive data voltage. At this time, the width of the load signal LOAD that maintains the high level is preferably wide enough so that sufficient charge sharing is performed so that the voltage DOUT of the data line can be stably changed to the voltage V1 of a predetermined level. Do. In addition, the time from the low level to the high level when the load signal LOAD changes from the low level to the high level is preferably about 1.8 ms.

In this case, the polarity of the data voltage is changed from the low level to the high level so that when the image data DAT of one pixel row is applied to the digital-analog converter 530 at the latch 520, the inversion signal RVS is applied. Determined according to the level of. That is, when the level of the inversion signal RVS is a high level, the polarity of the data voltage has a positive polarity, and when the level of the inversion signal RVS is a low level, the polarity of the data voltage is a negative polarity. However, the present invention is not limited thereto and vice versa.

Thus, the data lines (D ₁ -D _m) on a predetermined voltage level of all of the data lines by the charge sharing unit 550 before the data voltage corresponding to the image data (DAT) (D ₁ -D _m) Charge sharing is made to be uniform to the voltage V1 level. Therefore, even if the data lines D1-Dm are applied with the normal data voltage or the impulsive data voltage, all of them change from the same voltage level to the corresponding voltage. Therefore, all pixels have the impulsive data voltage or the image data voltage under the same charging condition. Charging operation is performed.

As a result, the defects in the bright horizontal stripes caused by the charging conditions when the black data is charged to the normal data voltage are more favorable than the charging conditions when the normal data voltage is charged to the normal data voltage of opposite polarity are reduced. That is, when the normal data voltage is applied after the impulsive data voltage is applied for the impulsive driving, or when the normal data voltage is changed to the opposite polarity, the data voltage is changed to the corresponding data voltage at the same voltage level V1. The charging operation of the pixel is performed under the same charging condition.

According to the present invention, since the driving time for displaying the impulsive image can be relatively reduced by simultaneously displaying the impulsive image on the plurality of pixel rows, the charging rate of the pixel voltage can be increased, thereby generating flicker due to insufficient charging rate. Can be minimized.

In addition, charge sharing is performed before the data voltage corresponding to the image data is transferred to the data line, and the charging operation is performed at the same data voltage after the impulsive data voltage is applied or after the normal data voltage is applied. Image quality defects such as

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (12)

A driving device of a display device having a plurality of pixels, A plurality of gate lines transferring a gate-on voltage to the pixel, A plurality of data lines for transferring a normal data voltage and an impulsive data voltage to the pixel; A data driver for applying the normal data voltage and the impulsive data voltage to the data line; A gate driver configured to apply the gate-on voltage to the gate line Including, The data driver changes the voltage levels of all data lines to a predetermined level before the normal data voltage or the impulsive data voltage is applied to the data lines. Drive device for display device. In claim 1, And the data driver comprises a charge sharing unit for connecting all data lines according to a control signal. In claim 2, And the charge sharing unit includes a plurality of transmission gates connected between adjacent data lines to change a conduction state according to the control signal. In claim 3, And a signal controller configured to output a plurality of data control signals to control operations of the data driver. In claim 4, The plurality of control signals include a load signal (LOAD) to apply the data voltage to the data line. In the fifth, And the transmission gate includes a control terminal and an inversion control terminal, and the load signal is applied to the control terminal as the control signal. In the sixth, And a pulse width of the load signal is 1 kHz or more. In claim 1, And a signal controller configured to convert M bundles of image signals into M bundles of normal image data, generate one bundle of impulsive image data, and transmit the normal image data and the impulsive image data to the data driver. (M is a natural number) The data driver generates the normal data voltage based on the normal image data and generates the impulsive data voltage based on the impulsive image data. Drive device for display device. In claim 8, And the normal image data is sequentially applied to M pixel rows, and the impulsive data is simultaneously applied to M pixel rows. In claim 9, And the gate on voltage includes a first gate on voltage for applying the normal data voltage and a second gate on voltage for applying the impulsive data voltage. In claim 10, Driving time of the display device is the same as the application time of the first and second gate-on voltage. In claim 1, And the impulsive data voltage is a black data voltage.

Images