KR20060125223A - Display device, driving apparatus of display device, and integrated circuit - Google Patents

Abstract

A display device, and a driving apparatus and an integrated circuit thereof are provided to prevent the defect of image quality due to the difference between the charging rates of pixels by reflecting the distortion of common voltage generated by changing the polarity for the voltage of a data signal, to the voltage of the data signal output to the pixel. A driving apparatus of a display device includes a plurality of pixels(PX); a reference gradation voltage generator(800) generating plural reference gradation voltages; and a data driving unit(500) generating plural gradation voltages on the basis of plural reference gradation voltages, selecting the gradation voltage corresponding to an image signal(R,G,B) applied from the outside, from the gradation voltages, and applying a data signal to the pixels by adding common voltage(Vcom) to the selected gradation voltage.

Description

Display device, driving device and integrated circuit of display device {DISPLAY DEVICE, DRIVING APPARATUS OF DISPLAY DEVICE, AND INTEGRATED CIRCUIT}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a data driving integrated circuit according to an embodiment of the present invention.

4 is a voltage waveform diagram of a data signal output to a pixel when a common voltage is distorted according to an exemplary embodiment of the present invention.

The present invention relates to a display device, a drive device for the display device, and an integrated circuit.

BACKGROUND ART A liquid crystal display (LCD) includes a lower and upper display panel including a pixel electrode and a common electrode, respectively, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes of the lower panel are arranged in a matrix form and connected to a switching element such as a thin film transistor (TFT) to receive data signals one by one in sequence. The common electrode is formed over the entire surface of the upper panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, the voltage polarity of the data signal with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel in order to prevent degradation caused by an electric field applied in one direction for a long time.

However, this change in polarity can lead to unfavorable phenomena such as flicker, flickering of the screen, or crosstalk, which causes vertical or horizontal stripes.

The flicker phenomenon is caused by a kickback voltage generated by the switching characteristics of the switching element, and is a phenomenon in which the common voltage applied to the common electrode is lowered by the kickback voltage. Therefore, reducing the size of the kickback voltage can reduce the flicker phenomenon and improve the image quality of the liquid crystal display.

The crosstalk phenomenon is caused by a parasitic capacitor generated between the pixel and the data line which is connected to the switching element and transmits a data signal to the switching element. This is because the crosstalk also changes in common voltage when the voltage polarity of the data signal changes, and the charging rate of the pixel varies according to the change of the common voltage.

As described above, distortion of the common voltage synchronized with the change in voltage polarity of the data signal causes poor image quality of the liquid crystal display.

Accordingly, an object of the present invention is to improve the image quality of a display device.

According to an aspect of the present invention, a driving device of a display device includes a plurality of pixels, a reference gray voltage generator for generating a plurality of reference gray voltages, and a plurality of gray levels based on the plurality of reference gray voltages. A data driver generates a voltage, selects a gray voltage corresponding to an image signal applied from the outside among the plurality of gray voltages, and adds a common voltage to the selected gray voltage to apply the data signal to the pixel.

The data driver includes a shift register, a data register for sequentially receiving and storing the video signal, and an operation region selected by the shift register, and a latch for sequentially storing the video signal stored in the data register in the selected operation region. A digital analog converter which generates the plurality of gray voltages based on the plurality of reference gray voltages, selects and outputs a gray voltage corresponding to the video signal from the latch, and a voltage common to the gray voltages from the digital analog converter And a common voltage applying unit for outputting the sum, and an output buffer for temporarily storing the voltage from the common voltage applying unit and outputting the voltage to the pixel.

In an integrated circuit according to another aspect of the present invention, an operation region is sequentially selected by a shift register, a data register for receiving and storing video signals from the outside, and the shift register, and stored in the data register in the selected operation region. A latch for sequentially storing the stored video signal, a digital analog converter for generating the plurality of analog voltages based on a plurality of reference voltages from the outside, selecting and outputting a voltage corresponding to the video signal from the latch, and the digital It includes a common voltage applying unit for outputting the sum of the common voltage from the outside to the voltage from the analog converter.

The common voltage applying unit preferably includes an output voltage from the digital analog converter and a voltage follower to which the common voltage is applied.

The integrated circuit may further include an output buffer configured to temporarily store and output a voltage from the common voltage applying unit.

According to another aspect of the present invention, a display device includes a display panel in which a plurality of pixels are arranged in a matrix, a reference gray voltage generator for generating a plurality of reference gray voltages, and a plurality of gray voltages based on the plurality of reference gray voltages. And a data driver for selecting a gray voltage corresponding to an image signal applied from the outside among the plurality of gray voltages, and adding a common voltage to the selected gray voltage to apply to the pixel.

The data driver includes a shift register, a data register for sequentially receiving and storing the video signal, and an operation region selected by the shift register, and a latch for sequentially storing the video signal stored in the data register in the selected operation region. A digital analog converter which generates the plurality of gray voltages based on the plurality of reference gray voltages, selects and outputs a gray voltage corresponding to the video signal from the latch, and a voltage common to the gray voltages from the digital analog converter And a common voltage applying unit for outputting the sum, and an output buffer for temporarily storing the voltage from the common voltage applying unit and outputting the voltage to the pixel.

Preferably, the common voltage applying unit includes an output signal from the digital analog converter and a voltage follower to which the common voltage is applied.

In this case, the display device may be a liquid crystal display device.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device, a driving device of the display device, and an integrated circuit according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings. A display device according to an exemplary embodiment of the present invention will be described with reference to a liquid crystal display.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. And a reference gray voltage generator 800 connected to 500, and a signal controller 600 for controlling them.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor C _LC , and a storage capacitor C _ST connected thereto. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 191 of the lower panel 100 and a common electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 191 and 270. It functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 191 of the lower panel 100 and a common electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 191 and 270. It functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the reference gray voltage generator 800 generates two sets of reference gray voltages related to the transmittance of the pixel PX. One of the pairs has a positive value (hereinafter referred to as positive polarity) with respect to the common voltage Vcom, and the other suit has a negative value (hereinafter referred to as negative polarity).

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 receives a common voltage Vcom, and includes a plurality of data driver integrated circuits 540 connected to the signal controller 600 and the reference gray voltage generator 800, respectively. Each data driving integrated circuit 540 is connected to a corresponding data line among the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and is based on the reference gray voltage from the reference gray voltage generator 800. A plurality of gray voltages are generated, a corresponding gray voltage is selected among the plurality of gray voltages, and applied to the data lines D ₁ -D _m connected as data signals. The data driver 500 will be described in detail below.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines a duration of the gate-on voltage Von.

The data control signal CONT2 is a load signal LOAD for applying a data signal to the horizontal synchronization start signal STH indicating the start of the transmission of the image signal for one row of pixels PX and the data lines D ₁ -D _m . ) And a data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included. In addition, the data control signal CONT2 may further include a plurality of signals SEL0, SEL1, and SHL for controlling the operation of the data driver 500.

According to the data control signal CONT2 from the signal controller 600, each data driver integrated circuit 540 of the data driver 500 receives the digital image signal DAT for one row of pixels PX, After generating a plurality of gray voltages based on the reference gray voltages from the reference gray voltage generator 800, the gray level voltages corresponding to the digital video signals DAT are selected from the gray voltages, thereby the digital video signal DAT. Is converted into an analog data signal and then applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all gate lines G ₁ -G _n ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, the data driver according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a block diagram of a data driving integrated circuit according to an exemplary embodiment of the present invention, and FIG. 4 is a voltage waveform diagram of a data signal output to a pixel when a common voltage is distorted according to an exemplary embodiment of the present invention.

The plurality of data driver integrated circuits 540 included in the data driver 500 have the same structure.

As shown in FIG. 3, the data driver integrated circuit 540 includes a data register 41 and a data clock signal HCLK to which the video signal DAT and the data clock signal HCLK are applied from the signal controller 600. ) And a shift register 42 and a shift register 42 to which a plurality of control signals SHL, SEL0 and SEL1 are applied, and a latch 43 and a latch 43 to which a load signal LOAD is applied. Connected to the digital analog converter 44 and the digital analog converter 44 to which the reference gray voltage GR1-GRp and the inverted signal RVS from the reference gray voltage generator 800 are applied. ) Is connected to the common voltage applying unit 45, to which the common voltage applying unit 45 is applied, and an output buffer 46 to which the inversion signal RVS is applied.

The common voltage applying unit 45 is connected to each output terminal of the digital-to-analog converter 44, and the non-inverting terminal (+) to which the common voltage Vcom from the outside is applied and the inverting terminal (-) connected to the output terminal. A plurality of operational amplifiers OP is provided, wherein the operational amplifiers OP function as a voltage follower.

The image signal DAT applied to the shift register 41 may be transmitted by reduced swing differential signaling (RSDS).

The common voltage Vcom applied to the common voltage applying unit 45 is generated from a voltage generating circuit (not shown) or the like on a printed circuit board on which many electrical elements and the like are mounted. It may be applied through a dummy pad or the like of the data driving integrated circuit 450 which is not connected to and is electrically floating.

The operation of the data driving integrated circuit 540 according to the exemplary embodiment of the present invention having the above structure is as follows.

When the video signal DAT is applied from the signal controller 600 in accordance with the data clock signal HCK, the data register 41 sequentially stores the applied video signal DAT.

The shift register 42 determines the function of the start pulse input / output terminals DIO1 and DIO2 in accordance with the state of the shift direction control signal SEL to determine the shift direction of the shift register 42. As an example, when the shift direction control signal SHL is in the high level H "state, the start pulse input / output terminal DIO1 functions as an input pin of a start pulse (not shown) instructing the start of the operation of the shift register 42 and starts. The pulse input / output terminal DIO2 functions as an output pin of the start pulse. Of course, the functions of the start pulse input / output terminals DIO1 and DIO2 are changed when the shift direction control signal SHL is in the low level L ″ state.

When the shifting direction of the shift register 42 is determined according to the shift direction control signal SEL in this manner, the shift register 42 outputs an enable signal to the first output terminal in synchronization with the data clock signal HCLK. The area of the latch 43 is selected, and at this time, the data register 41 outputs the stored video signal DAT to the latch 43 to store the video signal DAT in the selected area.

In this way, the shift register 42 shifts the positions of the output terminals to which the enable signal is output in synchronization with the data clock signal HCK one by one, and thus the area of the latch 43 to be selected is also shifted in turn so that all the latches 43 The video signal DAT from the data register 41 is sequentially stored in the () area. At this time, the control signals SEL0 and SEL1 are output selection signals, respectively, and the output terminals of the shift register 42 enabled are determined according to the states of these two signals SEL0 and SEL1.

When all the image signals DAT corresponding to the latch 43 of one data driving integrated circuit 540 are stored, the data driving integrated circuit 540 outputs a carry signal or the like to the next adjacent data driving integrated circuit. The same operation can then be made with the data driving integrated circuit. By this operation, one row of image signals DAT are divided and stored in the latches 43 of all the data driving integrated circuits 540.

When all the video signals DAT for one row are stored in the corresponding latch 43 by the operation of the shift register 42 and the data register 41, the state of the load signal LOAD applied from the signal control unit 600. For example, when switching from high level to low level, the video signal DAT stored in the latch 43 is simultaneously transmitted to the digital-to-analog converter 44.

The digital analog converter 44 generates a plurality of analog gray voltages based on the reference gray voltages GR1-GRp from the reference gray voltage generator 800, for example, using a resistor string composed of a plurality of resistors. The gray voltage corresponding to the image signal DAT transmitted from the plurality of gray voltages is selected and then output to the common voltage applying unit 45 as a data signal.

Since each operational amplifier OP of the common voltage applying unit 45 receives the data signal and the common voltage Vcom from the digital analog converter 44 simultaneously through the non-inverting terminal (+), the output buffer 46 The final data signal outputted through) becomes a signal obtained by adding the common voltage Vcom to the data signal applied from the digital-to-analog converter 44.

Thus, when the common voltage Vcom is distorted due to the voltage polarity inversion of the data signal, the final data signal outputs the voltage of the signal in which the waveform of the distorted common voltage Vcom is reflected.

That is, as shown in FIG. 4, the common voltage Vcom has a peak in the negative polarity direction when the polarity of the voltage Vd of the data signal is changed from positive polarity (+) to negative polarity (−). In the form of noise, on the contrary, when the change from the negative (-) to the positive (+), the noise in the form of a peak occurs in the positive direction. However, the noise of the common voltage Vcom is reflected in the voltage Vd of the data signal as it is, and the noise of the same shape as the peak generated in the common voltage Vcom occurs in the voltage Vd of the data signal.

Thus, even if the common voltage Vcom is distorted due to the polarity reversal of the voltage Vd of the data signal, the voltage Vd of the final data signal is also distorted by the distorted common voltage Vcom, so that it is substantially applied to the pixel. There is no change in the difference d between the voltage Vd and the common voltage Vcom of the final data signal. Therefore, the charge rate change of the pixel due to the distortion of the common voltage Vcom does not occur.

According to the present invention, since the distortion of the common voltage generated due to the polarity change of the data signal voltage is reflected in the voltage of the data signal output to the pixel, the image quality defect due to the difference in charge rate of the pixel due to the change in the common voltage Disappear. As a result, the image quality of the display device is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

A plurality of pixels, A reference gray voltage generator for generating a plurality of reference gray voltages, and Generate a plurality of gray voltages based on the plurality of reference gray voltages, select a gray voltage corresponding to an image signal applied from the outside among the plurality of gray voltages, and add a common voltage to the selected gray voltage as a data signal. Data driver applied to the pixel Driving device for a display device comprising a. In claim 1, The data driver, Shift register, A data register for sequentially receiving and storing the video signal; An operation region is sequentially selected by the shift register, and a latch for sequentially storing video signals stored in the data register in the selected operation region; A digital analog converter which generates the plurality of gray voltages based on the plurality of reference gray voltages, selects and outputs a gray voltage corresponding to the video signal from the latch; A common voltage applying unit which adds and outputs a common voltage to the gray voltage from the digital-to-analog converter, and An output buffer which temporarily stores the voltage from the common voltage applying unit and outputs the voltage to the pixel Driving device for a display device comprising a. In claim 2, And the common voltage applying unit is provided with an output signal from the digital analog converter and a voltage follower to which the common voltage is applied. Shift register, A data register that sequentially receives and stores a video signal from an external source, An operation region is sequentially selected by the shift register, and a latch for sequentially storing image signals stored in the data register in the selected operation region; A digital analog converter which generates the plurality of analog voltages based on a plurality of reference voltages from the outside, selects and outputs a voltage corresponding to the video signal from the latch, and Common voltage applying unit for outputting the sum of the voltage from the digital analog converter to the common voltage from the outside Integrated circuit comprising a. In claim 4, And the common voltage applying unit is provided with an output voltage from the digital analog converter and a voltage follower to which the common voltage is applied. In claim 4, And an output buffer for temporarily storing and outputting the voltage from the common voltage applying unit. A display panel in which a plurality of pixels are arranged in a matrix form, A reference gray voltage generator for generating a plurality of reference gray voltages, and A plurality of gray voltages are generated based on the plurality of reference gray voltages, a gray voltage corresponding to an image signal applied from the outside is selected from the plurality of gray voltages, and a common voltage is added to the selected gray voltages to the pixel. Applicable data driver Display device comprising a. In claim 7, The data driver, Shift register, A data register for sequentially receiving and storing the video signal; An operation region is sequentially selected by the shift register, and a latch for sequentially storing video signals stored in the data register in the selected operation region; A digital analog converter which generates the plurality of gray voltages based on the plurality of reference gray voltages, selects and outputs a gray voltage corresponding to the video signal from the latch; A common voltage applying unit which adds and outputs a common voltage to the gray voltage from the digital-to-analog converter, and An output buffer which temporarily stores the voltage from the common voltage applying unit and outputs the voltage to the pixel Display device comprising a. In claim 8, And the common voltage applying unit includes a voltage follower to which the output signal from the digital-to-analog converter and the common voltage are applied. The method according to any one of claims 7 to 9, And the display device is a liquid crystal display device.

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